0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/G2UL SoC
0004 *
0005 * Copyright (C) 2022 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/r9a07g043-cpg.h>
0010
0011 / {
0012 compatible = "renesas,r9a07g043";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 audio_clk1: audio-clk1 {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 /* This value must be overridden by boards that provide it */
0020 clock-frequency = <0>;
0021 };
0022
0023 audio_clk2: audio-clk2 {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 /* This value must be overridden by boards that provide it */
0027 clock-frequency = <0>;
0028 };
0029
0030 /* External CAN clock - to be overridden by boards that provide it */
0031 can_clk: can-clk {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <0>;
0035 };
0036
0037 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
0038 extal_clk: extal-clk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 /* This value must be overridden by the board */
0042 clock-frequency = <0>;
0043 };
0044
0045 cluster0_opp: opp-table-0 {
0046 compatible = "operating-points-v2";
0047 opp-shared;
0048
0049 opp-125000000 {
0050 opp-hz = /bits/ 64 <125000000>;
0051 opp-microvolt = <1100000>;
0052 clock-latency-ns = <300000>;
0053 };
0054 opp-250000000 {
0055 opp-hz = /bits/ 64 <250000000>;
0056 opp-microvolt = <1100000>;
0057 clock-latency-ns = <300000>;
0058 };
0059 opp-500000000 {
0060 opp-hz = /bits/ 64 <500000000>;
0061 opp-microvolt = <1100000>;
0062 clock-latency-ns = <300000>;
0063 };
0064 opp-1000000000 {
0065 opp-hz = /bits/ 64 <1000000000>;
0066 opp-microvolt = <1100000>;
0067 clock-latency-ns = <300000>;
0068 opp-suspend;
0069 };
0070 };
0071
0072 cpus {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 cpu0: cpu@0 {
0077 compatible = "arm,cortex-a55";
0078 reg = <0>;
0079 device_type = "cpu";
0080 #cooling-cells = <2>;
0081 next-level-cache = <&L3_CA55>;
0082 enable-method = "psci";
0083 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
0084 operating-points-v2 = <&cluster0_opp>;
0085 };
0086
0087 L3_CA55: cache-controller-0 {
0088 compatible = "cache";
0089 cache-unified;
0090 cache-size = <0x40000>;
0091 };
0092 };
0093
0094 psci {
0095 compatible = "arm,psci-1.0", "arm,psci-0.2";
0096 method = "smc";
0097 };
0098
0099 soc: soc {
0100 compatible = "simple-bus";
0101 interrupt-parent = <&gic>;
0102 #address-cells = <2>;
0103 #size-cells = <2>;
0104 ranges;
0105
0106 ssi0: ssi@10049c00 {
0107 compatible = "renesas,r9a07g043-ssi",
0108 "renesas,rz-ssi";
0109 reg = <0 0x10049c00 0 0x400>;
0110 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
0112 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
0113 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
0114 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0115 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
0116 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
0117 <&audio_clk1>, <&audio_clk2>;
0118 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0119 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
0120 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
0121 dma-names = "tx", "rx";
0122 power-domains = <&cpg>;
0123 #sound-dai-cells = <0>;
0124 status = "disabled";
0125 };
0126
0127 ssi1: ssi@1004a000 {
0128 compatible = "renesas,r9a07g043-ssi",
0129 "renesas,rz-ssi";
0130 reg = <0 0x1004a000 0 0x400>;
0131 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
0132 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
0133 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
0134 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
0135 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0136 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
0137 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
0138 <&audio_clk1>, <&audio_clk2>;
0139 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0140 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
0141 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
0142 dma-names = "tx", "rx";
0143 power-domains = <&cpg>;
0144 #sound-dai-cells = <0>;
0145 status = "disabled";
0146 };
0147
0148 ssi2: ssi@1004a400 {
0149 compatible = "renesas,r9a07g043-ssi",
0150 "renesas,rz-ssi";
0151 reg = <0 0x1004a400 0 0x400>;
0152 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
0154 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
0155 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
0156 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0157 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
0158 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
0159 <&audio_clk1>, <&audio_clk2>;
0160 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0161 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
0162 dmas = <&dmac 0x265f>;
0163 dma-names = "rt";
0164 power-domains = <&cpg>;
0165 #sound-dai-cells = <0>;
0166 status = "disabled";
0167 };
0168
0169 ssi3: ssi@1004a800 {
0170 compatible = "renesas,r9a07g043-ssi",
0171 "renesas,rz-ssi";
0172 reg = <0 0x1004a800 0 0x400>;
0173 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
0175 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
0176 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
0177 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
0178 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
0179 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
0180 <&audio_clk1>, <&audio_clk2>;
0181 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
0182 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
0183 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
0184 dma-names = "tx", "rx";
0185 power-domains = <&cpg>;
0186 #sound-dai-cells = <0>;
0187 status = "disabled";
0188 };
0189
0190 spi0: spi@1004ac00 {
0191 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
0192 reg = <0 0x1004ac00 0 0x400>;
0193 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
0194 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
0195 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
0196 interrupt-names = "error", "rx", "tx";
0197 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
0198 resets = <&cpg R9A07G043_RSPI0_RST>;
0199 power-domains = <&cpg>;
0200 num-cs = <1>;
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 status = "disabled";
0204 };
0205
0206 spi1: spi@1004b000 {
0207 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
0208 reg = <0 0x1004b000 0 0x400>;
0209 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
0211 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
0212 interrupt-names = "error", "rx", "tx";
0213 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
0214 resets = <&cpg R9A07G043_RSPI1_RST>;
0215 power-domains = <&cpg>;
0216 num-cs = <1>;
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219 status = "disabled";
0220 };
0221
0222 spi2: spi@1004b400 {
0223 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
0224 reg = <0 0x1004b400 0 0x400>;
0225 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
0226 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
0227 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
0228 interrupt-names = "error", "rx", "tx";
0229 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
0230 resets = <&cpg R9A07G043_RSPI2_RST>;
0231 power-domains = <&cpg>;
0232 num-cs = <1>;
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235 status = "disabled";
0236 };
0237
0238 scif0: serial@1004b800 {
0239 compatible = "renesas,scif-r9a07g043",
0240 "renesas,scif-r9a07g044";
0241 reg = <0 0x1004b800 0 0x400>;
0242 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
0243 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
0244 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
0245 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
0246 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
0247 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
0248 interrupt-names = "eri", "rxi", "txi",
0249 "bri", "dri", "tei";
0250 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
0251 clock-names = "fck";
0252 power-domains = <&cpg>;
0253 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
0254 status = "disabled";
0255 };
0256
0257 scif1: serial@1004bc00 {
0258 compatible = "renesas,scif-r9a07g043",
0259 "renesas,scif-r9a07g044";
0260 reg = <0 0x1004bc00 0 0x400>;
0261 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
0262 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
0265 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
0266 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
0267 interrupt-names = "eri", "rxi", "txi",
0268 "bri", "dri", "tei";
0269 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
0270 clock-names = "fck";
0271 power-domains = <&cpg>;
0272 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
0273 status = "disabled";
0274 };
0275
0276 scif2: serial@1004c000 {
0277 compatible = "renesas,scif-r9a07g043",
0278 "renesas,scif-r9a07g044";
0279 reg = <0 0x1004c000 0 0x400>;
0280 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
0281 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
0282 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
0283 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
0284 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
0285 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
0286 interrupt-names = "eri", "rxi", "txi",
0287 "bri", "dri", "tei";
0288 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
0289 clock-names = "fck";
0290 power-domains = <&cpg>;
0291 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
0292 status = "disabled";
0293 };
0294
0295 scif3: serial@1004c400 {
0296 compatible = "renesas,scif-r9a07g043",
0297 "renesas,scif-r9a07g044";
0298 reg = <0 0x1004c400 0 0x400>;
0299 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
0300 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
0302 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
0303 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
0305 interrupt-names = "eri", "rxi", "txi",
0306 "bri", "dri", "tei";
0307 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
0308 clock-names = "fck";
0309 power-domains = <&cpg>;
0310 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
0311 status = "disabled";
0312 };
0313
0314 scif4: serial@1004c800 {
0315 compatible = "renesas,scif-r9a07g043",
0316 "renesas,scif-r9a07g044";
0317 reg = <0 0x1004c800 0 0x400>;
0318 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
0319 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
0320 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
0321 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
0322 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
0323 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
0324 interrupt-names = "eri", "rxi", "txi",
0325 "bri", "dri", "tei";
0326 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
0327 clock-names = "fck";
0328 power-domains = <&cpg>;
0329 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
0330 status = "disabled";
0331 };
0332
0333 sci0: serial@1004d000 {
0334 compatible = "renesas,r9a07g043-sci", "renesas,sci";
0335 reg = <0 0x1004d000 0 0x400>;
0336 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
0337 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
0338 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
0339 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
0340 interrupt-names = "eri", "rxi", "txi", "tei";
0341 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
0342 clock-names = "fck";
0343 power-domains = <&cpg>;
0344 resets = <&cpg R9A07G043_SCI0_RST>;
0345 status = "disabled";
0346 };
0347
0348 sci1: serial@1004d400 {
0349 compatible = "renesas,r9a07g043-sci", "renesas,sci";
0350 reg = <0 0x1004d400 0 0x400>;
0351 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
0352 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
0353 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
0354 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
0355 interrupt-names = "eri", "rxi", "txi", "tei";
0356 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
0357 clock-names = "fck";
0358 power-domains = <&cpg>;
0359 resets = <&cpg R9A07G043_SCI1_RST>;
0360 status = "disabled";
0361 };
0362
0363 canfd: can@10050000 {
0364 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
0365 reg = <0 0x10050000 0 0x8000>;
0366 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
0367 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
0368 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
0369 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
0370 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
0371 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
0372 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
0373 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
0374 interrupt-names = "g_err", "g_recc",
0375 "ch0_err", "ch0_rec", "ch0_trx",
0376 "ch1_err", "ch1_rec", "ch1_trx";
0377 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
0378 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
0379 <&can_clk>;
0380 clock-names = "fck", "canfd", "can_clk";
0381 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
0382 assigned-clock-rates = <50000000>;
0383 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
0384 <&cpg R9A07G043_CANFD_RSTC_N>;
0385 reset-names = "rstp_n", "rstc_n";
0386 power-domains = <&cpg>;
0387 status = "disabled";
0388
0389 channel0 {
0390 status = "disabled";
0391 };
0392 channel1 {
0393 status = "disabled";
0394 };
0395 };
0396
0397 i2c0: i2c@10058000 {
0398 #address-cells = <1>;
0399 #size-cells = <0>;
0400 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
0401 reg = <0 0x10058000 0 0x400>;
0402 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
0403 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
0404 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
0405 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
0406 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
0407 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
0408 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
0409 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0410 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0411 "naki", "ali", "tmoi";
0412 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
0413 clock-frequency = <100000>;
0414 resets = <&cpg R9A07G043_I2C0_MRST>;
0415 power-domains = <&cpg>;
0416 status = "disabled";
0417 };
0418
0419 i2c1: i2c@10058400 {
0420 #address-cells = <1>;
0421 #size-cells = <0>;
0422 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
0423 reg = <0 0x10058400 0 0x400>;
0424 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
0425 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
0426 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
0427 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
0428 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
0429 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
0430 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
0431 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
0432 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0433 "naki", "ali", "tmoi";
0434 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
0435 clock-frequency = <100000>;
0436 resets = <&cpg R9A07G043_I2C1_MRST>;
0437 power-domains = <&cpg>;
0438 status = "disabled";
0439 };
0440
0441 i2c2: i2c@10058800 {
0442 #address-cells = <1>;
0443 #size-cells = <0>;
0444 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
0445 reg = <0 0x10058800 0 0x400>;
0446 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
0447 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
0448 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
0449 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
0450 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
0451 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
0452 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
0453 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
0454 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0455 "naki", "ali", "tmoi";
0456 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
0457 clock-frequency = <100000>;
0458 resets = <&cpg R9A07G043_I2C2_MRST>;
0459 power-domains = <&cpg>;
0460 status = "disabled";
0461 };
0462
0463 i2c3: i2c@10058c00 {
0464 #address-cells = <1>;
0465 #size-cells = <0>;
0466 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
0467 reg = <0 0x10058c00 0 0x400>;
0468 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
0469 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
0470 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
0471 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
0472 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
0473 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
0474 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
0475 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
0476 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0477 "naki", "ali", "tmoi";
0478 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
0479 clock-frequency = <100000>;
0480 resets = <&cpg R9A07G043_I2C3_MRST>;
0481 power-domains = <&cpg>;
0482 status = "disabled";
0483 };
0484
0485 adc: adc@10059000 {
0486 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
0487 reg = <0 0x10059000 0 0x400>;
0488 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
0489 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
0490 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
0491 clock-names = "adclk", "pclk";
0492 resets = <&cpg R9A07G043_ADC_PRESETN>,
0493 <&cpg R9A07G043_ADC_ADRST_N>;
0494 reset-names = "presetn", "adrst-n";
0495 power-domains = <&cpg>;
0496 status = "disabled";
0497
0498 #address-cells = <1>;
0499 #size-cells = <0>;
0500
0501 channel@0 {
0502 reg = <0>;
0503 };
0504 channel@1 {
0505 reg = <1>;
0506 };
0507 };
0508
0509 tsu: thermal@10059400 {
0510 compatible = "renesas,r9a07g043-tsu",
0511 "renesas,rzg2l-tsu";
0512 reg = <0 0x10059400 0 0x400>;
0513 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
0514 resets = <&cpg R9A07G043_TSU_PRESETN>;
0515 power-domains = <&cpg>;
0516 #thermal-sensor-cells = <1>;
0517 };
0518
0519 sbc: spi@10060000 {
0520 compatible = "renesas,r9a07g043-rpc-if",
0521 "renesas,rzg2l-rpc-if";
0522 reg = <0 0x10060000 0 0x10000>,
0523 <0 0x20000000 0 0x10000000>,
0524 <0 0x10070000 0 0x10000>;
0525 reg-names = "regs", "dirmap", "wbuf";
0526 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
0527 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
0528 resets = <&cpg R9A07G043_SPI_RST>;
0529 power-domains = <&cpg>;
0530 #address-cells = <1>;
0531 #size-cells = <0>;
0532 status = "disabled";
0533 };
0534
0535 cpg: clock-controller@11010000 {
0536 compatible = "renesas,r9a07g043-cpg";
0537 reg = <0 0x11010000 0 0x10000>;
0538 clocks = <&extal_clk>;
0539 clock-names = "extal";
0540 #clock-cells = <2>;
0541 #reset-cells = <1>;
0542 #power-domain-cells = <0>;
0543 };
0544
0545 sysc: system-controller@11020000 {
0546 compatible = "renesas,r9a07g043-sysc";
0547 reg = <0 0x11020000 0 0x10000>;
0548 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0549 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0550 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0551 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0552 interrupt-names = "lpm_int", "ca55stbydone_int",
0553 "cm33stbyr_int", "ca55_deny";
0554 status = "disabled";
0555 };
0556
0557 pinctrl: pinctrl@11030000 {
0558 compatible = "renesas,r9a07g043-pinctrl";
0559 reg = <0 0x11030000 0 0x10000>;
0560 gpio-controller;
0561 #gpio-cells = <2>;
0562 gpio-ranges = <&pinctrl 0 0 152>;
0563 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
0564 power-domains = <&cpg>;
0565 resets = <&cpg R9A07G043_GPIO_RSTN>,
0566 <&cpg R9A07G043_GPIO_PORT_RESETN>,
0567 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
0568 };
0569
0570 dmac: dma-controller@11820000 {
0571 compatible = "renesas,r9a07g043-dmac",
0572 "renesas,rz-dmac";
0573 reg = <0 0x11820000 0 0x10000>,
0574 <0 0x11830000 0 0x10000>;
0575 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
0576 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
0577 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
0578 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
0579 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
0580 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
0581 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
0582 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
0583 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
0584 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
0585 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
0586 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
0587 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
0588 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
0589 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
0590 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
0591 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
0592 interrupt-names = "error",
0593 "ch0", "ch1", "ch2", "ch3",
0594 "ch4", "ch5", "ch6", "ch7",
0595 "ch8", "ch9", "ch10", "ch11",
0596 "ch12", "ch13", "ch14", "ch15";
0597 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
0598 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
0599 power-domains = <&cpg>;
0600 resets = <&cpg R9A07G043_DMAC_ARESETN>,
0601 <&cpg R9A07G043_DMAC_RST_ASYNC>;
0602 #dma-cells = <1>;
0603 dma-channels = <16>;
0604 };
0605
0606 gic: interrupt-controller@11900000 {
0607 compatible = "arm,gic-v3";
0608 #interrupt-cells = <3>;
0609 #address-cells = <0>;
0610 interrupt-controller;
0611 reg = <0x0 0x11900000 0 0x40000>,
0612 <0x0 0x11940000 0 0x60000>;
0613 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
0614 };
0615
0616 sdhi0: mmc@11c00000 {
0617 compatible = "renesas,sdhi-r9a07g043",
0618 "renesas,rcar-gen3-sdhi";
0619 reg = <0x0 0x11c00000 0 0x10000>;
0620 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0621 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0622 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
0623 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
0624 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
0625 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
0626 clock-names = "core", "clkh", "cd", "aclk";
0627 resets = <&cpg R9A07G043_SDHI0_IXRST>;
0628 power-domains = <&cpg>;
0629 status = "disabled";
0630 };
0631
0632 sdhi1: mmc@11c10000 {
0633 compatible = "renesas,sdhi-r9a07g043",
0634 "renesas,rcar-gen3-sdhi";
0635 reg = <0x0 0x11c10000 0 0x10000>;
0636 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0637 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0638 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
0639 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
0640 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
0641 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
0642 clock-names = "core", "clkh", "cd", "aclk";
0643 resets = <&cpg R9A07G043_SDHI1_IXRST>;
0644 power-domains = <&cpg>;
0645 status = "disabled";
0646 };
0647
0648 eth0: ethernet@11c20000 {
0649 compatible = "renesas,r9a07g043-gbeth",
0650 "renesas,rzg2l-gbeth";
0651 reg = <0 0x11c20000 0 0x10000>;
0652 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0653 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0654 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0655 interrupt-names = "mux", "fil", "arp_ns";
0656 phy-mode = "rgmii";
0657 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
0658 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
0659 <&cpg CPG_CORE R9A07G043_CLK_HP>;
0660 clock-names = "axi", "chi", "refclk";
0661 resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
0662 power-domains = <&cpg>;
0663 #address-cells = <1>;
0664 #size-cells = <0>;
0665 status = "disabled";
0666 };
0667
0668 eth1: ethernet@11c30000 {
0669 compatible = "renesas,r9a07g043-gbeth",
0670 "renesas,rzg2l-gbeth";
0671 reg = <0 0x11c30000 0 0x10000>;
0672 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0673 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0674 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0675 interrupt-names = "mux", "fil", "arp_ns";
0676 phy-mode = "rgmii";
0677 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
0678 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
0679 <&cpg CPG_CORE R9A07G043_CLK_HP>;
0680 clock-names = "axi", "chi", "refclk";
0681 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
0682 power-domains = <&cpg>;
0683 #address-cells = <1>;
0684 #size-cells = <0>;
0685 status = "disabled";
0686 };
0687
0688 phyrst: usbphy-ctrl@11c40000 {
0689 compatible = "renesas,r9a07g043-usbphy-ctrl",
0690 "renesas,rzg2l-usbphy-ctrl";
0691 reg = <0 0x11c40000 0 0x10000>;
0692 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
0693 resets = <&cpg R9A07G043_USB_PRESETN>;
0694 power-domains = <&cpg>;
0695 #reset-cells = <1>;
0696 status = "disabled";
0697 };
0698
0699 ohci0: usb@11c50000 {
0700 compatible = "generic-ohci";
0701 reg = <0 0x11c50000 0 0x100>;
0702 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0703 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0704 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
0705 resets = <&phyrst 0>,
0706 <&cpg R9A07G043_USB_U2H0_HRESETN>;
0707 phys = <&usb2_phy0 1>;
0708 phy-names = "usb";
0709 power-domains = <&cpg>;
0710 status = "disabled";
0711 };
0712
0713 ohci1: usb@11c70000 {
0714 compatible = "generic-ohci";
0715 reg = <0 0x11c70000 0 0x100>;
0716 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0717 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0718 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
0719 resets = <&phyrst 1>,
0720 <&cpg R9A07G043_USB_U2H1_HRESETN>;
0721 phys = <&usb2_phy1 1>;
0722 phy-names = "usb";
0723 power-domains = <&cpg>;
0724 status = "disabled";
0725 };
0726
0727 ehci0: usb@11c50100 {
0728 compatible = "generic-ehci";
0729 reg = <0 0x11c50100 0 0x100>;
0730 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0731 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0732 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
0733 resets = <&phyrst 0>,
0734 <&cpg R9A07G043_USB_U2H0_HRESETN>;
0735 phys = <&usb2_phy0 2>;
0736 phy-names = "usb";
0737 companion = <&ohci0>;
0738 power-domains = <&cpg>;
0739 status = "disabled";
0740 };
0741
0742 ehci1: usb@11c70100 {
0743 compatible = "generic-ehci";
0744 reg = <0 0x11c70100 0 0x100>;
0745 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0746 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0747 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
0748 resets = <&phyrst 1>,
0749 <&cpg R9A07G043_USB_U2H1_HRESETN>;
0750 phys = <&usb2_phy1 2>;
0751 phy-names = "usb";
0752 companion = <&ohci1>;
0753 power-domains = <&cpg>;
0754 status = "disabled";
0755 };
0756
0757 usb2_phy0: usb-phy@11c50200 {
0758 compatible = "renesas,usb2-phy-r9a07g043",
0759 "renesas,rzg2l-usb2-phy";
0760 reg = <0 0x11c50200 0 0x700>;
0761 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0762 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0763 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
0764 resets = <&phyrst 0>;
0765 #phy-cells = <1>;
0766 power-domains = <&cpg>;
0767 status = "disabled";
0768 };
0769
0770 usb2_phy1: usb-phy@11c70200 {
0771 compatible = "renesas,usb2-phy-r9a07g043",
0772 "renesas,rzg2l-usb2-phy";
0773 reg = <0 0x11c70200 0 0x700>;
0774 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0775 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0776 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
0777 resets = <&phyrst 1>;
0778 #phy-cells = <1>;
0779 power-domains = <&cpg>;
0780 status = "disabled";
0781 };
0782
0783 hsusb: usb@11c60000 {
0784 compatible = "renesas,usbhs-r9a07g043",
0785 "renesas,rza2-usbhs";
0786 reg = <0 0x11c60000 0 0x10000>;
0787 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
0788 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0789 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0790 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0791 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
0792 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
0793 resets = <&phyrst 0>,
0794 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
0795 renesas,buswait = <7>;
0796 phys = <&usb2_phy0 3>;
0797 phy-names = "usb";
0798 power-domains = <&cpg>;
0799 status = "disabled";
0800 };
0801
0802 wdt0: watchdog@12800800 {
0803 compatible = "renesas,r9a07g043-wdt",
0804 "renesas,rzg2l-wdt";
0805 reg = <0 0x12800800 0 0x400>;
0806 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
0807 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
0808 clock-names = "pclk", "oscclk";
0809 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0810 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0811 interrupt-names = "wdt", "perrout";
0812 resets = <&cpg R9A07G043_WDT0_PRESETN>;
0813 power-domains = <&cpg>;
0814 status = "disabled";
0815 };
0816
0817 wdt2: watchdog@12800400 {
0818 compatible = "renesas,r9a07g043-wdt",
0819 "renesas,rzg2l-wdt";
0820 reg = <0 0x12800400 0 0x400>;
0821 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
0822 <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
0823 clock-names = "pclk", "oscclk";
0824 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0825 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0826 interrupt-names = "wdt", "perrout";
0827 resets = <&cpg R9A07G043_WDT2_PRESETN>;
0828 power-domains = <&cpg>;
0829 status = "disabled";
0830 };
0831
0832 ostm0: timer@12801000 {
0833 compatible = "renesas,r9a07g043-ostm",
0834 "renesas,ostm";
0835 reg = <0x0 0x12801000 0x0 0x400>;
0836 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
0837 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
0838 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
0839 power-domains = <&cpg>;
0840 status = "disabled";
0841 };
0842
0843 ostm1: timer@12801400 {
0844 compatible = "renesas,r9a07g043-ostm",
0845 "renesas,ostm";
0846 reg = <0x0 0x12801400 0x0 0x400>;
0847 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
0848 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
0849 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
0850 power-domains = <&cpg>;
0851 status = "disabled";
0852 };
0853
0854 ostm2: timer@12801800 {
0855 compatible = "renesas,r9a07g043-ostm",
0856 "renesas,ostm";
0857 reg = <0x0 0x12801800 0x0 0x400>;
0858 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
0859 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
0860 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
0861 power-domains = <&cpg>;
0862 status = "disabled";
0863 };
0864 };
0865
0866 thermal-zones {
0867 cpu-thermal {
0868 polling-delay-passive = <250>;
0869 polling-delay = <1000>;
0870 thermal-sensors = <&tsu 0>;
0871 sustainable-power = <717>;
0872
0873 cooling-maps {
0874 map0 {
0875 trip = <&target>;
0876 cooling-device = <&cpu0 0 2>;
0877 contribution = <1024>;
0878 };
0879 };
0880
0881 trips {
0882 sensor_crit: sensor-crit {
0883 temperature = <125000>;
0884 hysteresis = <1000>;
0885 type = "critical";
0886 };
0887
0888 target: trip-point {
0889 temperature = <100000>;
0890 hysteresis = <1000>;
0891 type = "passive";
0892 };
0893 };
0894 };
0895 };
0896
0897 timer {
0898 compatible = "arm,armv8-timer";
0899 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0900 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0901 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0902 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0903 };
0904 };
