0001 // SPDX-License-Identifier: (GPL-2.0 or MIT)
0002 /*
0003 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e-2G
0004 *
0005 * Copyright (C) 2021 Glider bv
0006 *
0007 * Based on r8a77951-ulcb.dts
0008 *
0009 * Copyright (C) 2016 Renesas Electronics Corp.
0010 * Copyright (C) 2016 Cogent Embedded, Inc.
0011 */
0012
0013 /dts-v1/;
0014 #include "r8a779m1.dtsi"
0015 #include "ulcb.dtsi"
0016
0017 / {
0018 model = "Renesas H3ULCB board based on r8a779m1";
0019 compatible = "renesas,h3ulcb", "renesas,r8a779m1", "renesas,r8a7795";
0020
0021 memory@48000000 {
0022 device_type = "memory";
0023 /* first 128MB is reserved for secure area. */
0024 reg = <0x0 0x48000000 0x0 0x38000000>;
0025 };
0026
0027 memory@500000000 {
0028 device_type = "memory";
0029 reg = <0x5 0x00000000 0x0 0x40000000>;
0030 };
0031
0032 memory@600000000 {
0033 device_type = "memory";
0034 reg = <0x6 0x00000000 0x0 0x40000000>;
0035 };
0036
0037 memory@700000000 {
0038 device_type = "memory";
0039 reg = <0x7 0x00000000 0x0 0x40000000>;
0040 };
0041 };
0042
0043 &du {
0044 clocks = <&cpg CPG_MOD 724>,
0045 <&cpg CPG_MOD 723>,
0046 <&cpg CPG_MOD 722>,
0047 <&cpg CPG_MOD 721>,
0048 <&versaclock5 1>,
0049 <&versaclock5 3>,
0050 <&versaclock5 4>,
0051 <&versaclock5 2>;
0052 clock-names = "du.0", "du.1", "du.2", "du.3",
0053 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
0054 };
