0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the R-Car V4H (R8A779G0) SoC
0004 *
0005 * Copyright (C) 2022 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/power/r8a779g0-sysc.h>
0011
0012 / {
0013 compatible = "renesas,r8a779g0";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 a76_0: cpu@0 {
0022 compatible = "arm,cortex-a76";
0023 reg = <0>;
0024 device_type = "cpu";
0025 power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
0026 };
0027 };
0028
0029 extal_clk: extal {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 /* This value must be overridden by the board */
0033 clock-frequency = <0>;
0034 };
0035
0036 extalr_clk: extalr {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 /* This value must be overridden by the board */
0040 clock-frequency = <0>;
0041 };
0042
0043 pmu_a76 {
0044 compatible = "arm,cortex-a76-pmu";
0045 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
0046 };
0047
0048 /* External SCIF clock - to be overridden by boards that provide it */
0049 scif_clk: scif {
0050 compatible = "fixed-clock";
0051 #clock-cells = <0>;
0052 clock-frequency = <0>;
0053 };
0054
0055 soc: soc {
0056 compatible = "simple-bus";
0057 interrupt-parent = <&gic>;
0058 #address-cells = <2>;
0059 #size-cells = <2>;
0060 ranges;
0061
0062 cpg: clock-controller@e6150000 {
0063 compatible = "renesas,r8a779g0-cpg-mssr";
0064 reg = <0 0xe6150000 0 0x4000>;
0065 clocks = <&extal_clk>, <&extalr_clk>;
0066 clock-names = "extal", "extalr";
0067 #clock-cells = <2>;
0068 #power-domain-cells = <0>;
0069 #reset-cells = <1>;
0070 };
0071
0072 rst: reset-controller@e6160000 {
0073 compatible = "renesas,r8a779g0-rst";
0074 reg = <0 0xe6160000 0 0x4000>;
0075 };
0076
0077 sysc: system-controller@e6180000 {
0078 compatible = "renesas,r8a779g0-sysc";
0079 reg = <0 0xe6180000 0 0x4000>;
0080 #power-domain-cells = <1>;
0081 };
0082
0083 hscif0: serial@e6540000 {
0084 compatible = "renesas,hscif-r8a779g0",
0085 "renesas,rcar-gen4-hscif",
0086 "renesas,hscif";
0087 reg = <0 0xe6540000 0 96>;
0088 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
0089 clocks = <&cpg CPG_MOD 514>,
0090 <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
0091 <&scif_clk>;
0092 clock-names = "fck", "brg_int", "scif_clk";
0093 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
0094 resets = <&cpg 514>;
0095 status = "disabled";
0096 };
0097
0098 gic: interrupt-controller@f1000000 {
0099 compatible = "arm,gic-v3";
0100 #interrupt-cells = <3>;
0101 #address-cells = <0>;
0102 interrupt-controller;
0103 reg = <0x0 0xf1000000 0 0x20000>,
0104 <0x0 0xf1060000 0 0x110000>;
0105 interrupts = <GIC_PPI 9
0106 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0107 };
0108
0109 prr: chipid@fff00044 {
0110 compatible = "renesas,prr";
0111 reg = <0 0xfff00044 0 4>;
0112 };
0113 };
0114
0115 timer {
0116 compatible = "arm,armv8-timer";
0117 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0118 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0119 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0120 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0121 };
0122 };
