0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the V3H Starter Kit board
0004 *
0005 * Copyright (C) 2018 Renesas Electronics Corp.
0006 * Copyright (C) 2018 Cogent Embedded, Inc.
0007 */
0008
0009 /dts-v1/;
0010 #include "r8a77980.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012
0013 / {
0014 model = "Renesas V3H Starter Kit board";
0015 compatible = "renesas,v3hsk", "renesas,r8a77980";
0016
0017 aliases {
0018 serial0 = &scif0;
0019 ethernet0 = &gether;
0020 };
0021
0022 chosen {
0023 stdout-path = "serial0:115200n8";
0024 };
0025
0026 hdmi-out {
0027 compatible = "hdmi-connector";
0028 type = "a";
0029
0030 port {
0031 hdmi_con: endpoint {
0032 remote-endpoint = <&adv7511_out>;
0033 };
0034 };
0035 };
0036
0037 lvds-decoder {
0038 compatible = "thine,thc63lvd1024";
0039 vcc-supply = <&vcc3v3_d5>;
0040
0041 ports {
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044
0045 port@0 {
0046 reg = <0>;
0047 thc63lvd1024_in: endpoint {
0048 remote-endpoint = <&lvds0_out>;
0049 };
0050 };
0051
0052 port@2 {
0053 reg = <2>;
0054 thc63lvd1024_out: endpoint {
0055 remote-endpoint = <&adv7511_in>;
0056 };
0057 };
0058 };
0059 };
0060
0061 memory@48000000 {
0062 device_type = "memory";
0063 /* first 128MB is reserved for secure area. */
0064 reg = <0 0x48000000 0 0x78000000>;
0065 };
0066
0067 osc1_clk: osc1-clock {
0068 compatible = "fixed-clock";
0069 #clock-cells = <0>;
0070 clock-frequency = <148500000>;
0071 };
0072
0073 vcc1v8_d4: regulator-0 {
0074 compatible = "regulator-fixed";
0075 regulator-name = "VCC1V8_D4";
0076 regulator-min-microvolt = <1800000>;
0077 regulator-max-microvolt = <1800000>;
0078 regulator-boot-on;
0079 regulator-always-on;
0080 };
0081
0082 vcc3v3_d5: regulator-1 {
0083 compatible = "regulator-fixed";
0084 regulator-name = "VCC3V3_D5";
0085 regulator-min-microvolt = <3300000>;
0086 regulator-max-microvolt = <3300000>;
0087 regulator-boot-on;
0088 regulator-always-on;
0089 };
0090 };
0091
0092 &du {
0093 clocks = <&cpg CPG_MOD 724>,
0094 <&osc1_clk>;
0095 clock-names = "du.0", "dclkin.0";
0096 status = "okay";
0097 };
0098
0099 &extal_clk {
0100 clock-frequency = <16666666>;
0101 };
0102
0103 &extalr_clk {
0104 clock-frequency = <32768>;
0105 };
0106
0107 &gether {
0108 pinctrl-0 = <&gether_pins>;
0109 pinctrl-names = "default";
0110
0111 phy-mode = "rgmii";
0112 phy-handle = <&phy0>;
0113 renesas,no-ether-link;
0114 status = "okay";
0115
0116 phy0: ethernet-phy@0 {
0117 compatible = "ethernet-phy-id0022.1622",
0118 "ethernet-phy-ieee802.3-c22";
0119 reg = <0>;
0120 interrupt-parent = <&gpio4>;
0121 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
0122 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0123 };
0124 };
0125
0126 &i2c0 {
0127 pinctrl-0 = <&i2c0_pins>;
0128 pinctrl-names = "default";
0129
0130 status = "okay";
0131 clock-frequency = <400000>;
0132
0133 hdmi@39 {
0134 compatible = "adi,adv7511w";
0135 #sound-dai-cells = <0>;
0136 reg = <0x39>;
0137 interrupt-parent = <&gpio1>;
0138 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0139 avdd-supply = <&vcc1v8_d4>;
0140 dvdd-supply = <&vcc1v8_d4>;
0141 pvdd-supply = <&vcc1v8_d4>;
0142 bgvdd-supply = <&vcc1v8_d4>;
0143 dvdd-3v-supply = <&vcc3v3_d5>;
0144
0145 adi,input-depth = <8>;
0146 adi,input-colorspace = "rgb";
0147 adi,input-clock = "1x";
0148
0149 ports {
0150 #address-cells = <1>;
0151 #size-cells = <0>;
0152
0153 port@0 {
0154 reg = <0>;
0155 adv7511_in: endpoint {
0156 remote-endpoint = <&thc63lvd1024_out>;
0157 };
0158 };
0159
0160 port@1 {
0161 reg = <1>;
0162 adv7511_out: endpoint {
0163 remote-endpoint = <&hdmi_con>;
0164 };
0165 };
0166 };
0167 };
0168 };
0169
0170 &lvds0 {
0171 status = "okay";
0172
0173 ports {
0174 port@1 {
0175 lvds0_out: endpoint {
0176 remote-endpoint = <&thc63lvd1024_in>;
0177 };
0178 };
0179 };
0180 };
0181
0182 &pfc {
0183 gether_pins: gether {
0184 groups = "gether_mdio_a", "gether_rgmii",
0185 "gether_txcrefclk", "gether_txcrefclk_mega";
0186 function = "gether";
0187 };
0188
0189 i2c0_pins: i2c0 {
0190 groups = "i2c0";
0191 function = "i2c0";
0192 };
0193
0194 qspi0_pins: qspi0 {
0195 groups = "qspi0_ctrl", "qspi0_data4";
0196 function = "qspi0";
0197 };
0198
0199 scif0_pins: scif0 {
0200 groups = "scif0_data";
0201 function = "scif0";
0202 };
0203
0204 scif_clk_pins: scif_clk {
0205 groups = "scif_clk_b";
0206 function = "scif_clk";
0207 };
0208 };
0209
0210 &rpc {
0211 pinctrl-0 = <&qspi0_pins>;
0212 pinctrl-names = "default";
0213
0214 status = "okay";
0215
0216 flash@0 {
0217 compatible = "spansion,s25fs512s", "jedec,spi-nor";
0218 reg = <0>;
0219 spi-max-frequency = <50000000>;
0220 spi-rx-bus-width = <4>;
0221
0222 partitions {
0223 compatible = "fixed-partitions";
0224 #address-cells = <1>;
0225 #size-cells = <1>;
0226
0227 bootparam@0 {
0228 reg = <0x00000000 0x040000>;
0229 read-only;
0230 };
0231 cr7@40000 {
0232 reg = <0x00040000 0x080000>;
0233 read-only;
0234 };
0235 cert_header_sa3@c0000 {
0236 reg = <0x000c0000 0x080000>;
0237 read-only;
0238 };
0239 bl2@140000 {
0240 reg = <0x00140000 0x040000>;
0241 read-only;
0242 };
0243 cert_header_sa6@180000 {
0244 reg = <0x00180000 0x040000>;
0245 read-only;
0246 };
0247 bl31@1c0000 {
0248 reg = <0x001c0000 0x460000>;
0249 read-only;
0250 };
0251 uboot@640000 {
0252 reg = <0x00640000 0x0c0000>;
0253 read-only;
0254 };
0255 uboot-env@700000 {
0256 reg = <0x00700000 0x040000>;
0257 read-only;
0258 };
0259 dtb@740000 {
0260 reg = <0x00740000 0x080000>;
0261 };
0262 kernel@7c0000 {
0263 reg = <0x007c0000 0x1400000>;
0264 };
0265 user@1bc0000 {
0266 reg = <0x01bc0000 0x2440000>;
0267 };
0268 };
0269 };
0270 };
0271
0272 &rwdt {
0273 timeout-sec = <60>;
0274 status = "okay";
0275 };
0276
0277 &scif0 {
0278 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
0279 pinctrl-names = "default";
0280
0281 status = "okay";
0282 };
0283
0284 &scif_clk {
0285 clock-frequency = <14745600>;
0286 };
