0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the Eagle board with R-Car V3M
0004 *
0005 * Copyright (C) 2016-2017 Renesas Electronics Corp.
0006 * Copyright (C) 2017 Cogent Embedded, Inc.
0007 */
0008
0009 /dts-v1/;
0010 #include "r8a77970.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012
0013 / {
0014 model = "Renesas Eagle board based on r8a77970";
0015 compatible = "renesas,eagle", "renesas,r8a77970";
0016
0017 aliases {
0018 serial0 = &scif0;
0019 ethernet0 = &avb;
0020 };
0021
0022 chosen {
0023 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0024 stdout-path = "serial0:115200n8";
0025 };
0026
0027 d3p3: regulator-fixed {
0028 compatible = "regulator-fixed";
0029 regulator-name = "fixed-3.3V";
0030 regulator-min-microvolt = <3300000>;
0031 regulator-max-microvolt = <3300000>;
0032 regulator-boot-on;
0033 regulator-always-on;
0034 };
0035
0036 hdmi-out {
0037 compatible = "hdmi-connector";
0038 type = "a";
0039
0040 port {
0041 hdmi_con_out: endpoint {
0042 remote-endpoint = <&adv7511_out>;
0043 };
0044 };
0045 };
0046
0047 lvds-decoder {
0048 compatible = "thine,thc63lvd1024";
0049
0050 vcc-supply = <&d3p3>;
0051
0052 ports {
0053 #address-cells = <1>;
0054 #size-cells = <0>;
0055
0056 port@0 {
0057 reg = <0>;
0058 thc63lvd1024_in: endpoint {
0059 remote-endpoint = <&lvds0_out>;
0060 };
0061 };
0062
0063 port@2 {
0064 reg = <2>;
0065 thc63lvd1024_out: endpoint {
0066 remote-endpoint = <&adv7511_in>;
0067 };
0068 };
0069 };
0070 };
0071
0072 memory@48000000 {
0073 device_type = "memory";
0074 /* first 128MB is reserved for secure area. */
0075 reg = <0x0 0x48000000 0x0 0x38000000>;
0076 };
0077
0078 x1_clk: x1-clock {
0079 compatible = "fixed-clock";
0080 #clock-cells = <0>;
0081 clock-frequency = <148500000>;
0082 };
0083 };
0084
0085 &avb {
0086 pinctrl-0 = <&avb_pins>;
0087 pinctrl-names = "default";
0088
0089 renesas,no-ether-link;
0090 phy-handle = <&phy0>;
0091 rx-internal-delay-ps = <1800>;
0092 tx-internal-delay-ps = <2000>;
0093 status = "okay";
0094
0095 phy0: ethernet-phy@0 {
0096 compatible = "ethernet-phy-id0022.1622",
0097 "ethernet-phy-ieee802.3-c22";
0098 rxc-skew-ps = <1500>;
0099 reg = <0>;
0100 interrupt-parent = <&gpio1>;
0101 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
0102 reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
0103 };
0104 };
0105
0106 &canfd {
0107 pinctrl-0 = <&canfd0_pins>;
0108 pinctrl-names = "default";
0109 status = "okay";
0110
0111 channel0 {
0112 status = "okay";
0113 };
0114 };
0115
0116 &csi40 {
0117 status = "okay";
0118
0119 ports {
0120 port@0 {
0121 csi40_in: endpoint {
0122 clock-lanes = <0>;
0123 data-lanes = <1 2 3 4>;
0124 remote-endpoint = <&max9286_out0>;
0125 };
0126 };
0127 };
0128 };
0129
0130 &du {
0131 clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
0132 clock-names = "du.0", "dclkin.0";
0133 status = "okay";
0134 };
0135
0136 &extal_clk {
0137 clock-frequency = <16666666>;
0138 };
0139
0140 &extalr_clk {
0141 clock-frequency = <32768>;
0142 };
0143
0144 &i2c0 {
0145 pinctrl-0 = <&i2c0_pins>;
0146 pinctrl-names = "default";
0147
0148 status = "okay";
0149 clock-frequency = <400000>;
0150
0151 io_expander: gpio@20 {
0152 compatible = "onnn,pca9654";
0153 reg = <0x20>;
0154 gpio-controller;
0155 #gpio-cells = <2>;
0156 };
0157
0158 hdmi@39 {
0159 compatible = "adi,adv7511w";
0160 reg = <0x39>;
0161 interrupt-parent = <&gpio1>;
0162 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0163
0164 adi,input-depth = <8>;
0165 adi,input-colorspace = "rgb";
0166 adi,input-clock = "1x";
0167
0168 ports {
0169 #address-cells = <1>;
0170 #size-cells = <0>;
0171
0172 port@0 {
0173 reg = <0>;
0174 adv7511_in: endpoint {
0175 remote-endpoint = <&thc63lvd1024_out>;
0176 };
0177 };
0178
0179 port@1 {
0180 reg = <1>;
0181 adv7511_out: endpoint {
0182 remote-endpoint = <&hdmi_con_out>;
0183 };
0184 };
0185 };
0186 };
0187 };
0188
0189 &i2c3 {
0190 pinctrl-0 = <&i2c3_pins>;
0191 pinctrl-names = "default";
0192
0193 status = "okay";
0194 clock-frequency = <400000>;
0195
0196 gmsl0: gmsl-deserializer@48 {
0197 compatible = "maxim,max9286";
0198 reg = <0x48>;
0199
0200 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
0201 enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
0202
0203 ports {
0204 #address-cells = <1>;
0205 #size-cells = <0>;
0206
0207 port@0 {
0208 reg = <0>;
0209 };
0210
0211 port@1 {
0212 reg = <1>;
0213 };
0214
0215 port@2 {
0216 reg = <2>;
0217 };
0218
0219 port@3 {
0220 reg = <3>;
0221 };
0222
0223 port@4 {
0224 reg = <4>;
0225 max9286_out0: endpoint {
0226 clock-lanes = <0>;
0227 data-lanes = <1 2 3 4>;
0228 remote-endpoint = <&csi40_in>;
0229 };
0230 };
0231 };
0232
0233 i2c-mux {
0234 #address-cells = <1>;
0235 #size-cells = <0>;
0236
0237 i2c@0 {
0238 #address-cells = <1>;
0239 #size-cells = <0>;
0240 reg = <0>;
0241
0242 status = "disabled";
0243 };
0244
0245 i2c@1 {
0246 #address-cells = <1>;
0247 #size-cells = <0>;
0248 reg = <1>;
0249
0250 status = "disabled";
0251 };
0252
0253 i2c@2 {
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 reg = <2>;
0257
0258 status = "disabled";
0259 };
0260
0261 i2c@3 {
0262 #address-cells = <1>;
0263 #size-cells = <0>;
0264 reg = <3>;
0265
0266 status = "disabled";
0267 };
0268 };
0269 };
0270 };
0271
0272 &lvds0 {
0273 status = "okay";
0274
0275 ports {
0276 port@1 {
0277 lvds0_out: endpoint {
0278 remote-endpoint = <&thc63lvd1024_in>;
0279 };
0280 };
0281 };
0282 };
0283
0284 &pfc {
0285 avb_pins: avb0 {
0286 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
0287 function = "avb0";
0288 };
0289
0290 canfd0_pins: canfd0 {
0291 groups = "canfd0_data_a";
0292 function = "canfd0";
0293 };
0294
0295 i2c0_pins: i2c0 {
0296 groups = "i2c0";
0297 function = "i2c0";
0298 };
0299
0300 i2c3_pins: i2c3 {
0301 groups = "i2c3_a";
0302 function = "i2c3";
0303 };
0304
0305 qspi0_pins: qspi0 {
0306 groups = "qspi0_ctrl", "qspi0_data4";
0307 function = "qspi0";
0308 };
0309
0310 scif0_pins: scif0 {
0311 groups = "scif0_data";
0312 function = "scif0";
0313 };
0314 };
0315
0316 &rpc {
0317 pinctrl-0 = <&qspi0_pins>;
0318 pinctrl-names = "default";
0319
0320 status = "okay";
0321
0322 flash@0 {
0323 compatible = "spansion,s25fs512s", "jedec,spi-nor";
0324 reg = <0>;
0325 spi-max-frequency = <50000000>;
0326 spi-rx-bus-width = <4>;
0327
0328 partitions {
0329 compatible = "fixed-partitions";
0330 #address-cells = <1>;
0331 #size-cells = <1>;
0332
0333 bootparam@0 {
0334 reg = <0x00000000 0x040000>;
0335 read-only;
0336 };
0337 cr7@40000 {
0338 reg = <0x00040000 0x080000>;
0339 read-only;
0340 };
0341 cert_header_sa3@c0000 {
0342 reg = <0x000c0000 0x080000>;
0343 read-only;
0344 };
0345 bl2@140000 {
0346 reg = <0x00140000 0x040000>;
0347 read-only;
0348 };
0349 cert_header_sa6@180000 {
0350 reg = <0x00180000 0x040000>;
0351 read-only;
0352 };
0353 bl31@1c0000 {
0354 reg = <0x001c0000 0x460000>;
0355 read-only;
0356 };
0357 uboot@640000 {
0358 reg = <0x00640000 0x0c0000>;
0359 read-only;
0360 };
0361 uboot-env@700000 {
0362 reg = <0x00700000 0x040000>;
0363 read-only;
0364 };
0365 dtb@740000 {
0366 reg = <0x00740000 0x080000>;
0367 };
0368 kernel@7c0000 {
0369 reg = <0x007c0000 0x1400000>;
0370 };
0371 user@1bc0000 {
0372 reg = <0x01bc0000 0x2440000>;
0373 };
0374 };
0375 };
0376 };
0377
0378 &rwdt {
0379 timeout-sec = <60>;
0380 status = "okay";
0381 };
0382
0383 &scif0 {
0384 pinctrl-0 = <&scif0_pins>;
0385 pinctrl-names = "default";
0386
0387 status = "okay";
0388 };
