0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the r8a774a1 SoC
0004 *
0005 * Copyright (C) 2018 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
0011 #include <dt-bindings/power/r8a774a1-sysc.h>
0012
0013 #define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
0014
0015 / {
0016 compatible = "renesas,r8a774a1";
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 i2c0 = &i2c0;
0022 i2c1 = &i2c1;
0023 i2c2 = &i2c2;
0024 i2c3 = &i2c3;
0025 i2c4 = &i2c4;
0026 i2c5 = &i2c5;
0027 i2c6 = &i2c6;
0028 i2c7 = &iic_pmic;
0029 };
0030
0031 /*
0032 * The external audio clocks are configured as 0 Hz fixed frequency
0033 * clocks by default.
0034 * Boards that provide audio clocks should override them.
0035 */
0036 audio_clk_a: audio_clk_a {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <0>;
0040 };
0041
0042 audio_clk_b: audio_clk_b {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 clock-frequency = <0>;
0046 };
0047
0048 audio_clk_c: audio_clk_c {
0049 compatible = "fixed-clock";
0050 #clock-cells = <0>;
0051 clock-frequency = <0>;
0052 };
0053
0054 /* External CAN clock - to be overridden by boards that provide it */
0055 can_clk: can {
0056 compatible = "fixed-clock";
0057 #clock-cells = <0>;
0058 clock-frequency = <0>;
0059 };
0060
0061 cluster0_opp: opp-table-0 {
0062 compatible = "operating-points-v2";
0063 opp-shared;
0064
0065 opp-500000000 {
0066 opp-hz = /bits/ 64 <500000000>;
0067 opp-microvolt = <820000>;
0068 clock-latency-ns = <300000>;
0069 };
0070 opp-1000000000 {
0071 opp-hz = /bits/ 64 <1000000000>;
0072 opp-microvolt = <820000>;
0073 clock-latency-ns = <300000>;
0074 };
0075 opp-1500000000 {
0076 opp-hz = /bits/ 64 <1500000000>;
0077 opp-microvolt = <820000>;
0078 clock-latency-ns = <300000>;
0079 opp-suspend;
0080 };
0081 };
0082
0083 cluster1_opp: opp-table-1 {
0084 compatible = "operating-points-v2";
0085 opp-shared;
0086
0087 opp-800000000 {
0088 opp-hz = /bits/ 64 <800000000>;
0089 opp-microvolt = <820000>;
0090 clock-latency-ns = <300000>;
0091 };
0092 opp-1000000000 {
0093 opp-hz = /bits/ 64 <1000000000>;
0094 opp-microvolt = <820000>;
0095 clock-latency-ns = <300000>;
0096 };
0097 opp-1200000000 {
0098 opp-hz = /bits/ 64 <1200000000>;
0099 opp-microvolt = <820000>;
0100 clock-latency-ns = <300000>;
0101 };
0102 };
0103
0104 cpus {
0105 #address-cells = <1>;
0106 #size-cells = <0>;
0107
0108 cpu-map {
0109 cluster0 {
0110 core0 {
0111 cpu = <&a57_0>;
0112 };
0113 core1 {
0114 cpu = <&a57_1>;
0115 };
0116 };
0117
0118 cluster1 {
0119 core0 {
0120 cpu = <&a53_0>;
0121 };
0122 core1 {
0123 cpu = <&a53_1>;
0124 };
0125 core2 {
0126 cpu = <&a53_2>;
0127 };
0128 core3 {
0129 cpu = <&a53_3>;
0130 };
0131 };
0132 };
0133
0134 a57_0: cpu@0 {
0135 compatible = "arm,cortex-a57";
0136 reg = <0x0>;
0137 device_type = "cpu";
0138 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
0139 next-level-cache = <&L2_CA57>;
0140 enable-method = "psci";
0141 dynamic-power-coefficient = <854>;
0142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
0143 operating-points-v2 = <&cluster0_opp>;
0144 capacity-dmips-mhz = <1024>;
0145 #cooling-cells = <2>;
0146 };
0147
0148 a57_1: cpu@1 {
0149 compatible = "arm,cortex-a57";
0150 reg = <0x1>;
0151 device_type = "cpu";
0152 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
0153 next-level-cache = <&L2_CA57>;
0154 enable-method = "psci";
0155 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
0156 operating-points-v2 = <&cluster0_opp>;
0157 capacity-dmips-mhz = <1024>;
0158 #cooling-cells = <2>;
0159 };
0160
0161 a53_0: cpu@100 {
0162 compatible = "arm,cortex-a53";
0163 reg = <0x100>;
0164 device_type = "cpu";
0165 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
0166 next-level-cache = <&L2_CA53>;
0167 enable-method = "psci";
0168 #cooling-cells = <2>;
0169 dynamic-power-coefficient = <277>;
0170 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
0171 operating-points-v2 = <&cluster1_opp>;
0172 capacity-dmips-mhz = <560>;
0173 };
0174
0175 a53_1: cpu@101 {
0176 compatible = "arm,cortex-a53";
0177 reg = <0x101>;
0178 device_type = "cpu";
0179 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
0180 next-level-cache = <&L2_CA53>;
0181 enable-method = "psci";
0182 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
0183 operating-points-v2 = <&cluster1_opp>;
0184 capacity-dmips-mhz = <560>;
0185 };
0186
0187 a53_2: cpu@102 {
0188 compatible = "arm,cortex-a53";
0189 reg = <0x102>;
0190 device_type = "cpu";
0191 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
0192 next-level-cache = <&L2_CA53>;
0193 enable-method = "psci";
0194 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
0195 operating-points-v2 = <&cluster1_opp>;
0196 capacity-dmips-mhz = <560>;
0197 };
0198
0199 a53_3: cpu@103 {
0200 compatible = "arm,cortex-a53";
0201 reg = <0x103>;
0202 device_type = "cpu";
0203 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
0204 next-level-cache = <&L2_CA53>;
0205 enable-method = "psci";
0206 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
0207 operating-points-v2 = <&cluster1_opp>;
0208 capacity-dmips-mhz = <560>;
0209 };
0210
0211 L2_CA57: cache-controller-0 {
0212 compatible = "cache";
0213 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
0214 cache-unified;
0215 cache-level = <2>;
0216 };
0217
0218 L2_CA53: cache-controller-1 {
0219 compatible = "cache";
0220 power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
0221 cache-unified;
0222 cache-level = <2>;
0223 };
0224 };
0225
0226 extal_clk: extal {
0227 compatible = "fixed-clock";
0228 #clock-cells = <0>;
0229 /* This value must be overridden by the board */
0230 clock-frequency = <0>;
0231 };
0232
0233 extalr_clk: extalr {
0234 compatible = "fixed-clock";
0235 #clock-cells = <0>;
0236 /* This value must be overridden by the board */
0237 clock-frequency = <0>;
0238 };
0239
0240 /* External PCIe clock - can be overridden by the board */
0241 pcie_bus_clk: pcie_bus {
0242 compatible = "fixed-clock";
0243 #clock-cells = <0>;
0244 clock-frequency = <0>;
0245 };
0246
0247 pmu_a53 {
0248 compatible = "arm,cortex-a53-pmu";
0249 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0250 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0251 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0252 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0253 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
0254 };
0255
0256 pmu_a57 {
0257 compatible = "arm,cortex-a57-pmu";
0258 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0259 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0260 interrupt-affinity = <&a57_0>, <&a57_1>;
0261 };
0262
0263 psci {
0264 compatible = "arm,psci-1.0", "arm,psci-0.2";
0265 method = "smc";
0266 };
0267
0268 /* External SCIF clock - to be overridden by boards that provide it */
0269 scif_clk: scif {
0270 compatible = "fixed-clock";
0271 #clock-cells = <0>;
0272 clock-frequency = <0>;
0273 };
0274
0275 soc {
0276 compatible = "simple-bus";
0277 interrupt-parent = <&gic>;
0278 #address-cells = <2>;
0279 #size-cells = <2>;
0280 ranges;
0281
0282 rwdt: watchdog@e6020000 {
0283 compatible = "renesas,r8a774a1-wdt",
0284 "renesas,rcar-gen3-wdt";
0285 reg = <0 0xe6020000 0 0x0c>;
0286 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0287 clocks = <&cpg CPG_MOD 402>;
0288 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0289 resets = <&cpg 402>;
0290 status = "disabled";
0291 };
0292
0293 gpio0: gpio@e6050000 {
0294 compatible = "renesas,gpio-r8a774a1",
0295 "renesas,rcar-gen3-gpio";
0296 reg = <0 0xe6050000 0 0x50>;
0297 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0298 #gpio-cells = <2>;
0299 gpio-controller;
0300 gpio-ranges = <&pfc 0 0 16>;
0301 #interrupt-cells = <2>;
0302 interrupt-controller;
0303 clocks = <&cpg CPG_MOD 912>;
0304 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0305 resets = <&cpg 912>;
0306 };
0307
0308 gpio1: gpio@e6051000 {
0309 compatible = "renesas,gpio-r8a774a1",
0310 "renesas,rcar-gen3-gpio";
0311 reg = <0 0xe6051000 0 0x50>;
0312 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0313 #gpio-cells = <2>;
0314 gpio-controller;
0315 gpio-ranges = <&pfc 0 32 29>;
0316 #interrupt-cells = <2>;
0317 interrupt-controller;
0318 clocks = <&cpg CPG_MOD 911>;
0319 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0320 resets = <&cpg 911>;
0321 };
0322
0323 gpio2: gpio@e6052000 {
0324 compatible = "renesas,gpio-r8a774a1",
0325 "renesas,rcar-gen3-gpio";
0326 reg = <0 0xe6052000 0 0x50>;
0327 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0328 #gpio-cells = <2>;
0329 gpio-controller;
0330 gpio-ranges = <&pfc 0 64 15>;
0331 #interrupt-cells = <2>;
0332 interrupt-controller;
0333 clocks = <&cpg CPG_MOD 910>;
0334 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0335 resets = <&cpg 910>;
0336 };
0337
0338 gpio3: gpio@e6053000 {
0339 compatible = "renesas,gpio-r8a774a1",
0340 "renesas,rcar-gen3-gpio";
0341 reg = <0 0xe6053000 0 0x50>;
0342 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0343 #gpio-cells = <2>;
0344 gpio-controller;
0345 gpio-ranges = <&pfc 0 96 16>;
0346 #interrupt-cells = <2>;
0347 interrupt-controller;
0348 clocks = <&cpg CPG_MOD 909>;
0349 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0350 resets = <&cpg 909>;
0351 };
0352
0353 gpio4: gpio@e6054000 {
0354 compatible = "renesas,gpio-r8a774a1",
0355 "renesas,rcar-gen3-gpio";
0356 reg = <0 0xe6054000 0 0x50>;
0357 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0358 #gpio-cells = <2>;
0359 gpio-controller;
0360 gpio-ranges = <&pfc 0 128 18>;
0361 #interrupt-cells = <2>;
0362 interrupt-controller;
0363 clocks = <&cpg CPG_MOD 908>;
0364 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0365 resets = <&cpg 908>;
0366 };
0367
0368 gpio5: gpio@e6055000 {
0369 compatible = "renesas,gpio-r8a774a1",
0370 "renesas,rcar-gen3-gpio";
0371 reg = <0 0xe6055000 0 0x50>;
0372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0373 #gpio-cells = <2>;
0374 gpio-controller;
0375 gpio-ranges = <&pfc 0 160 26>;
0376 #interrupt-cells = <2>;
0377 interrupt-controller;
0378 clocks = <&cpg CPG_MOD 907>;
0379 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0380 resets = <&cpg 907>;
0381 };
0382
0383 gpio6: gpio@e6055400 {
0384 compatible = "renesas,gpio-r8a774a1",
0385 "renesas,rcar-gen3-gpio";
0386 reg = <0 0xe6055400 0 0x50>;
0387 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0388 #gpio-cells = <2>;
0389 gpio-controller;
0390 gpio-ranges = <&pfc 0 192 32>;
0391 #interrupt-cells = <2>;
0392 interrupt-controller;
0393 clocks = <&cpg CPG_MOD 906>;
0394 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0395 resets = <&cpg 906>;
0396 };
0397
0398 gpio7: gpio@e6055800 {
0399 compatible = "renesas,gpio-r8a774a1",
0400 "renesas,rcar-gen3-gpio";
0401 reg = <0 0xe6055800 0 0x50>;
0402 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0403 #gpio-cells = <2>;
0404 gpio-controller;
0405 gpio-ranges = <&pfc 0 224 4>;
0406 #interrupt-cells = <2>;
0407 interrupt-controller;
0408 clocks = <&cpg CPG_MOD 905>;
0409 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0410 resets = <&cpg 905>;
0411 };
0412
0413 pfc: pinctrl@e6060000 {
0414 compatible = "renesas,pfc-r8a774a1";
0415 reg = <0 0xe6060000 0 0x50c>;
0416 };
0417
0418 cmt0: timer@e60f0000 {
0419 compatible = "renesas,r8a774a1-cmt0",
0420 "renesas,rcar-gen3-cmt0";
0421 reg = <0 0xe60f0000 0 0x1004>;
0422 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0423 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0424 clocks = <&cpg CPG_MOD 303>;
0425 clock-names = "fck";
0426 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0427 resets = <&cpg 303>;
0428 status = "disabled";
0429 };
0430
0431 cmt1: timer@e6130000 {
0432 compatible = "renesas,r8a774a1-cmt1",
0433 "renesas,rcar-gen3-cmt1";
0434 reg = <0 0xe6130000 0 0x1004>;
0435 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0436 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0437 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0438 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0439 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0440 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0441 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0442 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0443 clocks = <&cpg CPG_MOD 302>;
0444 clock-names = "fck";
0445 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0446 resets = <&cpg 302>;
0447 status = "disabled";
0448 };
0449
0450 cmt2: timer@e6140000 {
0451 compatible = "renesas,r8a774a1-cmt1",
0452 "renesas,rcar-gen3-cmt1";
0453 reg = <0 0xe6140000 0 0x1004>;
0454 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
0455 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
0456 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
0458 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
0459 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
0460 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
0461 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
0462 clocks = <&cpg CPG_MOD 301>;
0463 clock-names = "fck";
0464 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0465 resets = <&cpg 301>;
0466 status = "disabled";
0467 };
0468
0469 cmt3: timer@e6148000 {
0470 compatible = "renesas,r8a774a1-cmt1",
0471 "renesas,rcar-gen3-cmt1";
0472 reg = <0 0xe6148000 0 0x1004>;
0473 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
0474 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
0475 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
0476 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
0477 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
0478 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
0479 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
0480 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
0481 clocks = <&cpg CPG_MOD 300>;
0482 clock-names = "fck";
0483 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0484 resets = <&cpg 300>;
0485 status = "disabled";
0486 };
0487
0488 cpg: clock-controller@e6150000 {
0489 compatible = "renesas,r8a774a1-cpg-mssr";
0490 reg = <0 0xe6150000 0 0x0bb0>;
0491 clocks = <&extal_clk>, <&extalr_clk>;
0492 clock-names = "extal", "extalr";
0493 #clock-cells = <2>;
0494 #power-domain-cells = <0>;
0495 #reset-cells = <1>;
0496 };
0497
0498 rst: reset-controller@e6160000 {
0499 compatible = "renesas,r8a774a1-rst";
0500 reg = <0 0xe6160000 0 0x018c>;
0501 };
0502
0503 sysc: system-controller@e6180000 {
0504 compatible = "renesas,r8a774a1-sysc";
0505 reg = <0 0xe6180000 0 0x0400>;
0506 #power-domain-cells = <1>;
0507 };
0508
0509 tsc: thermal@e6198000 {
0510 compatible = "renesas,r8a774a1-thermal";
0511 reg = <0 0xe6198000 0 0x100>,
0512 <0 0xe61a0000 0 0x100>,
0513 <0 0xe61a8000 0 0x100>;
0514 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
0515 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0516 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0517 clocks = <&cpg CPG_MOD 522>;
0518 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0519 resets = <&cpg 522>;
0520 #thermal-sensor-cells = <1>;
0521 };
0522
0523 intc_ex: interrupt-controller@e61c0000 {
0524 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
0525 #interrupt-cells = <2>;
0526 interrupt-controller;
0527 reg = <0 0xe61c0000 0 0x200>;
0528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0529 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0530 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0531 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0532 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0533 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
0534 clocks = <&cpg CPG_MOD 407>;
0535 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0536 resets = <&cpg 407>;
0537 };
0538
0539 tmu0: timer@e61e0000 {
0540 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
0541 reg = <0 0xe61e0000 0 0x30>;
0542 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0543 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0544 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0545 clocks = <&cpg CPG_MOD 125>;
0546 clock-names = "fck";
0547 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0548 resets = <&cpg 125>;
0549 status = "disabled";
0550 };
0551
0552 tmu1: timer@e6fc0000 {
0553 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
0554 reg = <0 0xe6fc0000 0 0x30>;
0555 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0556 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0557 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
0558 clocks = <&cpg CPG_MOD 124>;
0559 clock-names = "fck";
0560 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0561 resets = <&cpg 124>;
0562 status = "disabled";
0563 };
0564
0565 tmu2: timer@e6fd0000 {
0566 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
0567 reg = <0 0xe6fd0000 0 0x30>;
0568 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
0569 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
0570 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
0571 clocks = <&cpg CPG_MOD 123>;
0572 clock-names = "fck";
0573 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0574 resets = <&cpg 123>;
0575 status = "disabled";
0576 };
0577
0578 tmu3: timer@e6fe0000 {
0579 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
0580 reg = <0 0xe6fe0000 0 0x30>;
0581 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0582 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0583 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0584 clocks = <&cpg CPG_MOD 122>;
0585 clock-names = "fck";
0586 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0587 resets = <&cpg 122>;
0588 status = "disabled";
0589 };
0590
0591 tmu4: timer@ffc00000 {
0592 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
0593 reg = <0 0xffc00000 0 0x30>;
0594 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
0595 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
0596 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
0597 clocks = <&cpg CPG_MOD 121>;
0598 clock-names = "fck";
0599 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0600 resets = <&cpg 121>;
0601 status = "disabled";
0602 };
0603
0604 i2c0: i2c@e6500000 {
0605 #address-cells = <1>;
0606 #size-cells = <0>;
0607 compatible = "renesas,i2c-r8a774a1",
0608 "renesas,rcar-gen3-i2c";
0609 reg = <0 0xe6500000 0 0x40>;
0610 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
0611 clocks = <&cpg CPG_MOD 931>;
0612 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0613 resets = <&cpg 931>;
0614 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
0615 <&dmac2 0x91>, <&dmac2 0x90>;
0616 dma-names = "tx", "rx", "tx", "rx";
0617 i2c-scl-internal-delay-ns = <110>;
0618 status = "disabled";
0619 };
0620
0621 i2c1: i2c@e6508000 {
0622 #address-cells = <1>;
0623 #size-cells = <0>;
0624 compatible = "renesas,i2c-r8a774a1",
0625 "renesas,rcar-gen3-i2c";
0626 reg = <0 0xe6508000 0 0x40>;
0627 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
0628 clocks = <&cpg CPG_MOD 930>;
0629 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0630 resets = <&cpg 930>;
0631 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
0632 <&dmac2 0x93>, <&dmac2 0x92>;
0633 dma-names = "tx", "rx", "tx", "rx";
0634 i2c-scl-internal-delay-ns = <6>;
0635 status = "disabled";
0636 };
0637
0638 i2c2: i2c@e6510000 {
0639 #address-cells = <1>;
0640 #size-cells = <0>;
0641 compatible = "renesas,i2c-r8a774a1",
0642 "renesas,rcar-gen3-i2c";
0643 reg = <0 0xe6510000 0 0x40>;
0644 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
0645 clocks = <&cpg CPG_MOD 929>;
0646 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0647 resets = <&cpg 929>;
0648 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
0649 <&dmac2 0x95>, <&dmac2 0x94>;
0650 dma-names = "tx", "rx", "tx", "rx";
0651 i2c-scl-internal-delay-ns = <6>;
0652 status = "disabled";
0653 };
0654
0655 i2c3: i2c@e66d0000 {
0656 #address-cells = <1>;
0657 #size-cells = <0>;
0658 compatible = "renesas,i2c-r8a774a1",
0659 "renesas,rcar-gen3-i2c";
0660 reg = <0 0xe66d0000 0 0x40>;
0661 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
0662 clocks = <&cpg CPG_MOD 928>;
0663 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0664 resets = <&cpg 928>;
0665 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
0666 dma-names = "tx", "rx";
0667 i2c-scl-internal-delay-ns = <110>;
0668 status = "disabled";
0669 };
0670
0671 i2c4: i2c@e66d8000 {
0672 #address-cells = <1>;
0673 #size-cells = <0>;
0674 compatible = "renesas,i2c-r8a774a1",
0675 "renesas,rcar-gen3-i2c";
0676 reg = <0 0xe66d8000 0 0x40>;
0677 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0678 clocks = <&cpg CPG_MOD 927>;
0679 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0680 resets = <&cpg 927>;
0681 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
0682 dma-names = "tx", "rx";
0683 i2c-scl-internal-delay-ns = <110>;
0684 status = "disabled";
0685 };
0686
0687 i2c5: i2c@e66e0000 {
0688 #address-cells = <1>;
0689 #size-cells = <0>;
0690 compatible = "renesas,i2c-r8a774a1",
0691 "renesas,rcar-gen3-i2c";
0692 reg = <0 0xe66e0000 0 0x40>;
0693 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0694 clocks = <&cpg CPG_MOD 919>;
0695 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0696 resets = <&cpg 919>;
0697 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
0698 dma-names = "tx", "rx";
0699 i2c-scl-internal-delay-ns = <110>;
0700 status = "disabled";
0701 };
0702
0703 i2c6: i2c@e66e8000 {
0704 #address-cells = <1>;
0705 #size-cells = <0>;
0706 compatible = "renesas,i2c-r8a774a1",
0707 "renesas,rcar-gen3-i2c";
0708 reg = <0 0xe66e8000 0 0x40>;
0709 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0710 clocks = <&cpg CPG_MOD 918>;
0711 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0712 resets = <&cpg 918>;
0713 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
0714 dma-names = "tx", "rx";
0715 i2c-scl-internal-delay-ns = <6>;
0716 status = "disabled";
0717 };
0718
0719 iic_pmic: i2c@e60b0000 {
0720 #address-cells = <1>;
0721 #size-cells = <0>;
0722 compatible = "renesas,iic-r8a774a1",
0723 "renesas,rcar-gen3-iic",
0724 "renesas,rmobile-iic";
0725 reg = <0 0xe60b0000 0 0x425>;
0726 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0727 clocks = <&cpg CPG_MOD 926>;
0728 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0729 resets = <&cpg 926>;
0730 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
0731 dma-names = "tx", "rx";
0732 status = "disabled";
0733 };
0734
0735 hscif0: serial@e6540000 {
0736 compatible = "renesas,hscif-r8a774a1",
0737 "renesas,rcar-gen3-hscif",
0738 "renesas,hscif";
0739 reg = <0 0xe6540000 0 0x60>;
0740 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0741 clocks = <&cpg CPG_MOD 520>,
0742 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
0743 <&scif_clk>;
0744 clock-names = "fck", "brg_int", "scif_clk";
0745 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
0746 <&dmac2 0x31>, <&dmac2 0x30>;
0747 dma-names = "tx", "rx", "tx", "rx";
0748 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0749 resets = <&cpg 520>;
0750 status = "disabled";
0751 };
0752
0753 hscif1: serial@e6550000 {
0754 compatible = "renesas,hscif-r8a774a1",
0755 "renesas,rcar-gen3-hscif",
0756 "renesas,hscif";
0757 reg = <0 0xe6550000 0 0x60>;
0758 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0759 clocks = <&cpg CPG_MOD 519>,
0760 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
0761 <&scif_clk>;
0762 clock-names = "fck", "brg_int", "scif_clk";
0763 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
0764 <&dmac2 0x33>, <&dmac2 0x32>;
0765 dma-names = "tx", "rx", "tx", "rx";
0766 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0767 resets = <&cpg 519>;
0768 status = "disabled";
0769 };
0770
0771 hscif2: serial@e6560000 {
0772 compatible = "renesas,hscif-r8a774a1",
0773 "renesas,rcar-gen3-hscif",
0774 "renesas,hscif";
0775 reg = <0 0xe6560000 0 0x60>;
0776 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0777 clocks = <&cpg CPG_MOD 518>,
0778 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
0779 <&scif_clk>;
0780 clock-names = "fck", "brg_int", "scif_clk";
0781 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
0782 <&dmac2 0x35>, <&dmac2 0x34>;
0783 dma-names = "tx", "rx", "tx", "rx";
0784 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0785 resets = <&cpg 518>;
0786 status = "disabled";
0787 };
0788
0789 hscif3: serial@e66a0000 {
0790 compatible = "renesas,hscif-r8a774a1",
0791 "renesas,rcar-gen3-hscif",
0792 "renesas,hscif";
0793 reg = <0 0xe66a0000 0 0x60>;
0794 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0795 clocks = <&cpg CPG_MOD 517>,
0796 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
0797 <&scif_clk>;
0798 clock-names = "fck", "brg_int", "scif_clk";
0799 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
0800 dma-names = "tx", "rx";
0801 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0802 resets = <&cpg 517>;
0803 status = "disabled";
0804 };
0805
0806 hscif4: serial@e66b0000 {
0807 compatible = "renesas,hscif-r8a774a1",
0808 "renesas,rcar-gen3-hscif",
0809 "renesas,hscif";
0810 reg = <0 0xe66b0000 0 0x60>;
0811 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0812 clocks = <&cpg CPG_MOD 516>,
0813 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
0814 <&scif_clk>;
0815 clock-names = "fck", "brg_int", "scif_clk";
0816 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
0817 dma-names = "tx", "rx";
0818 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0819 resets = <&cpg 516>;
0820 status = "disabled";
0821 };
0822
0823 hsusb: usb@e6590000 {
0824 compatible = "renesas,usbhs-r8a774a1",
0825 "renesas,rcar-gen3-usbhs";
0826 reg = <0 0xe6590000 0 0x200>;
0827 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0828 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
0829 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
0830 <&usb_dmac1 0>, <&usb_dmac1 1>;
0831 dma-names = "ch0", "ch1", "ch2", "ch3";
0832 renesas,buswait = <11>;
0833 phys = <&usb2_phy0 3>;
0834 phy-names = "usb";
0835 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0836 resets = <&cpg 704>, <&cpg 703>;
0837 status = "disabled";
0838 };
0839
0840 usb2_clksel: clock-controller@e6590630 {
0841 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
0842 "renesas,rcar-gen3-usb2-clock-sel";
0843 reg = <0 0xe6590630 0 0x02>;
0844 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
0845 <&usb_extal_clk>, <&usb3s0_clk>;
0846 clock-names = "ehci_ohci", "hs-usb-if",
0847 "usb_extal", "usb_xtal";
0848 #clock-cells = <0>;
0849 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0850 resets = <&cpg 703>, <&cpg 704>;
0851 reset-names = "ehci_ohci", "hs-usb-if";
0852 status = "disabled";
0853 };
0854
0855 usb_dmac0: dma-controller@e65a0000 {
0856 compatible = "renesas,r8a774a1-usb-dmac",
0857 "renesas,usb-dmac";
0858 reg = <0 0xe65a0000 0 0x100>;
0859 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0860 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0861 interrupt-names = "ch0", "ch1";
0862 clocks = <&cpg CPG_MOD 330>;
0863 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0864 resets = <&cpg 330>;
0865 #dma-cells = <1>;
0866 dma-channels = <2>;
0867 };
0868
0869 usb_dmac1: dma-controller@e65b0000 {
0870 compatible = "renesas,r8a774a1-usb-dmac",
0871 "renesas,usb-dmac";
0872 reg = <0 0xe65b0000 0 0x100>;
0873 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0874 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0875 interrupt-names = "ch0", "ch1";
0876 clocks = <&cpg CPG_MOD 331>;
0877 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0878 resets = <&cpg 331>;
0879 #dma-cells = <1>;
0880 dma-channels = <2>;
0881 };
0882
0883 usb3_phy0: usb-phy@e65ee000 {
0884 compatible = "renesas,r8a774a1-usb3-phy",
0885 "renesas,rcar-gen3-usb3-phy";
0886 reg = <0 0xe65ee000 0 0x90>;
0887 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
0888 <&usb_extal_clk>;
0889 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
0890 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0891 resets = <&cpg 328>;
0892 #phy-cells = <0>;
0893 status = "disabled";
0894 };
0895
0896 dmac0: dma-controller@e6700000 {
0897 compatible = "renesas,dmac-r8a774a1",
0898 "renesas,rcar-dmac";
0899 reg = <0 0xe6700000 0 0x10000>;
0900 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
0901 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0902 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0903 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0904 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0905 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0906 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
0907 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
0908 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0909 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0910 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
0911 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0912 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0913 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0914 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
0915 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
0916 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
0917 interrupt-names = "error",
0918 "ch0", "ch1", "ch2", "ch3",
0919 "ch4", "ch5", "ch6", "ch7",
0920 "ch8", "ch9", "ch10", "ch11",
0921 "ch12", "ch13", "ch14", "ch15";
0922 clocks = <&cpg CPG_MOD 219>;
0923 clock-names = "fck";
0924 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0925 resets = <&cpg 219>;
0926 #dma-cells = <1>;
0927 dma-channels = <16>;
0928 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
0929 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
0930 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
0931 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
0932 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
0933 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
0934 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
0935 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
0936 };
0937
0938 dmac1: dma-controller@e7300000 {
0939 compatible = "renesas,dmac-r8a774a1",
0940 "renesas,rcar-dmac";
0941 reg = <0 0xe7300000 0 0x10000>;
0942 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
0943 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
0944 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
0945 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
0946 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
0947 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
0948 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
0949 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
0950 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
0951 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
0952 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
0953 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
0954 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
0955 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
0956 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
0957 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
0958 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
0959 interrupt-names = "error",
0960 "ch0", "ch1", "ch2", "ch3",
0961 "ch4", "ch5", "ch6", "ch7",
0962 "ch8", "ch9", "ch10", "ch11",
0963 "ch12", "ch13", "ch14", "ch15";
0964 clocks = <&cpg CPG_MOD 218>;
0965 clock-names = "fck";
0966 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
0967 resets = <&cpg 218>;
0968 #dma-cells = <1>;
0969 dma-channels = <16>;
0970 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
0971 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
0972 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
0973 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
0974 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
0975 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
0976 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
0977 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
0978 };
0979
0980 dmac2: dma-controller@e7310000 {
0981 compatible = "renesas,dmac-r8a774a1",
0982 "renesas,rcar-dmac";
0983 reg = <0 0xe7310000 0 0x10000>;
0984 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
0985 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
0986 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
0987 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
0988 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
0989 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
0990 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
0991 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
0992 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
0993 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
0994 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
0995 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
0996 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
0997 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
0998 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
0999 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1001 interrupt-names = "error",
1002 "ch0", "ch1", "ch2", "ch3",
1003 "ch4", "ch5", "ch6", "ch7",
1004 "ch8", "ch9", "ch10", "ch11",
1005 "ch12", "ch13", "ch14", "ch15";
1006 clocks = <&cpg CPG_MOD 217>;
1007 clock-names = "fck";
1008 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1009 resets = <&cpg 217>;
1010 #dma-cells = <1>;
1011 dma-channels = <16>;
1012 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1013 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1014 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1015 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1016 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1017 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1018 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1019 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1020 };
1021
1022 ipmmu_ds0: iommu@e6740000 {
1023 compatible = "renesas,ipmmu-r8a774a1";
1024 reg = <0 0xe6740000 0 0x1000>;
1025 renesas,ipmmu-main = <&ipmmu_mm 0>;
1026 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1027 #iommu-cells = <1>;
1028 };
1029
1030 ipmmu_ds1: iommu@e7740000 {
1031 compatible = "renesas,ipmmu-r8a774a1";
1032 reg = <0 0xe7740000 0 0x1000>;
1033 renesas,ipmmu-main = <&ipmmu_mm 1>;
1034 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1035 #iommu-cells = <1>;
1036 };
1037
1038 ipmmu_hc: iommu@e6570000 {
1039 compatible = "renesas,ipmmu-r8a774a1";
1040 reg = <0 0xe6570000 0 0x1000>;
1041 renesas,ipmmu-main = <&ipmmu_mm 2>;
1042 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1043 #iommu-cells = <1>;
1044 };
1045
1046 ipmmu_mm: iommu@e67b0000 {
1047 compatible = "renesas,ipmmu-r8a774a1";
1048 reg = <0 0xe67b0000 0 0x1000>;
1049 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1051 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1052 #iommu-cells = <1>;
1053 };
1054
1055 ipmmu_mp: iommu@ec670000 {
1056 compatible = "renesas,ipmmu-r8a774a1";
1057 reg = <0 0xec670000 0 0x1000>;
1058 renesas,ipmmu-main = <&ipmmu_mm 4>;
1059 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1060 #iommu-cells = <1>;
1061 };
1062
1063 ipmmu_pv0: iommu@fd800000 {
1064 compatible = "renesas,ipmmu-r8a774a1";
1065 reg = <0 0xfd800000 0 0x1000>;
1066 renesas,ipmmu-main = <&ipmmu_mm 5>;
1067 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1068 #iommu-cells = <1>;
1069 };
1070
1071 ipmmu_pv1: iommu@fd950000 {
1072 compatible = "renesas,ipmmu-r8a774a1";
1073 reg = <0 0xfd950000 0 0x1000>;
1074 renesas,ipmmu-main = <&ipmmu_mm 6>;
1075 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1076 #iommu-cells = <1>;
1077 };
1078
1079 ipmmu_vc0: iommu@fe6b0000 {
1080 compatible = "renesas,ipmmu-r8a774a1";
1081 reg = <0 0xfe6b0000 0 0x1000>;
1082 renesas,ipmmu-main = <&ipmmu_mm 8>;
1083 power-domains = <&sysc R8A774A1_PD_A3VC>;
1084 #iommu-cells = <1>;
1085 };
1086
1087 ipmmu_vi0: iommu@febd0000 {
1088 compatible = "renesas,ipmmu-r8a774a1";
1089 reg = <0 0xfebd0000 0 0x1000>;
1090 renesas,ipmmu-main = <&ipmmu_mm 9>;
1091 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1092 #iommu-cells = <1>;
1093 };
1094
1095 avb: ethernet@e6800000 {
1096 compatible = "renesas,etheravb-r8a774a1",
1097 "renesas,etheravb-rcar-gen3";
1098 reg = <0 0xe6800000 0 0x800>;
1099 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1115 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1118 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1119 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1120 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1121 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1123 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1124 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1125 "ch4", "ch5", "ch6", "ch7",
1126 "ch8", "ch9", "ch10", "ch11",
1127 "ch12", "ch13", "ch14", "ch15",
1128 "ch16", "ch17", "ch18", "ch19",
1129 "ch20", "ch21", "ch22", "ch23",
1130 "ch24";
1131 clocks = <&cpg CPG_MOD 812>;
1132 clock-names = "fck";
1133 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1134 resets = <&cpg 812>;
1135 phy-mode = "rgmii";
1136 rx-internal-delay-ps = <0>;
1137 tx-internal-delay-ps = <0>;
1138 iommus = <&ipmmu_ds0 16>;
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141 status = "disabled";
1142 };
1143
1144 can0: can@e6c30000 {
1145 compatible = "renesas,can-r8a774a1",
1146 "renesas,rcar-gen3-can";
1147 reg = <0 0xe6c30000 0 0x1000>;
1148 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&cpg CPG_MOD 916>,
1150 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1151 <&can_clk>;
1152 clock-names = "clkp1", "clkp2", "can_clk";
1153 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1154 assigned-clock-rates = <40000000>;
1155 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1156 resets = <&cpg 916>;
1157 status = "disabled";
1158 };
1159
1160 can1: can@e6c38000 {
1161 compatible = "renesas,can-r8a774a1",
1162 "renesas,rcar-gen3-can";
1163 reg = <0 0xe6c38000 0 0x1000>;
1164 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&cpg CPG_MOD 915>,
1166 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1167 <&can_clk>;
1168 clock-names = "clkp1", "clkp2", "can_clk";
1169 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1170 assigned-clock-rates = <40000000>;
1171 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1172 resets = <&cpg 915>;
1173 status = "disabled";
1174 };
1175
1176 canfd: can@e66c0000 {
1177 compatible = "renesas,r8a774a1-canfd",
1178 "renesas,rcar-gen3-canfd";
1179 reg = <0 0xe66c0000 0 0x8000>;
1180 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1182 interrupt-names = "ch_int", "g_int";
1183 clocks = <&cpg CPG_MOD 914>,
1184 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1185 <&can_clk>;
1186 clock-names = "fck", "canfd", "can_clk";
1187 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1188 assigned-clock-rates = <40000000>;
1189 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1190 resets = <&cpg 914>;
1191 status = "disabled";
1192
1193 channel0 {
1194 status = "disabled";
1195 };
1196
1197 channel1 {
1198 status = "disabled";
1199 };
1200 };
1201
1202 pwm0: pwm@e6e30000 {
1203 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1204 reg = <0 0xe6e30000 0 0x8>;
1205 #pwm-cells = <2>;
1206 clocks = <&cpg CPG_MOD 523>;
1207 resets = <&cpg 523>;
1208 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1209 status = "disabled";
1210 };
1211
1212 pwm1: pwm@e6e31000 {
1213 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1214 reg = <0 0xe6e31000 0 0x8>;
1215 #pwm-cells = <2>;
1216 clocks = <&cpg CPG_MOD 523>;
1217 resets = <&cpg 523>;
1218 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1219 status = "disabled";
1220 };
1221
1222 pwm2: pwm@e6e32000 {
1223 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1224 reg = <0 0xe6e32000 0 0x8>;
1225 #pwm-cells = <2>;
1226 clocks = <&cpg CPG_MOD 523>;
1227 resets = <&cpg 523>;
1228 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1229 status = "disabled";
1230 };
1231
1232 pwm3: pwm@e6e33000 {
1233 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1234 reg = <0 0xe6e33000 0 0x8>;
1235 #pwm-cells = <2>;
1236 clocks = <&cpg CPG_MOD 523>;
1237 resets = <&cpg 523>;
1238 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1239 status = "disabled";
1240 };
1241
1242 pwm4: pwm@e6e34000 {
1243 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1244 reg = <0 0xe6e34000 0 0x8>;
1245 #pwm-cells = <2>;
1246 clocks = <&cpg CPG_MOD 523>;
1247 resets = <&cpg 523>;
1248 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1249 status = "disabled";
1250 };
1251
1252 pwm5: pwm@e6e35000 {
1253 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1254 reg = <0 0xe6e35000 0 0x8>;
1255 #pwm-cells = <2>;
1256 clocks = <&cpg CPG_MOD 523>;
1257 resets = <&cpg 523>;
1258 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1259 status = "disabled";
1260 };
1261
1262 pwm6: pwm@e6e36000 {
1263 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1264 reg = <0 0xe6e36000 0 0x8>;
1265 #pwm-cells = <2>;
1266 clocks = <&cpg CPG_MOD 523>;
1267 resets = <&cpg 523>;
1268 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1269 status = "disabled";
1270 };
1271
1272 scif0: serial@e6e60000 {
1273 compatible = "renesas,scif-r8a774a1",
1274 "renesas,rcar-gen3-scif", "renesas,scif";
1275 reg = <0 0xe6e60000 0 0x40>;
1276 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&cpg CPG_MOD 207>,
1278 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1279 <&scif_clk>;
1280 clock-names = "fck", "brg_int", "scif_clk";
1281 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1282 <&dmac2 0x51>, <&dmac2 0x50>;
1283 dma-names = "tx", "rx", "tx", "rx";
1284 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1285 resets = <&cpg 207>;
1286 status = "disabled";
1287 };
1288
1289 scif1: serial@e6e68000 {
1290 compatible = "renesas,scif-r8a774a1",
1291 "renesas,rcar-gen3-scif", "renesas,scif";
1292 reg = <0 0xe6e68000 0 0x40>;
1293 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&cpg CPG_MOD 206>,
1295 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1296 <&scif_clk>;
1297 clock-names = "fck", "brg_int", "scif_clk";
1298 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1299 <&dmac2 0x53>, <&dmac2 0x52>;
1300 dma-names = "tx", "rx", "tx", "rx";
1301 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1302 resets = <&cpg 206>;
1303 status = "disabled";
1304 };
1305
1306 scif2: serial@e6e88000 {
1307 compatible = "renesas,scif-r8a774a1",
1308 "renesas,rcar-gen3-scif", "renesas,scif";
1309 reg = <0 0xe6e88000 0 0x40>;
1310 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&cpg CPG_MOD 310>,
1312 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1313 <&scif_clk>;
1314 clock-names = "fck", "brg_int", "scif_clk";
1315 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1316 <&dmac2 0x13>, <&dmac2 0x12>;
1317 dma-names = "tx", "rx", "tx", "rx";
1318 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1319 resets = <&cpg 310>;
1320 status = "disabled";
1321 };
1322
1323 scif3: serial@e6c50000 {
1324 compatible = "renesas,scif-r8a774a1",
1325 "renesas,rcar-gen3-scif", "renesas,scif";
1326 reg = <0 0xe6c50000 0 0x40>;
1327 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1328 clocks = <&cpg CPG_MOD 204>,
1329 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1330 <&scif_clk>;
1331 clock-names = "fck", "brg_int", "scif_clk";
1332 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1333 dma-names = "tx", "rx";
1334 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1335 resets = <&cpg 204>;
1336 status = "disabled";
1337 };
1338
1339 scif4: serial@e6c40000 {
1340 compatible = "renesas,scif-r8a774a1",
1341 "renesas,rcar-gen3-scif", "renesas,scif";
1342 reg = <0 0xe6c40000 0 0x40>;
1343 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1344 clocks = <&cpg CPG_MOD 203>,
1345 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1346 <&scif_clk>;
1347 clock-names = "fck", "brg_int", "scif_clk";
1348 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1349 dma-names = "tx", "rx";
1350 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1351 resets = <&cpg 203>;
1352 status = "disabled";
1353 };
1354
1355 scif5: serial@e6f30000 {
1356 compatible = "renesas,scif-r8a774a1",
1357 "renesas,rcar-gen3-scif", "renesas,scif";
1358 reg = <0 0xe6f30000 0 0x40>;
1359 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1360 clocks = <&cpg CPG_MOD 202>,
1361 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1362 <&scif_clk>;
1363 clock-names = "fck", "brg_int", "scif_clk";
1364 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1365 <&dmac2 0x5b>, <&dmac2 0x5a>;
1366 dma-names = "tx", "rx", "tx", "rx";
1367 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1368 resets = <&cpg 202>;
1369 status = "disabled";
1370 };
1371
1372 msiof0: spi@e6e90000 {
1373 compatible = "renesas,msiof-r8a774a1",
1374 "renesas,rcar-gen3-msiof";
1375 reg = <0 0xe6e90000 0 0x0064>;
1376 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1377 clocks = <&cpg CPG_MOD 211>;
1378 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1379 <&dmac2 0x41>, <&dmac2 0x40>;
1380 dma-names = "tx", "rx", "tx", "rx";
1381 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1382 resets = <&cpg 211>;
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1385 status = "disabled";
1386 };
1387
1388 msiof1: spi@e6ea0000 {
1389 compatible = "renesas,msiof-r8a774a1",
1390 "renesas,rcar-gen3-msiof";
1391 reg = <0 0xe6ea0000 0 0x0064>;
1392 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1393 clocks = <&cpg CPG_MOD 210>;
1394 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1395 <&dmac2 0x43>, <&dmac2 0x42>;
1396 dma-names = "tx", "rx", "tx", "rx";
1397 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1398 resets = <&cpg 210>;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 status = "disabled";
1402 };
1403
1404 msiof2: spi@e6c00000 {
1405 compatible = "renesas,msiof-r8a774a1",
1406 "renesas,rcar-gen3-msiof";
1407 reg = <0 0xe6c00000 0 0x0064>;
1408 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cpg CPG_MOD 209>;
1410 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1411 dma-names = "tx", "rx";
1412 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1413 resets = <&cpg 209>;
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1416 status = "disabled";
1417 };
1418
1419 msiof3: spi@e6c10000 {
1420 compatible = "renesas,msiof-r8a774a1",
1421 "renesas,rcar-gen3-msiof";
1422 reg = <0 0xe6c10000 0 0x0064>;
1423 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1424 clocks = <&cpg CPG_MOD 208>;
1425 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1426 dma-names = "tx", "rx";
1427 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1428 resets = <&cpg 208>;
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1431 status = "disabled";
1432 };
1433
1434 vin0: video@e6ef0000 {
1435 compatible = "renesas,vin-r8a774a1";
1436 reg = <0 0xe6ef0000 0 0x1000>;
1437 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&cpg CPG_MOD 811>;
1439 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1440 resets = <&cpg 811>;
1441 renesas,id = <0>;
1442 status = "disabled";
1443
1444 ports {
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1447
1448 port@1 {
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451
1452 reg = <1>;
1453
1454 vin0csi20: endpoint@0 {
1455 reg = <0>;
1456 remote-endpoint = <&csi20vin0>;
1457 };
1458 vin0csi40: endpoint@2 {
1459 reg = <2>;
1460 remote-endpoint = <&csi40vin0>;
1461 };
1462 };
1463 };
1464 };
1465
1466 vin1: video@e6ef1000 {
1467 compatible = "renesas,vin-r8a774a1";
1468 reg = <0 0xe6ef1000 0 0x1000>;
1469 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&cpg CPG_MOD 810>;
1471 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1472 resets = <&cpg 810>;
1473 renesas,id = <1>;
1474 status = "disabled";
1475
1476 ports {
1477 #address-cells = <1>;
1478 #size-cells = <0>;
1479
1480 port@1 {
1481 #address-cells = <1>;
1482 #size-cells = <0>;
1483
1484 reg = <1>;
1485
1486 vin1csi20: endpoint@0 {
1487 reg = <0>;
1488 remote-endpoint = <&csi20vin1>;
1489 };
1490 vin1csi40: endpoint@2 {
1491 reg = <2>;
1492 remote-endpoint = <&csi40vin1>;
1493 };
1494 };
1495 };
1496 };
1497
1498 vin2: video@e6ef2000 {
1499 compatible = "renesas,vin-r8a774a1";
1500 reg = <0 0xe6ef2000 0 0x1000>;
1501 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MOD 809>;
1503 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1504 resets = <&cpg 809>;
1505 renesas,id = <2>;
1506 status = "disabled";
1507
1508 ports {
1509 #address-cells = <1>;
1510 #size-cells = <0>;
1511
1512 port@1 {
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515
1516 reg = <1>;
1517
1518 vin2csi20: endpoint@0 {
1519 reg = <0>;
1520 remote-endpoint = <&csi20vin2>;
1521 };
1522 vin2csi40: endpoint@2 {
1523 reg = <2>;
1524 remote-endpoint = <&csi40vin2>;
1525 };
1526 };
1527 };
1528 };
1529
1530 vin3: video@e6ef3000 {
1531 compatible = "renesas,vin-r8a774a1";
1532 reg = <0 0xe6ef3000 0 0x1000>;
1533 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MOD 808>;
1535 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1536 resets = <&cpg 808>;
1537 renesas,id = <3>;
1538 status = "disabled";
1539
1540 ports {
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543
1544 port@1 {
1545 #address-cells = <1>;
1546 #size-cells = <0>;
1547
1548 reg = <1>;
1549
1550 vin3csi20: endpoint@0 {
1551 reg = <0>;
1552 remote-endpoint = <&csi20vin3>;
1553 };
1554 vin3csi40: endpoint@2 {
1555 reg = <2>;
1556 remote-endpoint = <&csi40vin3>;
1557 };
1558 };
1559 };
1560 };
1561
1562 vin4: video@e6ef4000 {
1563 compatible = "renesas,vin-r8a774a1";
1564 reg = <0 0xe6ef4000 0 0x1000>;
1565 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MOD 807>;
1567 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1568 resets = <&cpg 807>;
1569 renesas,id = <4>;
1570 status = "disabled";
1571
1572 ports {
1573 #address-cells = <1>;
1574 #size-cells = <0>;
1575
1576 port@1 {
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1579
1580 reg = <1>;
1581
1582 vin4csi20: endpoint@0 {
1583 reg = <0>;
1584 remote-endpoint = <&csi20vin4>;
1585 };
1586 vin4csi40: endpoint@2 {
1587 reg = <2>;
1588 remote-endpoint = <&csi40vin4>;
1589 };
1590 };
1591 };
1592 };
1593
1594 vin5: video@e6ef5000 {
1595 compatible = "renesas,vin-r8a774a1";
1596 reg = <0 0xe6ef5000 0 0x1000>;
1597 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MOD 806>;
1599 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1600 resets = <&cpg 806>;
1601 renesas,id = <5>;
1602 status = "disabled";
1603
1604 ports {
1605 #address-cells = <1>;
1606 #size-cells = <0>;
1607
1608 port@1 {
1609 #address-cells = <1>;
1610 #size-cells = <0>;
1611
1612 reg = <1>;
1613
1614 vin5csi20: endpoint@0 {
1615 reg = <0>;
1616 remote-endpoint = <&csi20vin5>;
1617 };
1618 vin5csi40: endpoint@2 {
1619 reg = <2>;
1620 remote-endpoint = <&csi40vin5>;
1621 };
1622 };
1623 };
1624 };
1625
1626 vin6: video@e6ef6000 {
1627 compatible = "renesas,vin-r8a774a1";
1628 reg = <0 0xe6ef6000 0 0x1000>;
1629 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MOD 805>;
1631 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1632 resets = <&cpg 805>;
1633 renesas,id = <6>;
1634 status = "disabled";
1635
1636 ports {
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639
1640 port@1 {
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643
1644 reg = <1>;
1645
1646 vin6csi20: endpoint@0 {
1647 reg = <0>;
1648 remote-endpoint = <&csi20vin6>;
1649 };
1650 vin6csi40: endpoint@2 {
1651 reg = <2>;
1652 remote-endpoint = <&csi40vin6>;
1653 };
1654 };
1655 };
1656 };
1657
1658 vin7: video@e6ef7000 {
1659 compatible = "renesas,vin-r8a774a1";
1660 reg = <0 0xe6ef7000 0 0x1000>;
1661 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MOD 804>;
1663 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1664 resets = <&cpg 804>;
1665 renesas,id = <7>;
1666 status = "disabled";
1667
1668 ports {
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1671
1672 port@1 {
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675
1676 reg = <1>;
1677
1678 vin7csi20: endpoint@0 {
1679 reg = <0>;
1680 remote-endpoint = <&csi20vin7>;
1681 };
1682 vin7csi40: endpoint@2 {
1683 reg = <2>;
1684 remote-endpoint = <&csi40vin7>;
1685 };
1686 };
1687 };
1688 };
1689
1690 rcar_sound: sound@ec500000 {
1691 /*
1692 * #sound-dai-cells is required
1693 *
1694 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1695 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1696 */
1697 /*
1698 * #clock-cells is required for audio_clkout0/1/2/3
1699 *
1700 * clkout : #clock-cells = <0>; <&rcar_sound>;
1701 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1702 */
1703 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1704 reg = <0 0xec500000 0 0x1000>, /* SCU */
1705 <0 0xec5a0000 0 0x100>, /* ADG */
1706 <0 0xec540000 0 0x1000>, /* SSIU */
1707 <0 0xec541000 0 0x280>, /* SSI */
1708 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1709 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1710
1711 clocks = <&cpg CPG_MOD 1005>,
1712 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1713 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1714 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1715 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1716 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1717 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1718 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1719 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1720 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1721 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1722 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1723 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1724 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1725 <&audio_clk_a>, <&audio_clk_b>,
1726 <&audio_clk_c>,
1727 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
1728 clock-names = "ssi-all",
1729 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1730 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1731 "ssi.1", "ssi.0",
1732 "src.9", "src.8", "src.7", "src.6",
1733 "src.5", "src.4", "src.3", "src.2",
1734 "src.1", "src.0",
1735 "mix.1", "mix.0",
1736 "ctu.1", "ctu.0",
1737 "dvc.0", "dvc.1",
1738 "clk_a", "clk_b", "clk_c", "clk_i";
1739 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1740 resets = <&cpg 1005>,
1741 <&cpg 1006>, <&cpg 1007>,
1742 <&cpg 1008>, <&cpg 1009>,
1743 <&cpg 1010>, <&cpg 1011>,
1744 <&cpg 1012>, <&cpg 1013>,
1745 <&cpg 1014>, <&cpg 1015>;
1746 reset-names = "ssi-all",
1747 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1748 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1749 "ssi.1", "ssi.0";
1750 status = "disabled";
1751
1752 rcar_sound,ctu {
1753 ctu00: ctu-0 { };
1754 ctu01: ctu-1 { };
1755 ctu02: ctu-2 { };
1756 ctu03: ctu-3 { };
1757 ctu10: ctu-4 { };
1758 ctu11: ctu-5 { };
1759 ctu12: ctu-6 { };
1760 ctu13: ctu-7 { };
1761 };
1762
1763 rcar_sound,dvc {
1764 dvc0: dvc-0 {
1765 dmas = <&audma1 0xbc>;
1766 dma-names = "tx";
1767 };
1768 dvc1: dvc-1 {
1769 dmas = <&audma1 0xbe>;
1770 dma-names = "tx";
1771 };
1772 };
1773
1774 rcar_sound,mix {
1775 mix0: mix-0 { };
1776 mix1: mix-1 { };
1777 };
1778
1779 rcar_sound,src {
1780 src0: src-0 {
1781 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1782 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1783 dma-names = "rx", "tx";
1784 };
1785 src1: src-1 {
1786 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1788 dma-names = "rx", "tx";
1789 };
1790 src2: src-2 {
1791 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1793 dma-names = "rx", "tx";
1794 };
1795 src3: src-3 {
1796 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1798 dma-names = "rx", "tx";
1799 };
1800 src4: src-4 {
1801 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1803 dma-names = "rx", "tx";
1804 };
1805 src5: src-5 {
1806 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1808 dma-names = "rx", "tx";
1809 };
1810 src6: src-6 {
1811 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1813 dma-names = "rx", "tx";
1814 };
1815 src7: src-7 {
1816 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1818 dma-names = "rx", "tx";
1819 };
1820 src8: src-8 {
1821 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1822 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1823 dma-names = "rx", "tx";
1824 };
1825 src9: src-9 {
1826 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1827 dmas = <&audma0 0x97>, <&audma1 0xba>;
1828 dma-names = "rx", "tx";
1829 };
1830 };
1831
1832 rcar_sound,ssi {
1833 ssi0: ssi-0 {
1834 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1835 dmas = <&audma0 0x01>, <&audma1 0x02>;
1836 dma-names = "rx", "tx";
1837 };
1838 ssi1: ssi-1 {
1839 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1840 dmas = <&audma0 0x03>, <&audma1 0x04>;
1841 dma-names = "rx", "tx";
1842 };
1843 ssi2: ssi-2 {
1844 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1845 dmas = <&audma0 0x05>, <&audma1 0x06>;
1846 dma-names = "rx", "tx";
1847 };
1848 ssi3: ssi-3 {
1849 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1850 dmas = <&audma0 0x07>, <&audma1 0x08>;
1851 dma-names = "rx", "tx";
1852 };
1853 ssi4: ssi-4 {
1854 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1855 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1856 dma-names = "rx", "tx";
1857 };
1858 ssi5: ssi-5 {
1859 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1860 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1861 dma-names = "rx", "tx";
1862 };
1863 ssi6: ssi-6 {
1864 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1865 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1866 dma-names = "rx", "tx";
1867 };
1868 ssi7: ssi-7 {
1869 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1870 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1871 dma-names = "rx", "tx";
1872 };
1873 ssi8: ssi-8 {
1874 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1875 dmas = <&audma0 0x11>, <&audma1 0x12>;
1876 dma-names = "rx", "tx";
1877 };
1878 ssi9: ssi-9 {
1879 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1880 dmas = <&audma0 0x13>, <&audma1 0x14>;
1881 dma-names = "rx", "tx";
1882 };
1883 };
1884
1885 rcar_sound,ssiu {
1886 ssiu00: ssiu-0 {
1887 dmas = <&audma0 0x15>, <&audma1 0x16>;
1888 dma-names = "rx", "tx";
1889 };
1890 ssiu01: ssiu-1 {
1891 dmas = <&audma0 0x35>, <&audma1 0x36>;
1892 dma-names = "rx", "tx";
1893 };
1894 ssiu02: ssiu-2 {
1895 dmas = <&audma0 0x37>, <&audma1 0x38>;
1896 dma-names = "rx", "tx";
1897 };
1898 ssiu03: ssiu-3 {
1899 dmas = <&audma0 0x47>, <&audma1 0x48>;
1900 dma-names = "rx", "tx";
1901 };
1902 ssiu04: ssiu-4 {
1903 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1904 dma-names = "rx", "tx";
1905 };
1906 ssiu05: ssiu-5 {
1907 dmas = <&audma0 0x43>, <&audma1 0x44>;
1908 dma-names = "rx", "tx";
1909 };
1910 ssiu06: ssiu-6 {
1911 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1912 dma-names = "rx", "tx";
1913 };
1914 ssiu07: ssiu-7 {
1915 dmas = <&audma0 0x53>, <&audma1 0x54>;
1916 dma-names = "rx", "tx";
1917 };
1918 ssiu10: ssiu-8 {
1919 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1920 dma-names = "rx", "tx";
1921 };
1922 ssiu11: ssiu-9 {
1923 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1924 dma-names = "rx", "tx";
1925 };
1926 ssiu12: ssiu-10 {
1927 dmas = <&audma0 0x57>, <&audma1 0x58>;
1928 dma-names = "rx", "tx";
1929 };
1930 ssiu13: ssiu-11 {
1931 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1932 dma-names = "rx", "tx";
1933 };
1934 ssiu14: ssiu-12 {
1935 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1936 dma-names = "rx", "tx";
1937 };
1938 ssiu15: ssiu-13 {
1939 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1940 dma-names = "rx", "tx";
1941 };
1942 ssiu16: ssiu-14 {
1943 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1944 dma-names = "rx", "tx";
1945 };
1946 ssiu17: ssiu-15 {
1947 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1948 dma-names = "rx", "tx";
1949 };
1950 ssiu20: ssiu-16 {
1951 dmas = <&audma0 0x63>, <&audma1 0x64>;
1952 dma-names = "rx", "tx";
1953 };
1954 ssiu21: ssiu-17 {
1955 dmas = <&audma0 0x67>, <&audma1 0x68>;
1956 dma-names = "rx", "tx";
1957 };
1958 ssiu22: ssiu-18 {
1959 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1960 dma-names = "rx", "tx";
1961 };
1962 ssiu23: ssiu-19 {
1963 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1964 dma-names = "rx", "tx";
1965 };
1966 ssiu24: ssiu-20 {
1967 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1968 dma-names = "rx", "tx";
1969 };
1970 ssiu25: ssiu-21 {
1971 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1972 dma-names = "rx", "tx";
1973 };
1974 ssiu26: ssiu-22 {
1975 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1976 dma-names = "rx", "tx";
1977 };
1978 ssiu27: ssiu-23 {
1979 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1980 dma-names = "rx", "tx";
1981 };
1982 ssiu30: ssiu-24 {
1983 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1984 dma-names = "rx", "tx";
1985 };
1986 ssiu31: ssiu-25 {
1987 dmas = <&audma0 0x21>, <&audma1 0x22>;
1988 dma-names = "rx", "tx";
1989 };
1990 ssiu32: ssiu-26 {
1991 dmas = <&audma0 0x23>, <&audma1 0x24>;
1992 dma-names = "rx", "tx";
1993 };
1994 ssiu33: ssiu-27 {
1995 dmas = <&audma0 0x25>, <&audma1 0x26>;
1996 dma-names = "rx", "tx";
1997 };
1998 ssiu34: ssiu-28 {
1999 dmas = <&audma0 0x27>, <&audma1 0x28>;
2000 dma-names = "rx", "tx";
2001 };
2002 ssiu35: ssiu-29 {
2003 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2004 dma-names = "rx", "tx";
2005 };
2006 ssiu36: ssiu-30 {
2007 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2008 dma-names = "rx", "tx";
2009 };
2010 ssiu37: ssiu-31 {
2011 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2012 dma-names = "rx", "tx";
2013 };
2014 ssiu40: ssiu-32 {
2015 dmas = <&audma0 0x71>, <&audma1 0x72>;
2016 dma-names = "rx", "tx";
2017 };
2018 ssiu41: ssiu-33 {
2019 dmas = <&audma0 0x17>, <&audma1 0x18>;
2020 dma-names = "rx", "tx";
2021 };
2022 ssiu42: ssiu-34 {
2023 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2024 dma-names = "rx", "tx";
2025 };
2026 ssiu43: ssiu-35 {
2027 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2028 dma-names = "rx", "tx";
2029 };
2030 ssiu44: ssiu-36 {
2031 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2032 dma-names = "rx", "tx";
2033 };
2034 ssiu45: ssiu-37 {
2035 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2036 dma-names = "rx", "tx";
2037 };
2038 ssiu46: ssiu-38 {
2039 dmas = <&audma0 0x31>, <&audma1 0x32>;
2040 dma-names = "rx", "tx";
2041 };
2042 ssiu47: ssiu-39 {
2043 dmas = <&audma0 0x33>, <&audma1 0x34>;
2044 dma-names = "rx", "tx";
2045 };
2046 ssiu50: ssiu-40 {
2047 dmas = <&audma0 0x73>, <&audma1 0x74>;
2048 dma-names = "rx", "tx";
2049 };
2050 ssiu60: ssiu-41 {
2051 dmas = <&audma0 0x75>, <&audma1 0x76>;
2052 dma-names = "rx", "tx";
2053 };
2054 ssiu70: ssiu-42 {
2055 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2056 dma-names = "rx", "tx";
2057 };
2058 ssiu80: ssiu-43 {
2059 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2060 dma-names = "rx", "tx";
2061 };
2062 ssiu90: ssiu-44 {
2063 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2064 dma-names = "rx", "tx";
2065 };
2066 ssiu91: ssiu-45 {
2067 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2068 dma-names = "rx", "tx";
2069 };
2070 ssiu92: ssiu-46 {
2071 dmas = <&audma0 0x81>, <&audma1 0x82>;
2072 dma-names = "rx", "tx";
2073 };
2074 ssiu93: ssiu-47 {
2075 dmas = <&audma0 0x83>, <&audma1 0x84>;
2076 dma-names = "rx", "tx";
2077 };
2078 ssiu94: ssiu-48 {
2079 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2080 dma-names = "rx", "tx";
2081 };
2082 ssiu95: ssiu-49 {
2083 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2084 dma-names = "rx", "tx";
2085 };
2086 ssiu96: ssiu-50 {
2087 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2088 dma-names = "rx", "tx";
2089 };
2090 ssiu97: ssiu-51 {
2091 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2092 dma-names = "rx", "tx";
2093 };
2094 };
2095 };
2096
2097 audma0: dma-controller@ec700000 {
2098 compatible = "renesas,dmac-r8a774a1",
2099 "renesas,rcar-dmac";
2100 reg = <0 0xec700000 0 0x10000>;
2101 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2105 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2106 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2107 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2108 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2109 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2110 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2112 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2113 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2118 interrupt-names = "error",
2119 "ch0", "ch1", "ch2", "ch3",
2120 "ch4", "ch5", "ch6", "ch7",
2121 "ch8", "ch9", "ch10", "ch11",
2122 "ch12", "ch13", "ch14", "ch15";
2123 clocks = <&cpg CPG_MOD 502>;
2124 clock-names = "fck";
2125 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2126 resets = <&cpg 502>;
2127 #dma-cells = <1>;
2128 dma-channels = <16>;
2129 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2130 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2131 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2132 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2133 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2134 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2135 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2136 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2137 };
2138
2139 audma1: dma-controller@ec720000 {
2140 compatible = "renesas,dmac-r8a774a1",
2141 "renesas,rcar-dmac";
2142 reg = <0 0xec720000 0 0x10000>;
2143 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2144 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2145 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2155 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2156 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2157 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2160 interrupt-names = "error",
2161 "ch0", "ch1", "ch2", "ch3",
2162 "ch4", "ch5", "ch6", "ch7",
2163 "ch8", "ch9", "ch10", "ch11",
2164 "ch12", "ch13", "ch14", "ch15";
2165 clocks = <&cpg CPG_MOD 501>;
2166 clock-names = "fck";
2167 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2168 resets = <&cpg 501>;
2169 #dma-cells = <1>;
2170 dma-channels = <16>;
2171 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2172 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2173 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2174 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2175 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2176 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2177 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2178 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2179 };
2180
2181 xhci0: usb@ee000000 {
2182 compatible = "renesas,xhci-r8a774a1",
2183 "renesas,rcar-gen3-xhci";
2184 reg = <0 0xee000000 0 0xc00>;
2185 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2186 clocks = <&cpg CPG_MOD 328>;
2187 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2188 resets = <&cpg 328>;
2189 status = "disabled";
2190 };
2191
2192 usb3_peri0: usb@ee020000 {
2193 compatible = "renesas,r8a774a1-usb3-peri",
2194 "renesas,rcar-gen3-usb3-peri";
2195 reg = <0 0xee020000 0 0x400>;
2196 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2197 clocks = <&cpg CPG_MOD 328>;
2198 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2199 resets = <&cpg 328>;
2200 status = "disabled";
2201 };
2202
2203 ohci0: usb@ee080000 {
2204 compatible = "generic-ohci";
2205 reg = <0 0xee080000 0 0x100>;
2206 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2207 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2208 phys = <&usb2_phy0 1>;
2209 phy-names = "usb";
2210 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2211 resets = <&cpg 703>, <&cpg 704>;
2212 status = "disabled";
2213 };
2214
2215 ohci1: usb@ee0a0000 {
2216 compatible = "generic-ohci";
2217 reg = <0 0xee0a0000 0 0x100>;
2218 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2219 clocks = <&cpg CPG_MOD 702>;
2220 phys = <&usb2_phy1 1>;
2221 phy-names = "usb";
2222 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2223 resets = <&cpg 702>;
2224 status = "disabled";
2225 };
2226
2227 ehci0: usb@ee080100 {
2228 compatible = "generic-ehci";
2229 reg = <0 0xee080100 0 0x100>;
2230 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2231 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2232 phys = <&usb2_phy0 2>;
2233 phy-names = "usb";
2234 companion = <&ohci0>;
2235 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2236 resets = <&cpg 703>, <&cpg 704>;
2237 status = "disabled";
2238 };
2239
2240 ehci1: usb@ee0a0100 {
2241 compatible = "generic-ehci";
2242 reg = <0 0xee0a0100 0 0x100>;
2243 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2244 clocks = <&cpg CPG_MOD 702>;
2245 phys = <&usb2_phy1 2>;
2246 phy-names = "usb";
2247 companion = <&ohci1>;
2248 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2249 resets = <&cpg 702>;
2250 status = "disabled";
2251 };
2252
2253 usb2_phy0: usb-phy@ee080200 {
2254 compatible = "renesas,usb2-phy-r8a774a1",
2255 "renesas,rcar-gen3-usb2-phy";
2256 reg = <0 0xee080200 0 0x700>;
2257 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2258 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2259 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2260 resets = <&cpg 703>, <&cpg 704>;
2261 #phy-cells = <1>;
2262 status = "disabled";
2263 };
2264
2265 usb2_phy1: usb-phy@ee0a0200 {
2266 compatible = "renesas,usb2-phy-r8a774a1",
2267 "renesas,rcar-gen3-usb2-phy";
2268 reg = <0 0xee0a0200 0 0x700>;
2269 clocks = <&cpg CPG_MOD 702>;
2270 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2271 resets = <&cpg 702>;
2272 #phy-cells = <1>;
2273 status = "disabled";
2274 };
2275
2276 sdhi0: mmc@ee100000 {
2277 compatible = "renesas,sdhi-r8a774a1",
2278 "renesas,rcar-gen3-sdhi";
2279 reg = <0 0xee100000 0 0x2000>;
2280 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2281 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
2282 clock-names = "core", "clkh";
2283 max-frequency = <200000000>;
2284 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2285 resets = <&cpg 314>;
2286 status = "disabled";
2287 };
2288
2289 sdhi1: mmc@ee120000 {
2290 compatible = "renesas,sdhi-r8a774a1",
2291 "renesas,rcar-gen3-sdhi";
2292 reg = <0 0xee120000 0 0x2000>;
2293 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2294 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
2295 clock-names = "core", "clkh";
2296 max-frequency = <200000000>;
2297 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2298 resets = <&cpg 313>;
2299 status = "disabled";
2300 };
2301
2302 sdhi2: mmc@ee140000 {
2303 compatible = "renesas,sdhi-r8a774a1",
2304 "renesas,rcar-gen3-sdhi";
2305 reg = <0 0xee140000 0 0x2000>;
2306 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2307 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
2308 clock-names = "core", "clkh";
2309 max-frequency = <200000000>;
2310 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2311 resets = <&cpg 312>;
2312 status = "disabled";
2313 };
2314
2315 sdhi3: mmc@ee160000 {
2316 compatible = "renesas,sdhi-r8a774a1",
2317 "renesas,rcar-gen3-sdhi";
2318 reg = <0 0xee160000 0 0x2000>;
2319 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2320 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
2321 clock-names = "core", "clkh";
2322 max-frequency = <200000000>;
2323 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2324 resets = <&cpg 311>;
2325 status = "disabled";
2326 };
2327
2328 rpc: spi@ee200000 {
2329 compatible = "renesas,r8a774a1-rpc-if",
2330 "renesas,rcar-gen3-rpc-if";
2331 reg = <0 0xee200000 0 0x200>,
2332 <0 0x08000000 0 0x4000000>,
2333 <0 0xee208000 0 0x100>;
2334 reg-names = "regs", "dirmap", "wbuf";
2335 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2336 clocks = <&cpg CPG_MOD 917>;
2337 clock-names = "rpc";
2338 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2339 resets = <&cpg 917>;
2340 #address-cells = <1>;
2341 #size-cells = <0>;
2342 status = "disabled";
2343 };
2344
2345 gic: interrupt-controller@f1010000 {
2346 compatible = "arm,gic-400";
2347 #interrupt-cells = <3>;
2348 #address-cells = <0>;
2349 interrupt-controller;
2350 reg = <0x0 0xf1010000 0 0x1000>,
2351 <0x0 0xf1020000 0 0x20000>,
2352 <0x0 0xf1040000 0 0x20000>,
2353 <0x0 0xf1060000 0 0x20000>;
2354 interrupts = <GIC_PPI 9
2355 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2356 clocks = <&cpg CPG_MOD 408>;
2357 clock-names = "clk";
2358 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2359 resets = <&cpg 408>;
2360 };
2361
2362 pciec0: pcie@fe000000 {
2363 compatible = "renesas,pcie-r8a774a1",
2364 "renesas,pcie-rcar-gen3";
2365 reg = <0 0xfe000000 0 0x80000>;
2366 #address-cells = <3>;
2367 #size-cells = <2>;
2368 bus-range = <0x00 0xff>;
2369 device_type = "pci";
2370 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2371 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2372 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2373 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2374 /* Map all possible DDR as inbound ranges */
2375 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2376 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2377 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2378 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2379 #interrupt-cells = <1>;
2380 interrupt-map-mask = <0 0 0 0>;
2381 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2383 clock-names = "pcie", "pcie_bus";
2384 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2385 resets = <&cpg 319>;
2386 status = "disabled";
2387 };
2388
2389 pciec1: pcie@ee800000 {
2390 compatible = "renesas,pcie-r8a774a1",
2391 "renesas,pcie-rcar-gen3";
2392 reg = <0 0xee800000 0 0x80000>;
2393 #address-cells = <3>;
2394 #size-cells = <2>;
2395 bus-range = <0x00 0xff>;
2396 device_type = "pci";
2397 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2398 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2399 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2400 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2401 /* Map all possible DDR as inbound ranges */
2402 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2403 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2405 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2406 #interrupt-cells = <1>;
2407 interrupt-map-mask = <0 0 0 0>;
2408 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2409 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2410 clock-names = "pcie", "pcie_bus";
2411 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2412 resets = <&cpg 318>;
2413 status = "disabled";
2414 };
2415
2416 pciec0_ep: pcie-ep@fe000000 {
2417 compatible = "renesas,r8a774a1-pcie-ep",
2418 "renesas,rcar-gen3-pcie-ep";
2419 reg = <0x0 0xfe000000 0 0x80000>,
2420 <0x0 0xfe100000 0 0x100000>,
2421 <0x0 0xfe200000 0 0x200000>,
2422 <0x0 0x30000000 0 0x8000000>,
2423 <0x0 0x38000000 0 0x8000000>;
2424 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2425 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2426 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2427 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2428 clocks = <&cpg CPG_MOD 319>;
2429 clock-names = "pcie";
2430 resets = <&cpg 319>;
2431 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2432 status = "disabled";
2433 };
2434
2435 pciec1_ep: pcie-ep@ee800000 {
2436 compatible = "renesas,r8a774a1-pcie-ep",
2437 "renesas,rcar-gen3-pcie-ep";
2438 reg = <0x0 0xee800000 0 0x80000>,
2439 <0x0 0xee900000 0 0x100000>,
2440 <0x0 0xeea00000 0 0x200000>,
2441 <0x0 0xc0000000 0 0x8000000>,
2442 <0x0 0xc8000000 0 0x8000000>;
2443 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2444 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2447 clocks = <&cpg CPG_MOD 318>;
2448 clock-names = "pcie";
2449 resets = <&cpg 318>;
2450 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2451 status = "disabled";
2452 };
2453
2454 fdp1@fe940000 {
2455 compatible = "renesas,fdp1";
2456 reg = <0 0xfe940000 0 0x2400>;
2457 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2458 clocks = <&cpg CPG_MOD 119>;
2459 power-domains = <&sysc R8A774A1_PD_A3VC>;
2460 resets = <&cpg 119>;
2461 renesas,fcp = <&fcpf0>;
2462 };
2463
2464 fcpf0: fcp@fe950000 {
2465 compatible = "renesas,fcpf";
2466 reg = <0 0xfe950000 0 0x200>;
2467 clocks = <&cpg CPG_MOD 615>;
2468 power-domains = <&sysc R8A774A1_PD_A3VC>;
2469 resets = <&cpg 615>;
2470 };
2471
2472 fcpvb0: fcp@fe96f000 {
2473 compatible = "renesas,fcpv";
2474 reg = <0 0xfe96f000 0 0x200>;
2475 clocks = <&cpg CPG_MOD 607>;
2476 power-domains = <&sysc R8A774A1_PD_A3VC>;
2477 resets = <&cpg 607>;
2478 };
2479
2480 fcpvd0: fcp@fea27000 {
2481 compatible = "renesas,fcpv";
2482 reg = <0 0xfea27000 0 0x200>;
2483 clocks = <&cpg CPG_MOD 603>;
2484 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2485 resets = <&cpg 603>;
2486 iommus = <&ipmmu_vi0 8>;
2487 };
2488
2489 fcpvd1: fcp@fea2f000 {
2490 compatible = "renesas,fcpv";
2491 reg = <0 0xfea2f000 0 0x200>;
2492 clocks = <&cpg CPG_MOD 602>;
2493 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2494 resets = <&cpg 602>;
2495 iommus = <&ipmmu_vi0 9>;
2496 };
2497
2498 fcpvd2: fcp@fea37000 {
2499 compatible = "renesas,fcpv";
2500 reg = <0 0xfea37000 0 0x200>;
2501 clocks = <&cpg CPG_MOD 601>;
2502 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2503 resets = <&cpg 601>;
2504 iommus = <&ipmmu_vi0 10>;
2505 };
2506
2507 fcpvi0: fcp@fe9af000 {
2508 compatible = "renesas,fcpv";
2509 reg = <0 0xfe9af000 0 0x200>;
2510 clocks = <&cpg CPG_MOD 611>;
2511 power-domains = <&sysc R8A774A1_PD_A3VC>;
2512 resets = <&cpg 611>;
2513 iommus = <&ipmmu_vc0 19>;
2514 };
2515
2516 vspb: vsp@fe960000 {
2517 compatible = "renesas,vsp2";
2518 reg = <0 0xfe960000 0 0x8000>;
2519 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2520 clocks = <&cpg CPG_MOD 626>;
2521 power-domains = <&sysc R8A774A1_PD_A3VC>;
2522 resets = <&cpg 626>;
2523
2524 renesas,fcp = <&fcpvb0>;
2525 };
2526
2527 vspd0: vsp@fea20000 {
2528 compatible = "renesas,vsp2";
2529 reg = <0 0xfea20000 0 0x5000>;
2530 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2531 clocks = <&cpg CPG_MOD 623>;
2532 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2533 resets = <&cpg 623>;
2534
2535 renesas,fcp = <&fcpvd0>;
2536 };
2537
2538 vspd1: vsp@fea28000 {
2539 compatible = "renesas,vsp2";
2540 reg = <0 0xfea28000 0 0x5000>;
2541 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2542 clocks = <&cpg CPG_MOD 622>;
2543 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2544 resets = <&cpg 622>;
2545
2546 renesas,fcp = <&fcpvd1>;
2547 };
2548
2549 vspd2: vsp@fea30000 {
2550 compatible = "renesas,vsp2";
2551 reg = <0 0xfea30000 0 0x5000>;
2552 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2553 clocks = <&cpg CPG_MOD 621>;
2554 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2555 resets = <&cpg 621>;
2556
2557 renesas,fcp = <&fcpvd2>;
2558 };
2559
2560 vspi0: vsp@fe9a0000 {
2561 compatible = "renesas,vsp2";
2562 reg = <0 0xfe9a0000 0 0x8000>;
2563 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2564 clocks = <&cpg CPG_MOD 631>;
2565 power-domains = <&sysc R8A774A1_PD_A3VC>;
2566 resets = <&cpg 631>;
2567
2568 renesas,fcp = <&fcpvi0>;
2569 };
2570
2571 csi20: csi2@fea80000 {
2572 compatible = "renesas,r8a774a1-csi2";
2573 reg = <0 0xfea80000 0 0x10000>;
2574 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2575 clocks = <&cpg CPG_MOD 714>;
2576 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2577 resets = <&cpg 714>;
2578 status = "disabled";
2579
2580 ports {
2581 #address-cells = <1>;
2582 #size-cells = <0>;
2583
2584 port@0 {
2585 reg = <0>;
2586 };
2587
2588 port@1 {
2589 #address-cells = <1>;
2590 #size-cells = <0>;
2591
2592 reg = <1>;
2593
2594 csi20vin0: endpoint@0 {
2595 reg = <0>;
2596 remote-endpoint = <&vin0csi20>;
2597 };
2598 csi20vin1: endpoint@1 {
2599 reg = <1>;
2600 remote-endpoint = <&vin1csi20>;
2601 };
2602 csi20vin2: endpoint@2 {
2603 reg = <2>;
2604 remote-endpoint = <&vin2csi20>;
2605 };
2606 csi20vin3: endpoint@3 {
2607 reg = <3>;
2608 remote-endpoint = <&vin3csi20>;
2609 };
2610 csi20vin4: endpoint@4 {
2611 reg = <4>;
2612 remote-endpoint = <&vin4csi20>;
2613 };
2614 csi20vin5: endpoint@5 {
2615 reg = <5>;
2616 remote-endpoint = <&vin5csi20>;
2617 };
2618 csi20vin6: endpoint@6 {
2619 reg = <6>;
2620 remote-endpoint = <&vin6csi20>;
2621 };
2622 csi20vin7: endpoint@7 {
2623 reg = <7>;
2624 remote-endpoint = <&vin7csi20>;
2625 };
2626 };
2627 };
2628 };
2629
2630 csi40: csi2@feaa0000 {
2631 compatible = "renesas,r8a774a1-csi2";
2632 reg = <0 0xfeaa0000 0 0x10000>;
2633 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MOD 716>;
2635 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2636 resets = <&cpg 716>;
2637 status = "disabled";
2638
2639 ports {
2640 #address-cells = <1>;
2641 #size-cells = <0>;
2642
2643 port@0 {
2644 reg = <0>;
2645 };
2646
2647 port@1 {
2648 #address-cells = <1>;
2649 #size-cells = <0>;
2650
2651 reg = <1>;
2652
2653 csi40vin0: endpoint@0 {
2654 reg = <0>;
2655 remote-endpoint = <&vin0csi40>;
2656 };
2657 csi40vin1: endpoint@1 {
2658 reg = <1>;
2659 remote-endpoint = <&vin1csi40>;
2660 };
2661 csi40vin2: endpoint@2 {
2662 reg = <2>;
2663 remote-endpoint = <&vin2csi40>;
2664 };
2665 csi40vin3: endpoint@3 {
2666 reg = <3>;
2667 remote-endpoint = <&vin3csi40>;
2668 };
2669 csi40vin4: endpoint@4 {
2670 reg = <4>;
2671 remote-endpoint = <&vin4csi40>;
2672 };
2673 csi40vin5: endpoint@5 {
2674 reg = <5>;
2675 remote-endpoint = <&vin5csi40>;
2676 };
2677 csi40vin6: endpoint@6 {
2678 reg = <6>;
2679 remote-endpoint = <&vin6csi40>;
2680 };
2681 csi40vin7: endpoint@7 {
2682 reg = <7>;
2683 remote-endpoint = <&vin7csi40>;
2684 };
2685 };
2686
2687 };
2688 };
2689
2690 hdmi0: hdmi@fead0000 {
2691 compatible = "renesas,r8a774a1-hdmi",
2692 "renesas,rcar-gen3-hdmi";
2693 reg = <0 0xfead0000 0 0x10000>;
2694 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2695 clocks = <&cpg CPG_MOD 729>,
2696 <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
2697 clock-names = "iahb", "isfr";
2698 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2699 resets = <&cpg 729>;
2700 status = "disabled";
2701
2702 ports {
2703 #address-cells = <1>;
2704 #size-cells = <0>;
2705 port@0 {
2706 reg = <0>;
2707 dw_hdmi0_in: endpoint {
2708 remote-endpoint = <&du_out_hdmi0>;
2709 };
2710 };
2711 port@1 {
2712 reg = <1>;
2713 };
2714 port@2 {
2715 /* HDMI sound */
2716 reg = <2>;
2717 };
2718 };
2719 };
2720
2721 du: display@feb00000 {
2722 compatible = "renesas,du-r8a774a1";
2723 reg = <0 0xfeb00000 0 0x70000>;
2724 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2725 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2726 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2727 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2728 <&cpg CPG_MOD 722>;
2729 clock-names = "du.0", "du.1", "du.2";
2730 resets = <&cpg 724>, <&cpg 722>;
2731 reset-names = "du.0", "du.2";
2732 status = "disabled";
2733
2734 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2735
2736 ports {
2737 #address-cells = <1>;
2738 #size-cells = <0>;
2739
2740 port@0 {
2741 reg = <0>;
2742 };
2743 port@1 {
2744 reg = <1>;
2745 du_out_hdmi0: endpoint {
2746 remote-endpoint = <&dw_hdmi0_in>;
2747 };
2748 };
2749 port@2 {
2750 reg = <2>;
2751 du_out_lvds0: endpoint {
2752 remote-endpoint = <&lvds0_in>;
2753 };
2754 };
2755 };
2756 };
2757
2758 lvds0: lvds@feb90000 {
2759 compatible = "renesas,r8a774a1-lvds";
2760 reg = <0 0xfeb90000 0 0x14>;
2761 clocks = <&cpg CPG_MOD 727>;
2762 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2763 resets = <&cpg 727>;
2764 status = "disabled";
2765
2766 ports {
2767 #address-cells = <1>;
2768 #size-cells = <0>;
2769
2770 port@0 {
2771 reg = <0>;
2772 lvds0_in: endpoint {
2773 remote-endpoint = <&du_out_lvds0>;
2774 };
2775 };
2776 port@1 {
2777 reg = <1>;
2778 };
2779 };
2780 };
2781
2782 prr: chipid@fff00044 {
2783 compatible = "renesas,prr";
2784 reg = <0 0xfff00044 0 4>;
2785 };
2786 };
2787
2788 thermal-zones {
2789 sensor1_thermal: sensor1-thermal {
2790 polling-delay-passive = <250>;
2791 polling-delay = <1000>;
2792 thermal-sensors = <&tsc 0>;
2793 sustainable-power = <3874>;
2794
2795 trips {
2796 sensor1_crit: sensor1-crit {
2797 temperature = <120000>;
2798 hysteresis = <1000>;
2799 type = "critical";
2800 };
2801 };
2802 };
2803
2804 sensor2_thermal: sensor2-thermal {
2805 polling-delay-passive = <250>;
2806 polling-delay = <1000>;
2807 thermal-sensors = <&tsc 1>;
2808 sustainable-power = <3874>;
2809
2810 trips {
2811 sensor2_crit: sensor2-crit {
2812 temperature = <120000>;
2813 hysteresis = <1000>;
2814 type = "critical";
2815 };
2816 };
2817 };
2818
2819 sensor3_thermal: sensor3-thermal {
2820 polling-delay-passive = <250>;
2821 polling-delay = <1000>;
2822 thermal-sensors = <&tsc 2>;
2823 sustainable-power = <3874>;
2824
2825 cooling-maps {
2826 map0 {
2827 trip = <&target>;
2828 cooling-device = <&a57_0 0 2>;
2829 contribution = <1024>;
2830 };
2831 map1 {
2832 trip = <&target>;
2833 cooling-device = <&a53_0 0 2>;
2834 contribution = <1024>;
2835 };
2836 };
2837 trips {
2838 target: trip-point1 {
2839 temperature = <100000>;
2840 hysteresis = <1000>;
2841 type = "passive";
2842 };
2843
2844 sensor3_crit: sensor3-crit {
2845 temperature = <120000>;
2846 hysteresis = <1000>;
2847 type = "critical";
2848 };
2849 };
2850 };
2851 };
2852
2853 timer {
2854 compatible = "arm,armv8-timer";
2855 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2856 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2857 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2858 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2859 };
2860
2861 /* External USB clocks - can be overridden by the board */
2862 usb3s0_clk: usb3s0 {
2863 compatible = "fixed-clock";
2864 #clock-cells = <0>;
2865 clock-frequency = <0>;
2866 };
2867
2868 usb_extal_clk: usb_extal {
2869 compatible = "fixed-clock";
2870 #clock-cells = <0>;
2871 clock-frequency = <0>;
2872 };
2873 };
