0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
0004 * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
0005 *
0006 * Copyright (C) 2020 Renesas Electronics Corp.
0007 */
0008
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include "hihope-common.dtsi"
0011
0012 / {
0013 audio_clkout: audio-clkout {
0014 /*
0015 * This is same as <&rcar_sound 0>
0016 * but needed to avoid cs2000/rcar_sound probe dead-lock
0017 */
0018 compatible = "fixed-clock";
0019 #clock-cells = <0>;
0020 clock-frequency = <12288000>;
0021 };
0022
0023 wlan_en_reg: regulator-wlan_en {
0024 compatible = "regulator-fixed";
0025 regulator-name = "wlan-en-regulator";
0026 regulator-min-microvolt = <1800000>;
0027 regulator-max-microvolt = <1800000>;
0028 startup-delay-us = <70000>;
0029
0030 gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
0031 enable-active-high;
0032 };
0033
0034 x1801_clk: x1801-clock {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <24576000>;
0038 };
0039 };
0040
0041 &hscif0 {
0042 bluetooth {
0043 compatible = "ti,wl1837-st";
0044 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
0045 };
0046 };
0047
0048 &i2c2 {
0049 pinctrl-0 = <&i2c2_pins>;
0050 pinctrl-names = "default";
0051 status = "okay";
0052
0053 cs2000: clk_multiplier@4f {
0054 #clock-cells = <0>;
0055 compatible = "cirrus,cs2000-cp";
0056 reg = <0x4f>;
0057 clocks = <&audio_clkout>, <&x1801_clk>;
0058 clock-names = "clk_in", "ref_clk";
0059
0060 assigned-clocks = <&cs2000>;
0061 assigned-clock-rates = <24576000>; /* 1/1 divide */
0062 };
0063 };
0064
0065 &pfc {
0066 i2c2_pins: i2c2 {
0067 groups = "i2c2_a";
0068 function = "i2c2";
0069 };
0070
0071 sound_clk_pins: sound_clk {
0072 groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
0073 function = "audio_clk";
0074 };
0075
0076 sound_pins: sound {
0077 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
0078 function = "ssi";
0079 };
0080 };
0081
0082 &rcar_sound {
0083 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
0084 pinctrl-names = "default";
0085 status = "okay";
0086
0087 /* Single DAI */
0088 #sound-dai-cells = <0>;
0089
0090 /* audio_clkout0/1/2/3 */
0091 #clock-cells = <1>;
0092 clock-frequency = <12288000 11289600>;
0093
0094 /*
0095 * Update <audio_clk_b> to <cs2000>
0096 * Switch SW2404 should be at position 1 so that clock from
0097 * CS2000 is connected to AUDIO_CLKB_A
0098 */
0099 clocks = <&cpg CPG_MOD 1005>,
0100 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
0101 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
0102 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
0103 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
0104 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
0105 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
0106 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
0107 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
0108 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
0109 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
0110 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
0111 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
0112 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
0113 <&audio_clk_a>, <&cs2000>,
0114 <&audio_clk_c>,
0115 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
0116
0117 rsnd_port: port {
0118 rsnd_endpoint: endpoint {
0119 remote-endpoint = <&dw_hdmi0_snd_in>;
0120
0121 dai-format = "i2s";
0122 bitclock-master = <&rsnd_endpoint>;
0123 frame-master = <&rsnd_endpoint>;
0124
0125 playback = <&ssi2>;
0126 };
0127 };
0128 };
