0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the Draak board
0004 *
0005 * Copyright (C) 2016-2018 Renesas Electronics Corp.
0006 * Copyright (C) 2017 Glider bvba
0007 */
0008
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/input/input.h>
0011
0012 / {
0013 model = "Renesas Draak board";
0014 compatible = "renesas,draak";
0015
0016 aliases {
0017 serial0 = &scif2;
0018 ethernet0 = &avb;
0019 };
0020
0021 audio_clkout: audio-clkout {
0022 /*
0023 * This is same as <&rcar_sound 0>
0024 * but needed to avoid cs2000/rcar_sound probe dead-lock
0025 */
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <12288000>;
0029 };
0030
0031 backlight: backlight {
0032 compatible = "pwm-backlight";
0033 pwms = <&pwm1 0 50000>;
0034
0035 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
0036 default-brightness-level = <10>;
0037
0038 power-supply = <®_12p0v>;
0039 enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
0040 };
0041
0042 chosen {
0043 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0044 stdout-path = "serial0:115200n8";
0045 };
0046
0047 composite-in {
0048 compatible = "composite-video-connector";
0049
0050 port {
0051 composite_con_in: endpoint {
0052 remote-endpoint = <&adv7180_in>;
0053 };
0054 };
0055 };
0056
0057 hdmi-in {
0058 compatible = "hdmi-connector";
0059 type = "a";
0060
0061 port {
0062 hdmi_con_in: endpoint {
0063 remote-endpoint = <&adv7612_in>;
0064 };
0065 };
0066 };
0067
0068 hdmi-out {
0069 compatible = "hdmi-connector";
0070 type = "a";
0071
0072 port {
0073 hdmi_con_out: endpoint {
0074 remote-endpoint = <&adv7511_out>;
0075 };
0076 };
0077 };
0078
0079 keys {
0080 compatible = "gpio-keys";
0081
0082 pinctrl-0 = <&keys_pins>;
0083 pinctrl-names = "default";
0084
0085 key-1 {
0086 gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
0087 linux,code = <KEY_1>;
0088 label = "SW56-1";
0089 wakeup-source;
0090 debounce-interval = <20>;
0091 };
0092 key-2 {
0093 gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
0094 linux,code = <KEY_2>;
0095 label = "SW56-2";
0096 wakeup-source;
0097 debounce-interval = <20>;
0098 };
0099 key-3 {
0100 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
0101 linux,code = <KEY_3>;
0102 label = "SW56-3";
0103 wakeup-source;
0104 debounce-interval = <20>;
0105 };
0106 key-4 {
0107 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
0108 linux,code = <KEY_4>;
0109 label = "SW56-4";
0110 wakeup-source;
0111 debounce-interval = <20>;
0112 };
0113 };
0114
0115 lvds-decoder {
0116 compatible = "thine,thc63lvd1024";
0117 vcc-supply = <®_3p3v>;
0118
0119 ports {
0120 #address-cells = <1>;
0121 #size-cells = <0>;
0122
0123 port@0 {
0124 reg = <0>;
0125 thc63lvd1024_in: endpoint {
0126 remote-endpoint = <&lvds0_out>;
0127 };
0128 };
0129
0130 port@2 {
0131 reg = <2>;
0132 thc63lvd1024_out: endpoint {
0133 remote-endpoint = <&adv7511_in>;
0134 };
0135 };
0136 };
0137 };
0138
0139 memory@48000000 {
0140 device_type = "memory";
0141 /* first 128MB is reserved for secure area. */
0142 reg = <0x0 0x48000000 0x0 0x18000000>;
0143 };
0144
0145 reg_1p8v: regulator-1p8v {
0146 compatible = "regulator-fixed";
0147 regulator-name = "fixed-1.8V";
0148 regulator-min-microvolt = <1800000>;
0149 regulator-max-microvolt = <1800000>;
0150 regulator-boot-on;
0151 regulator-always-on;
0152 };
0153
0154 reg_3p3v: regulator-3p3v {
0155 compatible = "regulator-fixed";
0156 regulator-name = "fixed-3.3V";
0157 regulator-min-microvolt = <3300000>;
0158 regulator-max-microvolt = <3300000>;
0159 regulator-boot-on;
0160 regulator-always-on;
0161 };
0162
0163 reg_12p0v: regulator-12p0v {
0164 compatible = "regulator-fixed";
0165 regulator-name = "D12.0V";
0166 regulator-min-microvolt = <12000000>;
0167 regulator-max-microvolt = <12000000>;
0168 regulator-boot-on;
0169 regulator-always-on;
0170 };
0171
0172 sound_card: sound {
0173 compatible = "audio-graph-card";
0174
0175 dais = <&rsnd_port0 /* ak4613 */
0176 /* HDMI is not yet supported */
0177 >;
0178 };
0179
0180 vga {
0181 compatible = "vga-connector";
0182
0183 port {
0184 vga_in: endpoint {
0185 remote-endpoint = <&adv7123_out>;
0186 };
0187 };
0188 };
0189
0190 vga-encoder {
0191 compatible = "adi,adv7123";
0192
0193 ports {
0194 #address-cells = <1>;
0195 #size-cells = <0>;
0196
0197 port@0 {
0198 reg = <0>;
0199 adv7123_in: endpoint {
0200 remote-endpoint = <&du_out_rgb>;
0201 };
0202 };
0203 port@1 {
0204 reg = <1>;
0205 adv7123_out: endpoint {
0206 remote-endpoint = <&vga_in>;
0207 };
0208 };
0209 };
0210 };
0211
0212 x12_clk: x12 {
0213 compatible = "fixed-clock";
0214 #clock-cells = <0>;
0215 clock-frequency = <74250000>;
0216 };
0217
0218 x19_clk: x19 {
0219 compatible = "fixed-clock";
0220 #clock-cells = <0>;
0221 clock-frequency = <24576000>;
0222 };
0223 };
0224
0225 &audio_clk_b {
0226 /*
0227 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
0228 * and R-Car Sound uses AUDIO_CLKB.
0229 * Note is that schematic indicates VI4_FIELD conection only
0230 * not AUDIO_CLKB at SoC page.
0231 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
0232 * SW60 should be 1-2.
0233 */
0234
0235 clock-frequency = <22579200>;
0236 };
0237
0238 &avb {
0239 pinctrl-0 = <&avb0_pins>;
0240 pinctrl-names = "default";
0241 renesas,no-ether-link;
0242 phy-handle = <&phy0>;
0243 status = "okay";
0244
0245 phy0: ethernet-phy@0 {
0246 compatible = "ethernet-phy-id0022.1622",
0247 "ethernet-phy-ieee802.3-c22";
0248 rxc-skew-ps = <1500>;
0249 reg = <0>;
0250 interrupt-parent = <&gpio5>;
0251 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0252 reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
0253 /*
0254 * TX clock internal delay mode is required for reliable
0255 * 1Gbps communication using the KSZ9031RNX phy present on
0256 * the Draak board, however, TX clock internal delay mode
0257 * isn't supported on R-Car D3(e). Thus, limit speed to
0258 * 100Mbps for reliable communication.
0259 */
0260 max-speed = <100>;
0261 };
0262 };
0263
0264 &can0 {
0265 pinctrl-0 = <&can0_pins>;
0266 pinctrl-names = "default";
0267 status = "okay";
0268 };
0269
0270 &can1 {
0271 pinctrl-0 = <&can1_pins>;
0272 pinctrl-names = "default";
0273 status = "okay";
0274 };
0275
0276 &du {
0277 pinctrl-0 = <&du_pins>;
0278 pinctrl-names = "default";
0279 status = "okay";
0280
0281 clocks = <&cpg CPG_MOD 724>,
0282 <&cpg CPG_MOD 723>,
0283 <&x12_clk>;
0284 clock-names = "du.0", "du.1", "dclkin.0";
0285
0286 ports {
0287 port@0 {
0288 du_out_rgb: endpoint {
0289 remote-endpoint = <&adv7123_in>;
0290 };
0291 };
0292 };
0293 };
0294
0295 &ehci0 {
0296 dr_mode = "host";
0297 status = "okay";
0298 };
0299
0300 &extal_clk {
0301 clock-frequency = <48000000>;
0302 };
0303
0304 &hsusb {
0305 dr_mode = "host";
0306 status = "okay";
0307 };
0308
0309 &i2c0 {
0310 pinctrl-0 = <&i2c0_pins>;
0311 pinctrl-names = "default";
0312 status = "okay";
0313
0314 ak4613: codec@10 {
0315 compatible = "asahi-kasei,ak4613";
0316 #sound-dai-cells = <0>;
0317 reg = <0x10>;
0318 clocks = <&rcar_sound 0>; /* audio_clkout */
0319
0320 asahi-kasei,in1-single-end;
0321 asahi-kasei,in2-single-end;
0322 asahi-kasei,out1-single-end;
0323 asahi-kasei,out2-single-end;
0324 asahi-kasei,out3-single-end;
0325 asahi-kasei,out4-single-end;
0326 asahi-kasei,out5-single-end;
0327 asahi-kasei,out6-single-end;
0328
0329 port {
0330 ak4613_endpoint: endpoint {
0331 remote-endpoint = <&rsnd_for_ak4613>;
0332 };
0333 };
0334 };
0335
0336 composite-in@20 {
0337 compatible = "adi,adv7180cp";
0338 reg = <0x20>;
0339
0340 ports {
0341 #address-cells = <1>;
0342 #size-cells = <0>;
0343
0344 port@0 {
0345 reg = <0>;
0346 adv7180_in: endpoint {
0347 remote-endpoint = <&composite_con_in>;
0348 };
0349 };
0350
0351 port@3 {
0352 reg = <3>;
0353
0354 /*
0355 * The VIN4 video input path is shared between
0356 * CVBS and HDMI inputs through SW[49-53]
0357 * switches.
0358 *
0359 * CVBS is the default selection, link it to
0360 * VIN4 here.
0361 */
0362 adv7180_out: endpoint {
0363 remote-endpoint = <&vin4_in>;
0364 };
0365 };
0366 };
0367
0368 };
0369
0370 hdmi-encoder@39 {
0371 compatible = "adi,adv7511w";
0372 reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
0373 reg-names = "main", "edid", "cec", "packet";
0374 interrupt-parent = <&gpio1>;
0375 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
0376
0377 adi,input-depth = <8>;
0378 adi,input-colorspace = "rgb";
0379 adi,input-clock = "1x";
0380
0381 ports {
0382 #address-cells = <1>;
0383 #size-cells = <0>;
0384
0385 port@0 {
0386 reg = <0>;
0387 adv7511_in: endpoint {
0388 remote-endpoint = <&thc63lvd1024_out>;
0389 };
0390 };
0391
0392 port@1 {
0393 reg = <1>;
0394 adv7511_out: endpoint {
0395 remote-endpoint = <&hdmi_con_out>;
0396 };
0397 };
0398 };
0399 };
0400
0401 hdmi-decoder@4c {
0402 compatible = "adi,adv7612";
0403 reg = <0x4c>;
0404 default-input = <0>;
0405
0406 ports {
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409
0410 port@0 {
0411 reg = <0>;
0412
0413 adv7612_in: endpoint {
0414 remote-endpoint = <&hdmi_con_in>;
0415 };
0416 };
0417
0418 port@2 {
0419 reg = <2>;
0420
0421 /*
0422 * The VIN4 video input path is shared between
0423 * CVBS and HDMI inputs through SW[49-53]
0424 * switches.
0425 *
0426 * CVBS is the default selection, leave HDMI
0427 * not connected here.
0428 */
0429 adv7612_out: endpoint {
0430 pclk-sample = <0>;
0431 hsync-active = <0>;
0432 vsync-active = <0>;
0433 };
0434 };
0435 };
0436 };
0437
0438 cs2000: clk-multiplier@4f {
0439 #clock-cells = <0>;
0440 compatible = "cirrus,cs2000-cp";
0441 reg = <0x4f>;
0442 clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
0443 clock-names = "clk_in", "ref_clk";
0444
0445 assigned-clocks = <&cs2000>;
0446 assigned-clock-rates = <24576000>; /* 1/1 divide */
0447 };
0448
0449 eeprom@50 {
0450 compatible = "rohm,br24t01", "atmel,24c01";
0451 reg = <0x50>;
0452 pagesize = <8>;
0453 };
0454 };
0455
0456 &i2c1 {
0457 pinctrl-0 = <&i2c1_pins>;
0458 pinctrl-names = "default";
0459 status = "okay";
0460 };
0461
0462 &lvds0 {
0463 status = "okay";
0464
0465 clocks = <&cpg CPG_MOD 727>,
0466 <&x12_clk>,
0467 <&extal_clk>;
0468 clock-names = "fck", "dclkin.0", "extal";
0469
0470 ports {
0471 port@1 {
0472 lvds0_out: endpoint {
0473 remote-endpoint = <&thc63lvd1024_in>;
0474 };
0475 };
0476 };
0477 };
0478
0479 &lvds1 {
0480 /*
0481 * Even though the LVDS1 output is not connected, the encoder must be
0482 * enabled to supply a pixel clock to the DU for the DPAD output when
0483 * LVDS0 is in use.
0484 */
0485 status = "okay";
0486
0487 clocks = <&cpg CPG_MOD 727>,
0488 <&x12_clk>,
0489 <&extal_clk>;
0490 clock-names = "fck", "dclkin.0", "extal";
0491 };
0492
0493 &ohci0 {
0494 dr_mode = "host";
0495 status = "okay";
0496 };
0497
0498 &pfc {
0499 avb0_pins: avb {
0500 groups = "avb0_link", "avb0_mdio", "avb0_mii";
0501 function = "avb0";
0502 };
0503
0504 can0_pins: can0 {
0505 groups = "can0_data_a";
0506 function = "can0";
0507 };
0508
0509 can1_pins: can1 {
0510 groups = "can1_data_a";
0511 function = "can1";
0512 };
0513
0514 du_pins: du {
0515 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
0516 function = "du";
0517 };
0518
0519 i2c0_pins: i2c0 {
0520 groups = "i2c0";
0521 function = "i2c0";
0522 };
0523
0524 i2c1_pins: i2c1 {
0525 groups = "i2c1";
0526 function = "i2c1";
0527 };
0528
0529 keys_pins: keys {
0530 pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
0531 bias-pull-up;
0532 };
0533
0534 pwm0_pins: pwm0 {
0535 groups = "pwm0_c";
0536 function = "pwm0";
0537 };
0538
0539 pwm1_pins: pwm1 {
0540 groups = "pwm1_c";
0541 function = "pwm1";
0542 };
0543
0544 rpc_pins: rpc {
0545 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
0546 "rpc_int";
0547 function = "rpc";
0548 };
0549
0550 scif2_pins: scif2 {
0551 groups = "scif2_data";
0552 function = "scif2";
0553 };
0554
0555 sdhi2_pins: sd2 {
0556 groups = "mmc_data8", "mmc_ctrl";
0557 function = "mmc";
0558 power-source = <1800>;
0559 };
0560
0561 sdhi2_pins_uhs: sd2_uhs {
0562 groups = "mmc_data8", "mmc_ctrl";
0563 function = "mmc";
0564 power-source = <1800>;
0565 };
0566
0567 sound_pins: sound {
0568 groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
0569 function = "ssi";
0570 };
0571
0572 sound_clk_pins: sound-clk {
0573 groups = "audio_clk_a", "audio_clk_b",
0574 "audio_clkout", "audio_clkout1";
0575 function = "audio_clk";
0576 };
0577
0578 usb0_pins: usb0 {
0579 groups = "usb0";
0580 function = "usb0";
0581 };
0582
0583 vin4_pins_cvbs: vin4 {
0584 groups = "vin4_data8", "vin4_sync", "vin4_clk";
0585 function = "vin4";
0586 };
0587 };
0588
0589 &pwm0 {
0590 pinctrl-0 = <&pwm0_pins>;
0591 pinctrl-names = "default";
0592
0593 status = "okay";
0594 };
0595
0596 &pwm1 {
0597 pinctrl-0 = <&pwm1_pins>;
0598 pinctrl-names = "default";
0599
0600 status = "okay";
0601 };
0602
0603 &rcar_sound {
0604 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
0605 pinctrl-names = "default";
0606
0607 /* Single DAI */
0608 #sound-dai-cells = <0>;
0609
0610 /* audio_clkout0/1 */
0611 #clock-cells = <1>;
0612 clock-frequency = <12288000 11289600>;
0613
0614 status = "okay";
0615
0616 clocks = <&cpg CPG_MOD 1005>,
0617 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
0618 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
0619 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
0620 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
0621 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
0622 <&cs2000>, <&audio_clk_b>,
0623 <&cpg CPG_CORE R8A77995_CLK_ZA2>;
0624
0625 ports {
0626 rsnd_port0: port {
0627 rsnd_for_ak4613: endpoint {
0628 remote-endpoint = <&ak4613_endpoint>;
0629 dai-format = "left_j";
0630 bitclock-master = <&rsnd_for_ak4613>;
0631 frame-master = <&rsnd_for_ak4613>;
0632 playback = <&ssi3>, <&src5>, <&dvc0>;
0633 capture = <&ssi4>, <&src6>, <&dvc1>;
0634 };
0635 };
0636 };
0637 };
0638
0639 &rpc {
0640 pinctrl-0 = <&rpc_pins>;
0641 pinctrl-names = "default";
0642
0643 /* Left disabled. To be enabled by firmware when unlocked. */
0644
0645 flash@0 {
0646 compatible = "cypress,hyperflash", "cfi-flash";
0647 reg = <0>;
0648
0649 partitions {
0650 compatible = "fixed-partitions";
0651 #address-cells = <1>;
0652 #size-cells = <1>;
0653
0654 bootparam@0 {
0655 reg = <0x00000000 0x040000>;
0656 read-only;
0657 };
0658 bl2@40000 {
0659 reg = <0x00040000 0x140000>;
0660 read-only;
0661 };
0662 cert_header_sa6@180000 {
0663 reg = <0x00180000 0x040000>;
0664 read-only;
0665 };
0666 bl31@1c0000 {
0667 reg = <0x001c0000 0x040000>;
0668 read-only;
0669 };
0670 tee@200000 {
0671 reg = <0x00200000 0x440000>;
0672 read-only;
0673 };
0674 uboot@640000 {
0675 reg = <0x00640000 0x100000>;
0676 read-only;
0677 };
0678 dtb@740000 {
0679 reg = <0x00740000 0x080000>;
0680 };
0681 kernel@7c0000 {
0682 reg = <0x007c0000 0x1400000>;
0683 };
0684 user@1bc0000 {
0685 reg = <0x01bc0000 0x2440000>;
0686 };
0687 };
0688 };
0689 };
0690
0691 &rwdt {
0692 timeout-sec = <60>;
0693 status = "okay";
0694 };
0695
0696 &scif2 {
0697 pinctrl-0 = <&scif2_pins>;
0698 pinctrl-names = "default";
0699
0700 status = "okay";
0701 };
0702
0703 &sdhi2 {
0704 /* used for on-board eMMC */
0705 pinctrl-0 = <&sdhi2_pins>;
0706 pinctrl-1 = <&sdhi2_pins_uhs>;
0707 pinctrl-names = "default", "state_uhs";
0708
0709 vmmc-supply = <®_3p3v>;
0710 vqmmc-supply = <®_1p8v>;
0711 bus-width = <8>;
0712 mmc-hs200-1_8v;
0713 no-sd;
0714 no-sdio;
0715 non-removable;
0716 status = "okay";
0717 };
0718
0719 &ssi4 {
0720 shared-pin;
0721 };
0722
0723 &usb2_phy0 {
0724 pinctrl-0 = <&usb0_pins>;
0725 pinctrl-names = "default";
0726
0727 renesas,no-otg-pins;
0728 status = "okay";
0729 };
0730
0731 &vin4 {
0732 pinctrl-0 = <&vin4_pins_cvbs>;
0733 pinctrl-names = "default";
0734
0735 status = "okay";
0736
0737 ports {
0738 port {
0739 vin4_in: endpoint {
0740 remote-endpoint = <&adv7180_out>;
0741 };
0742 };
0743 };
0744 };
