0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
0002 /*
0003 * Realtek RTD16xx SoC family
0004 *
0005 * Copyright (c) 2019 Realtek Semiconductor Corp.
0006 * Copyright (c) 2019 Andreas Färber
0007 */
0008
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 interrupt-parent = <&gic>;
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 reserved-memory {
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020 ranges;
0021
0022 rpc_comm: rpc@2f000 {
0023 reg = <0x2f000 0x1000>;
0024 };
0025
0026 rpc_ringbuf: rpc@1ffe000 {
0027 reg = <0x1ffe000 0x4000>;
0028 };
0029
0030 tee: tee@10100000 {
0031 reg = <0x10100000 0xf00000>;
0032 no-map;
0033 };
0034 };
0035
0036 cpus {
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039
0040 cpu0: cpu@0 {
0041 device_type = "cpu";
0042 compatible = "arm,cortex-a55";
0043 reg = <0x0>;
0044 enable-method = "psci";
0045 next-level-cache = <&l2>;
0046 };
0047
0048 cpu1: cpu@100 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a55";
0051 reg = <0x100>;
0052 enable-method = "psci";
0053 next-level-cache = <&l3>;
0054 };
0055
0056 cpu2: cpu@200 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a55";
0059 reg = <0x200>;
0060 enable-method = "psci";
0061 next-level-cache = <&l3>;
0062 };
0063
0064 cpu3: cpu@300 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a55";
0067 reg = <0x300>;
0068 enable-method = "psci";
0069 next-level-cache = <&l3>;
0070 };
0071
0072 cpu4: cpu@400 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a55";
0075 reg = <0x400>;
0076 enable-method = "psci";
0077 next-level-cache = <&l3>;
0078 };
0079
0080 cpu5: cpu@500 {
0081 device_type = "cpu";
0082 compatible = "arm,cortex-a55";
0083 reg = <0x500>;
0084 enable-method = "psci";
0085 next-level-cache = <&l3>;
0086 };
0087
0088 l2: l2-cache {
0089 compatible = "cache";
0090 next-level-cache = <&l3>;
0091
0092 };
0093
0094 l3: l3-cache {
0095 compatible = "cache";
0096 };
0097 };
0098
0099 timer {
0100 compatible = "arm,armv8-timer";
0101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0102 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0103 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0104 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0105 };
0106
0107 arm_pmu: pmu {
0108 compatible = "arm,armv8-pmuv3";
0109 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
0110 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
0111 <&cpu3>, <&cpu4>, <&cpu5>;
0112 };
0113
0114 psci {
0115 compatible = "arm,psci-1.0";
0116 method = "smc";
0117 };
0118
0119 osc27M: osc {
0120 compatible = "fixed-clock";
0121 clock-frequency = <27000000>;
0122 clock-output-names = "osc27M";
0123 #clock-cells = <0>;
0124 };
0125
0126 soc {
0127 compatible = "simple-bus";
0128 #address-cells = <1>;
0129 #size-cells = <1>;
0130 ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
0131 <0x98000000 0x98000000 0x68000000>;
0132
0133 rbus: bus@98000000 {
0134 compatible = "simple-bus";
0135 reg = <0x98000000 0x200000>;
0136 #address-cells = <1>;
0137 #size-cells = <1>;
0138 ranges = <0x0 0x98000000 0x200000>;
0139
0140 crt: syscon@0 {
0141 compatible = "syscon", "simple-mfd";
0142 reg = <0x0 0x1000>;
0143 reg-io-width = <4>;
0144 #address-cells = <1>;
0145 #size-cells = <1>;
0146 ranges = <0x0 0x0 0x1000>;
0147 };
0148
0149 iso: syscon@7000 {
0150 compatible = "syscon", "simple-mfd";
0151 reg = <0x7000 0x1000>;
0152 reg-io-width = <4>;
0153 #address-cells = <1>;
0154 #size-cells = <1>;
0155 ranges = <0x0 0x7000 0x1000>;
0156 };
0157
0158 sb2: syscon@1a000 {
0159 compatible = "syscon", "simple-mfd";
0160 reg = <0x1a000 0x1000>;
0161 reg-io-width = <4>;
0162 #address-cells = <1>;
0163 #size-cells = <1>;
0164 ranges = <0x0 0x1a000 0x1000>;
0165 };
0166
0167 misc: syscon@1b000 {
0168 compatible = "syscon", "simple-mfd";
0169 reg = <0x1b000 0x1000>;
0170 reg-io-width = <4>;
0171 #address-cells = <1>;
0172 #size-cells = <1>;
0173 ranges = <0x0 0x1b000 0x1000>;
0174 };
0175
0176 scpu_wrapper: syscon@1d000 {
0177 compatible = "syscon", "simple-mfd";
0178 reg = <0x1d000 0x1000>;
0179 reg-io-width = <4>;
0180 #address-cells = <1>;
0181 #size-cells = <1>;
0182 ranges = <0x0 0x1d000 0x1000>;
0183 };
0184 };
0185
0186 gic: interrupt-controller@ff100000 {
0187 compatible = "arm,gic-v3";
0188 reg = <0xff100000 0x10000>,
0189 <0xff140000 0xc0000>;
0190 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0191 interrupt-controller;
0192 #interrupt-cells = <3>;
0193 };
0194 };
0195 };
0196
0197 &iso {
0198 uart0: serial0@800 {
0199 compatible = "snps,dw-apb-uart";
0200 reg = <0x800 0x400>;
0201 reg-shift = <2>;
0202 reg-io-width = <4>;
0203 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0204 clock-frequency = <27000000>;
0205 status = "disabled";
0206 };
0207 };
0208
0209 &misc {
0210 uart1: serial1@200 {
0211 compatible = "snps,dw-apb-uart";
0212 reg = <0x200 0x400>;
0213 reg-shift = <2>;
0214 reg-io-width = <4>;
0215 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0216 clock-frequency = <432000000>;
0217 status = "disabled";
0218 };
0219
0220 uart2: serial2@400 {
0221 compatible = "snps,dw-apb-uart";
0222 reg = <0x400 0x400>;
0223 reg-shift = <2>;
0224 reg-io-width = <4>;
0225 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0226 clock-frequency = <432000000>;
0227 status = "disabled";
0228 };
0229 };
