0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
0002 /*
0003 * Realtek RTD1395 SoC family
0004 *
0005 * Copyright (c) 2019 Andreas Färber
0006 */
0007
0008 /memreserve/ 0x0000000000000000 0x000000000002f000;
0009 /memreserve/ 0x000000000002f000 0x00000000000d1000;
0010
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/reset/realtek,rtd1295.h>
0013
0014 / {
0015 interrupt-parent = <&gic>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018
0019 reserved-memory {
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022 ranges;
0023
0024 rpc_comm: rpc@2f000 {
0025 reg = <0x2f000 0x1000>;
0026 };
0027
0028 rpc_ringbuf: rpc@1ffe000 {
0029 reg = <0x1ffe000 0x4000>;
0030 };
0031
0032 tee: tee@10100000 {
0033 reg = <0x10100000 0xf00000>;
0034 no-map;
0035 };
0036 };
0037
0038 arm_pmu: arm-pmu {
0039 compatible = "arm,cortex-a53-pmu";
0040 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0041 };
0042
0043 osc27M: osc {
0044 compatible = "fixed-clock";
0045 clock-frequency = <27000000>;
0046 #clock-cells = <0>;
0047 clock-output-names = "osc27M";
0048 };
0049
0050 soc {
0051 compatible = "simple-bus";
0052 #address-cells = <1>;
0053 #size-cells = <1>;
0054 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
0055 <0x98000000 0x98000000 0x68000000>;
0056
0057 rbus: bus@98000000 {
0058 compatible = "simple-bus";
0059 reg = <0x98000000 0x200000>;
0060 #address-cells = <1>;
0061 #size-cells = <1>;
0062 ranges = <0x0 0x98000000 0x200000>;
0063
0064 crt: syscon@0 {
0065 compatible = "syscon", "simple-mfd";
0066 reg = <0x0 0x1000>;
0067 reg-io-width = <4>;
0068 #address-cells = <1>;
0069 #size-cells = <1>;
0070 ranges = <0x0 0x0 0x1000>;
0071 };
0072
0073 iso: syscon@7000 {
0074 compatible = "syscon", "simple-mfd";
0075 reg = <0x7000 0x1000>;
0076 reg-io-width = <4>;
0077 #address-cells = <1>;
0078 #size-cells = <1>;
0079 ranges = <0x0 0x7000 0x1000>;
0080 };
0081
0082 sb2: syscon@1a000 {
0083 compatible = "syscon", "simple-mfd";
0084 reg = <0x1a000 0x1000>;
0085 reg-io-width = <4>;
0086 #address-cells = <1>;
0087 #size-cells = <1>;
0088 ranges = <0x0 0x1a000 0x1000>;
0089 };
0090
0091 misc: syscon@1b000 {
0092 compatible = "syscon", "simple-mfd";
0093 reg = <0x1b000 0x1000>;
0094 reg-io-width = <4>;
0095 #address-cells = <1>;
0096 #size-cells = <1>;
0097 ranges = <0x0 0x1b000 0x1000>;
0098 };
0099
0100 scpu_wrapper: syscon@1d000 {
0101 compatible = "syscon", "simple-mfd";
0102 reg = <0x1d000 0x2000>;
0103 reg-io-width = <4>;
0104 #address-cells = <1>;
0105 #size-cells = <1>;
0106 ranges = <0x0 0x1d000 0x2000>;
0107 };
0108 };
0109
0110 gic: interrupt-controller@ff011000 {
0111 compatible = "arm,gic-400";
0112 reg = <0xff011000 0x1000>,
0113 <0xff012000 0x2000>,
0114 <0xff014000 0x2000>,
0115 <0xff016000 0x2000>;
0116 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0117 interrupt-controller;
0118 #interrupt-cells = <3>;
0119 };
0120 };
0121 };
0122
0123 &crt {
0124 reset1: reset-controller@0 {
0125 compatible = "snps,dw-low-reset";
0126 reg = <0x0 0x4>;
0127 #reset-cells = <1>;
0128 };
0129
0130 reset2: reset-controller@4 {
0131 compatible = "snps,dw-low-reset";
0132 reg = <0x4 0x4>;
0133 #reset-cells = <1>;
0134 };
0135
0136 reset3: reset-controller@8 {
0137 compatible = "snps,dw-low-reset";
0138 reg = <0x8 0x4>;
0139 #reset-cells = <1>;
0140 };
0141
0142 reset4: reset-controller@50 {
0143 compatible = "snps,dw-low-reset";
0144 reg = <0x50 0x4>;
0145 #reset-cells = <1>;
0146 };
0147 };
0148
0149 &iso {
0150 iso_reset: reset-controller@88 {
0151 compatible = "snps,dw-low-reset";
0152 reg = <0x88 0x4>;
0153 #reset-cells = <1>;
0154 };
0155
0156 wdt: watchdog@680 {
0157 compatible = "realtek,rtd1295-watchdog";
0158 reg = <0x680 0x100>;
0159 clocks = <&osc27M>;
0160 };
0161
0162 uart0: serial@800 {
0163 compatible = "snps,dw-apb-uart";
0164 reg = <0x800 0x400>;
0165 reg-shift = <2>;
0166 reg-io-width = <4>;
0167 clock-frequency = <27000000>;
0168 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
0169 status = "disabled";
0170 };
0171 };
0172
0173 &misc {
0174 uart1: serial@200 {
0175 compatible = "snps,dw-apb-uart";
0176 reg = <0x200 0x100>;
0177 reg-shift = <2>;
0178 reg-io-width = <4>;
0179 clock-frequency = <432000000>;
0180 resets = <&reset2 RTD1295_RSTN_UR1>;
0181 status = "disabled";
0182 };
0183
0184 uart2: serial@400 {
0185 compatible = "snps,dw-apb-uart";
0186 reg = <0x400 0x100>;
0187 reg-shift = <2>;
0188 reg-io-width = <4>;
0189 clock-frequency = <432000000>;
0190 resets = <&reset2 RTD1295_RSTN_UR2>;
0191 status = "disabled";
0192 };
0193 };
