0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
0002 /*
0003 * Realtek RTD1293/RTD1295/RTD1296 SoC
0004 *
0005 * Copyright (c) 2016-2019 Andreas Färber
0006 */
0007
0008 /memreserve/ 0x0000000000000000 0x000000000001f000;
0009 /memreserve/ 0x000000000001f000 0x00000000000e1000;
0010 /memreserve/ 0x0000000001b00000 0x00000000004be000;
0011
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/reset/realtek,rtd1295.h>
0014
0015 / {
0016 interrupt-parent = <&gic>;
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019
0020 reserved-memory {
0021 #address-cells = <1>;
0022 #size-cells = <1>;
0023 ranges;
0024
0025 rpc_comm: rpc@1f000 {
0026 reg = <0x1f000 0x1000>;
0027 };
0028
0029 rpc_ringbuf: rpc@1ffe000 {
0030 reg = <0x1ffe000 0x4000>;
0031 };
0032
0033 tee: tee@10100000 {
0034 reg = <0x10100000 0xf00000>;
0035 no-map;
0036 };
0037 };
0038
0039 arm_pmu: arm-pmu {
0040 compatible = "arm,cortex-a53-pmu";
0041 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0042 };
0043
0044 osc27M: osc {
0045 compatible = "fixed-clock";
0046 clock-frequency = <27000000>;
0047 #clock-cells = <0>;
0048 clock-output-names = "osc27M";
0049 };
0050
0051 soc {
0052 compatible = "simple-bus";
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
0056 /* Exclude up to 2 GiB of RAM */
0057 <0x80000000 0x80000000 0x80000000>;
0058
0059 rbus: bus@98000000 {
0060 compatible = "simple-bus";
0061 reg = <0x98000000 0x200000>;
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 ranges = <0x0 0x98000000 0x200000>;
0065
0066 crt: syscon@0 {
0067 compatible = "syscon", "simple-mfd";
0068 reg = <0x0 0x1800>;
0069 reg-io-width = <4>;
0070 #address-cells = <1>;
0071 #size-cells = <1>;
0072 ranges = <0x0 0x0 0x1800>;
0073 };
0074
0075 iso: syscon@7000 {
0076 compatible = "syscon", "simple-mfd";
0077 reg = <0x7000 0x1000>;
0078 reg-io-width = <4>;
0079 #address-cells = <1>;
0080 #size-cells = <1>;
0081 ranges = <0x0 0x7000 0x1000>;
0082 };
0083
0084 sb2: syscon@1a000 {
0085 compatible = "syscon", "simple-mfd";
0086 reg = <0x1a000 0x1000>;
0087 reg-io-width = <4>;
0088 #address-cells = <1>;
0089 #size-cells = <1>;
0090 ranges = <0x0 0x1a000 0x1000>;
0091 };
0092
0093 misc: syscon@1b000 {
0094 compatible = "syscon", "simple-mfd";
0095 reg = <0x1b000 0x1000>;
0096 reg-io-width = <4>;
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 ranges = <0x0 0x1b000 0x1000>;
0100 };
0101
0102 scpu_wrapper: syscon@1d000 {
0103 compatible = "syscon", "simple-mfd";
0104 reg = <0x1d000 0x2000>;
0105 reg-io-width = <4>;
0106 #address-cells = <1>;
0107 #size-cells = <1>;
0108 ranges = <0x0 0x1d000 0x2000>;
0109 };
0110 };
0111
0112 gic: interrupt-controller@ff011000 {
0113 compatible = "arm,gic-400";
0114 reg = <0xff011000 0x1000>,
0115 <0xff012000 0x2000>,
0116 <0xff014000 0x2000>,
0117 <0xff016000 0x2000>;
0118 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0119 interrupt-controller;
0120 #interrupt-cells = <3>;
0121 };
0122 };
0123 };
0124
0125 &crt {
0126 reset1: reset-controller@0 {
0127 compatible = "snps,dw-low-reset";
0128 reg = <0x0 0x4>;
0129 #reset-cells = <1>;
0130 };
0131
0132 reset2: reset-controller@4 {
0133 compatible = "snps,dw-low-reset";
0134 reg = <0x4 0x4>;
0135 #reset-cells = <1>;
0136 };
0137
0138 reset3: reset-controller@8 {
0139 compatible = "snps,dw-low-reset";
0140 reg = <0x8 0x4>;
0141 #reset-cells = <1>;
0142 };
0143
0144 reset4: reset-controller@50 {
0145 compatible = "snps,dw-low-reset";
0146 reg = <0x50 0x4>;
0147 #reset-cells = <1>;
0148 };
0149 };
0150
0151 &iso {
0152 iso_reset: reset-controller@88 {
0153 compatible = "snps,dw-low-reset";
0154 reg = <0x88 0x4>;
0155 #reset-cells = <1>;
0156 };
0157
0158 wdt: watchdog@680 {
0159 compatible = "realtek,rtd1295-watchdog";
0160 reg = <0x680 0x100>;
0161 clocks = <&osc27M>;
0162 };
0163
0164 uart0: serial@800 {
0165 compatible = "snps,dw-apb-uart";
0166 reg = <0x800 0x400>;
0167 reg-shift = <2>;
0168 reg-io-width = <4>;
0169 clock-frequency = <27000000>;
0170 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
0171 status = "disabled";
0172 };
0173 };
0174
0175 &misc {
0176 uart1: serial@200 {
0177 compatible = "snps,dw-apb-uart";
0178 reg = <0x200 0x100>;
0179 reg-shift = <2>;
0180 reg-io-width = <4>;
0181 clock-frequency = <432000000>;
0182 resets = <&reset2 RTD1295_RSTN_UR1>;
0183 status = "disabled";
0184 };
0185
0186 uart2: serial@400 {
0187 compatible = "snps,dw-apb-uart";
0188 reg = <0x400 0x100>;
0189 reg-shift = <2>;
0190 reg-io-width = <4>;
0191 clock-frequency = <432000000>;
0192 resets = <&reset2 RTD1295_RSTN_UR2>;
0193 status = "disabled";
0194 };
0195 };
