0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
0002 /*
0003 * Realtek RTD1295 SoC
0004 *
0005 * Copyright (c) 2016-2019 Andreas Färber
0006 */
0007
0008 #include "rtd129x.dtsi"
0009
0010 / {
0011 compatible = "realtek,rtd1295";
0012
0013 cpus {
0014 #address-cells = <2>;
0015 #size-cells = <0>;
0016
0017 cpu0: cpu@0 {
0018 device_type = "cpu";
0019 compatible = "arm,cortex-a53";
0020 reg = <0x0 0x0>;
0021 next-level-cache = <&l2>;
0022 };
0023
0024 cpu1: cpu@1 {
0025 device_type = "cpu";
0026 compatible = "arm,cortex-a53";
0027 reg = <0x0 0x1>;
0028 next-level-cache = <&l2>;
0029 };
0030
0031 cpu2: cpu@2 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a53";
0034 reg = <0x0 0x2>;
0035 next-level-cache = <&l2>;
0036 };
0037
0038 cpu3: cpu@3 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a53";
0041 reg = <0x0 0x3>;
0042 next-level-cache = <&l2>;
0043 };
0044
0045 l2: l2-cache {
0046 compatible = "cache";
0047 };
0048 };
0049
0050 timer {
0051 compatible = "arm,armv8-timer";
0052 interrupts = <GIC_PPI 13
0053 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0054 <GIC_PPI 14
0055 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0056 <GIC_PPI 11
0057 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0058 <GIC_PPI 10
0059 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0060 };
0061 };
0062
0063 &arm_pmu {
0064 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0065 };
