0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2021, Linaro Limited
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
0008 #include <dt-bindings/clock/qcom,rpmh.h>
0009 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
0010 #include <dt-bindings/dma/qcom-gpi.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/mailbox/qcom-ipcc.h>
0013 #include <dt-bindings/power/qcom-rpmpd.h>
0014 #include <dt-bindings/interconnect/qcom,sm8450.h>
0015 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0016 #include <dt-bindings/thermal/thermal.h>
0017
0018 / {
0019 interrupt-parent = <&intc>;
0020
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023
0024 chosen { };
0025
0026 clocks {
0027 xo_board: xo-board {
0028 compatible = "fixed-clock";
0029 #clock-cells = <0>;
0030 clock-frequency = <76800000>;
0031 };
0032
0033 sleep_clk: sleep-clk {
0034 compatible = "fixed-clock";
0035 #clock-cells = <0>;
0036 clock-frequency = <32000>;
0037 };
0038 };
0039
0040 cpus {
0041 #address-cells = <2>;
0042 #size-cells = <0>;
0043
0044 CPU0: cpu@0 {
0045 device_type = "cpu";
0046 compatible = "qcom,kryo780";
0047 reg = <0x0 0x0>;
0048 enable-method = "psci";
0049 next-level-cache = <&L2_0>;
0050 power-domains = <&CPU_PD0>;
0051 power-domain-names = "psci";
0052 qcom,freq-domain = <&cpufreq_hw 0>;
0053 #cooling-cells = <2>;
0054 L2_0: l2-cache {
0055 compatible = "cache";
0056 next-level-cache = <&L3_0>;
0057 L3_0: l3-cache {
0058 compatible = "cache";
0059 };
0060 };
0061 };
0062
0063 CPU1: cpu@100 {
0064 device_type = "cpu";
0065 compatible = "qcom,kryo780";
0066 reg = <0x0 0x100>;
0067 enable-method = "psci";
0068 next-level-cache = <&L2_100>;
0069 power-domains = <&CPU_PD1>;
0070 power-domain-names = "psci";
0071 qcom,freq-domain = <&cpufreq_hw 0>;
0072 #cooling-cells = <2>;
0073 L2_100: l2-cache {
0074 compatible = "cache";
0075 next-level-cache = <&L3_0>;
0076 };
0077 };
0078
0079 CPU2: cpu@200 {
0080 device_type = "cpu";
0081 compatible = "qcom,kryo780";
0082 reg = <0x0 0x200>;
0083 enable-method = "psci";
0084 next-level-cache = <&L2_200>;
0085 power-domains = <&CPU_PD2>;
0086 power-domain-names = "psci";
0087 qcom,freq-domain = <&cpufreq_hw 0>;
0088 #cooling-cells = <2>;
0089 L2_200: l2-cache {
0090 compatible = "cache";
0091 next-level-cache = <&L3_0>;
0092 };
0093 };
0094
0095 CPU3: cpu@300 {
0096 device_type = "cpu";
0097 compatible = "qcom,kryo780";
0098 reg = <0x0 0x300>;
0099 enable-method = "psci";
0100 next-level-cache = <&L2_300>;
0101 power-domains = <&CPU_PD3>;
0102 power-domain-names = "psci";
0103 qcom,freq-domain = <&cpufreq_hw 0>;
0104 #cooling-cells = <2>;
0105 L2_300: l2-cache {
0106 compatible = "cache";
0107 next-level-cache = <&L3_0>;
0108 };
0109 };
0110
0111 CPU4: cpu@400 {
0112 device_type = "cpu";
0113 compatible = "qcom,kryo780";
0114 reg = <0x0 0x400>;
0115 enable-method = "psci";
0116 next-level-cache = <&L2_400>;
0117 power-domains = <&CPU_PD4>;
0118 power-domain-names = "psci";
0119 qcom,freq-domain = <&cpufreq_hw 1>;
0120 #cooling-cells = <2>;
0121 L2_400: l2-cache {
0122 compatible = "cache";
0123 next-level-cache = <&L3_0>;
0124 };
0125 };
0126
0127 CPU5: cpu@500 {
0128 device_type = "cpu";
0129 compatible = "qcom,kryo780";
0130 reg = <0x0 0x500>;
0131 enable-method = "psci";
0132 next-level-cache = <&L2_500>;
0133 power-domains = <&CPU_PD5>;
0134 power-domain-names = "psci";
0135 qcom,freq-domain = <&cpufreq_hw 1>;
0136 #cooling-cells = <2>;
0137 L2_500: l2-cache {
0138 compatible = "cache";
0139 next-level-cache = <&L3_0>;
0140 };
0141
0142 };
0143
0144 CPU6: cpu@600 {
0145 device_type = "cpu";
0146 compatible = "qcom,kryo780";
0147 reg = <0x0 0x600>;
0148 enable-method = "psci";
0149 next-level-cache = <&L2_600>;
0150 power-domains = <&CPU_PD6>;
0151 power-domain-names = "psci";
0152 qcom,freq-domain = <&cpufreq_hw 1>;
0153 #cooling-cells = <2>;
0154 L2_600: l2-cache {
0155 compatible = "cache";
0156 next-level-cache = <&L3_0>;
0157 };
0158 };
0159
0160 CPU7: cpu@700 {
0161 device_type = "cpu";
0162 compatible = "qcom,kryo780";
0163 reg = <0x0 0x700>;
0164 enable-method = "psci";
0165 next-level-cache = <&L2_700>;
0166 power-domains = <&CPU_PD7>;
0167 power-domain-names = "psci";
0168 qcom,freq-domain = <&cpufreq_hw 2>;
0169 #cooling-cells = <2>;
0170 L2_700: l2-cache {
0171 compatible = "cache";
0172 next-level-cache = <&L3_0>;
0173 };
0174 };
0175
0176 cpu-map {
0177 cluster0 {
0178 core0 {
0179 cpu = <&CPU0>;
0180 };
0181
0182 core1 {
0183 cpu = <&CPU1>;
0184 };
0185
0186 core2 {
0187 cpu = <&CPU2>;
0188 };
0189
0190 core3 {
0191 cpu = <&CPU3>;
0192 };
0193
0194 core4 {
0195 cpu = <&CPU4>;
0196 };
0197
0198 core5 {
0199 cpu = <&CPU5>;
0200 };
0201
0202 core6 {
0203 cpu = <&CPU6>;
0204 };
0205
0206 core7 {
0207 cpu = <&CPU7>;
0208 };
0209 };
0210 };
0211
0212 idle-states {
0213 entry-method = "psci";
0214
0215 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
0216 compatible = "arm,idle-state";
0217 idle-state-name = "silver-rail-power-collapse";
0218 arm,psci-suspend-param = <0x40000004>;
0219 entry-latency-us = <800>;
0220 exit-latency-us = <750>;
0221 min-residency-us = <4090>;
0222 local-timer-stop;
0223 };
0224
0225 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
0226 compatible = "arm,idle-state";
0227 idle-state-name = "gold-rail-power-collapse";
0228 arm,psci-suspend-param = <0x40000004>;
0229 entry-latency-us = <600>;
0230 exit-latency-us = <1550>;
0231 min-residency-us = <4791>;
0232 local-timer-stop;
0233 };
0234 };
0235
0236 domain-idle-states {
0237 CLUSTER_SLEEP_0: cluster-sleep-0 {
0238 compatible = "domain-idle-state";
0239 idle-state-name = "cluster-l3-off";
0240 arm,psci-suspend-param = <0x41000044>;
0241 entry-latency-us = <1050>;
0242 exit-latency-us = <2500>;
0243 min-residency-us = <5309>;
0244 local-timer-stop;
0245 };
0246
0247 CLUSTER_SLEEP_1: cluster-sleep-1 {
0248 compatible = "domain-idle-state";
0249 idle-state-name = "cluster-power-collapse";
0250 arm,psci-suspend-param = <0x4100c344>;
0251 entry-latency-us = <2700>;
0252 exit-latency-us = <3500>;
0253 min-residency-us = <13959>;
0254 local-timer-stop;
0255 };
0256 };
0257 };
0258
0259 firmware {
0260 scm: scm {
0261 compatible = "qcom,scm-sm8450", "qcom,scm";
0262 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
0263 #reset-cells = <1>;
0264 };
0265 };
0266
0267 clk_virt: interconnect-0 {
0268 compatible = "qcom,sm8450-clk-virt";
0269 #interconnect-cells = <2>;
0270 qcom,bcm-voters = <&apps_bcm_voter>;
0271 };
0272
0273 mc_virt: interconnect-1 {
0274 compatible = "qcom,sm8450-mc-virt";
0275 #interconnect-cells = <2>;
0276 qcom,bcm-voters = <&apps_bcm_voter>;
0277 };
0278
0279 memory@a0000000 {
0280 device_type = "memory";
0281 /* We expect the bootloader to fill in the size */
0282 reg = <0x0 0xa0000000 0x0 0x0>;
0283 };
0284
0285 pmu {
0286 compatible = "arm,armv8-pmuv3";
0287 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0288 };
0289
0290 psci {
0291 compatible = "arm,psci-1.0";
0292 method = "smc";
0293
0294 CPU_PD0: cpu0 {
0295 #power-domain-cells = <0>;
0296 power-domains = <&CLUSTER_PD>;
0297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0298 };
0299
0300 CPU_PD1: cpu1 {
0301 #power-domain-cells = <0>;
0302 power-domains = <&CLUSTER_PD>;
0303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0304 };
0305
0306 CPU_PD2: cpu2 {
0307 #power-domain-cells = <0>;
0308 power-domains = <&CLUSTER_PD>;
0309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0310 };
0311
0312 CPU_PD3: cpu3 {
0313 #power-domain-cells = <0>;
0314 power-domains = <&CLUSTER_PD>;
0315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0316 };
0317
0318 CPU_PD4: cpu4 {
0319 #power-domain-cells = <0>;
0320 power-domains = <&CLUSTER_PD>;
0321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0322 };
0323
0324 CPU_PD5: cpu5 {
0325 #power-domain-cells = <0>;
0326 power-domains = <&CLUSTER_PD>;
0327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0328 };
0329
0330 CPU_PD6: cpu6 {
0331 #power-domain-cells = <0>;
0332 power-domains = <&CLUSTER_PD>;
0333 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0334 };
0335
0336 CPU_PD7: cpu7 {
0337 #power-domain-cells = <0>;
0338 power-domains = <&CLUSTER_PD>;
0339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0340 };
0341
0342 CLUSTER_PD: cpu-cluster0 {
0343 #power-domain-cells = <0>;
0344 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
0345 };
0346 };
0347
0348 qup_opp_table_100mhz: opp-table-qup {
0349 compatible = "operating-points-v2";
0350
0351 opp-50000000 {
0352 opp-hz = /bits/ 64 <50000000>;
0353 required-opps = <&rpmhpd_opp_min_svs>;
0354 };
0355
0356 opp-75000000 {
0357 opp-hz = /bits/ 64 <75000000>;
0358 required-opps = <&rpmhpd_opp_low_svs>;
0359 };
0360
0361 opp-100000000 {
0362 opp-hz = /bits/ 64 <100000000>;
0363 required-opps = <&rpmhpd_opp_svs>;
0364 };
0365 };
0366
0367 reserved_memory: reserved-memory {
0368 #address-cells = <2>;
0369 #size-cells = <2>;
0370 ranges;
0371
0372 hyp_mem: memory@80000000 {
0373 reg = <0x0 0x80000000 0x0 0x600000>;
0374 no-map;
0375 };
0376
0377 xbl_dt_log_mem: memory@80600000 {
0378 reg = <0x0 0x80600000 0x0 0x40000>;
0379 no-map;
0380 };
0381
0382 xbl_ramdump_mem: memory@80640000 {
0383 reg = <0x0 0x80640000 0x0 0x180000>;
0384 no-map;
0385 };
0386
0387 xbl_sc_mem: memory@807c0000 {
0388 reg = <0x0 0x807c0000 0x0 0x40000>;
0389 no-map;
0390 };
0391
0392 aop_image_mem: memory@80800000 {
0393 reg = <0x0 0x80800000 0x0 0x60000>;
0394 no-map;
0395 };
0396
0397 aop_cmd_db_mem: memory@80860000 {
0398 compatible = "qcom,cmd-db";
0399 reg = <0x0 0x80860000 0x0 0x20000>;
0400 no-map;
0401 };
0402
0403 aop_config_mem: memory@80880000 {
0404 reg = <0x0 0x80880000 0x0 0x20000>;
0405 no-map;
0406 };
0407
0408 tme_crash_dump_mem: memory@808a0000 {
0409 reg = <0x0 0x808a0000 0x0 0x40000>;
0410 no-map;
0411 };
0412
0413 tme_log_mem: memory@808e0000 {
0414 reg = <0x0 0x808e0000 0x0 0x4000>;
0415 no-map;
0416 };
0417
0418 uefi_log_mem: memory@808e4000 {
0419 reg = <0x0 0x808e4000 0x0 0x10000>;
0420 no-map;
0421 };
0422
0423 /* secdata region can be reused by apps */
0424 smem: memory@80900000 {
0425 compatible = "qcom,smem";
0426 reg = <0x0 0x80900000 0x0 0x200000>;
0427 hwlocks = <&tcsr_mutex 3>;
0428 no-map;
0429 };
0430
0431 cpucp_fw_mem: memory@80b00000 {
0432 reg = <0x0 0x80b00000 0x0 0x100000>;
0433 no-map;
0434 };
0435
0436 cdsp_secure_heap: memory@80c00000 {
0437 reg = <0x0 0x80c00000 0x0 0x4600000>;
0438 no-map;
0439 };
0440
0441 camera_mem: memory@85200000 {
0442 reg = <0x0 0x85200000 0x0 0x500000>;
0443 no-map;
0444 };
0445
0446 video_mem: memory@85700000 {
0447 reg = <0x0 0x85700000 0x0 0x700000>;
0448 no-map;
0449 };
0450
0451 adsp_mem: memory@85e00000 {
0452 reg = <0x0 0x85e00000 0x0 0x2100000>;
0453 no-map;
0454 };
0455
0456 slpi_mem: memory@88000000 {
0457 reg = <0x0 0x88000000 0x0 0x1900000>;
0458 no-map;
0459 };
0460
0461 cdsp_mem: memory@89900000 {
0462 reg = <0x0 0x89900000 0x0 0x2000000>;
0463 no-map;
0464 };
0465
0466 ipa_fw_mem: memory@8b900000 {
0467 reg = <0x0 0x8b900000 0x0 0x10000>;
0468 no-map;
0469 };
0470
0471 ipa_gsi_mem: memory@8b910000 {
0472 reg = <0x0 0x8b910000 0x0 0xa000>;
0473 no-map;
0474 };
0475
0476 gpu_micro_code_mem: memory@8b91a000 {
0477 reg = <0x0 0x8b91a000 0x0 0x2000>;
0478 no-map;
0479 };
0480
0481 spss_region_mem: memory@8ba00000 {
0482 reg = <0x0 0x8ba00000 0x0 0x180000>;
0483 no-map;
0484 };
0485
0486 /* First part of the "SPU secure shared memory" region */
0487 spu_tz_shared_mem: memory@8bb80000 {
0488 reg = <0x0 0x8bb80000 0x0 0x60000>;
0489 no-map;
0490 };
0491
0492 /* Second part of the "SPU secure shared memory" region */
0493 spu_modem_shared_mem: memory@8bbe0000 {
0494 reg = <0x0 0x8bbe0000 0x0 0x20000>;
0495 no-map;
0496 };
0497
0498 mpss_mem: memory@8bc00000 {
0499 reg = <0x0 0x8bc00000 0x0 0x13200000>;
0500 no-map;
0501 };
0502
0503 cvp_mem: memory@9ee00000 {
0504 reg = <0x0 0x9ee00000 0x0 0x700000>;
0505 no-map;
0506 };
0507
0508 rmtfs_mem: memory@9fd00000 {
0509 compatible = "qcom,rmtfs-mem";
0510 reg = <0x0 0x9fd00000 0x0 0x280000>;
0511 no-map;
0512
0513 qcom,client-id = <1>;
0514 qcom,vmid = <15>;
0515 };
0516
0517 global_sync_mem: memory@a6f00000 {
0518 reg = <0x0 0xa6f00000 0x0 0x100000>;
0519 no-map;
0520 };
0521
0522 /* uefi region can be reused by APPS */
0523
0524 /* Linux kernel image is loaded at 0xa0000000 */
0525
0526 oem_vm_mem: memory@bb000000 {
0527 reg = <0x0 0xbb000000 0x0 0x5000000>;
0528 no-map;
0529 };
0530
0531 mte_mem: memory@c0000000 {
0532 reg = <0x0 0xc0000000 0x0 0x20000000>;
0533 no-map;
0534 };
0535
0536 qheebsp_reserved_mem: memory@e0000000 {
0537 reg = <0x0 0xe0000000 0x0 0x600000>;
0538 no-map;
0539 };
0540
0541 cpusys_vm_mem: memory@e0600000 {
0542 reg = <0x0 0xe0600000 0x0 0x400000>;
0543 no-map;
0544 };
0545
0546 hyp_reserved_mem: memory@e0a00000 {
0547 reg = <0x0 0xe0a00000 0x0 0x100000>;
0548 no-map;
0549 };
0550
0551 trust_ui_vm_mem: memory@e0b00000 {
0552 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
0553 no-map;
0554 };
0555
0556 trust_ui_vm_qrtr: memory@e55f3000 {
0557 reg = <0x0 0xe55f3000 0x0 0x9000>;
0558 no-map;
0559 };
0560
0561 trust_ui_vm_vblk0_ring: memory@e55fc000 {
0562 reg = <0x0 0xe55fc000 0x0 0x4000>;
0563 no-map;
0564 };
0565
0566 trust_ui_vm_swiotlb: memory@e5600000 {
0567 reg = <0x0 0xe5600000 0x0 0x100000>;
0568 no-map;
0569 };
0570
0571 tz_stat_mem: memory@e8800000 {
0572 reg = <0x0 0xe8800000 0x0 0x100000>;
0573 no-map;
0574 };
0575
0576 tags_mem: memory@e8900000 {
0577 reg = <0x0 0xe8900000 0x0 0x1200000>;
0578 no-map;
0579 };
0580
0581 qtee_mem: memory@e9b00000 {
0582 reg = <0x0 0xe9b00000 0x0 0x500000>;
0583 no-map;
0584 };
0585
0586 trusted_apps_mem: memory@ea000000 {
0587 reg = <0x0 0xea000000 0x0 0x3900000>;
0588 no-map;
0589 };
0590
0591 trusted_apps_ext_mem: memory@ed900000 {
0592 reg = <0x0 0xed900000 0x0 0x3b00000>;
0593 no-map;
0594 };
0595 };
0596
0597 smp2p-adsp {
0598 compatible = "qcom,smp2p";
0599 qcom,smem = <443>, <429>;
0600 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
0601 IPCC_MPROC_SIGNAL_SMP2P
0602 IRQ_TYPE_EDGE_RISING>;
0603 mboxes = <&ipcc IPCC_CLIENT_LPASS
0604 IPCC_MPROC_SIGNAL_SMP2P>;
0605
0606 qcom,local-pid = <0>;
0607 qcom,remote-pid = <2>;
0608
0609 smp2p_adsp_out: master-kernel {
0610 qcom,entry-name = "master-kernel";
0611 #qcom,smem-state-cells = <1>;
0612 };
0613
0614 smp2p_adsp_in: slave-kernel {
0615 qcom,entry-name = "slave-kernel";
0616 interrupt-controller;
0617 #interrupt-cells = <2>;
0618 };
0619 };
0620
0621 smp2p-cdsp {
0622 compatible = "qcom,smp2p";
0623 qcom,smem = <94>, <432>;
0624 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
0625 IPCC_MPROC_SIGNAL_SMP2P
0626 IRQ_TYPE_EDGE_RISING>;
0627 mboxes = <&ipcc IPCC_CLIENT_CDSP
0628 IPCC_MPROC_SIGNAL_SMP2P>;
0629
0630 qcom,local-pid = <0>;
0631 qcom,remote-pid = <5>;
0632
0633 smp2p_cdsp_out: master-kernel {
0634 qcom,entry-name = "master-kernel";
0635 #qcom,smem-state-cells = <1>;
0636 };
0637
0638 smp2p_cdsp_in: slave-kernel {
0639 qcom,entry-name = "slave-kernel";
0640 interrupt-controller;
0641 #interrupt-cells = <2>;
0642 };
0643 };
0644
0645 smp2p-modem {
0646 compatible = "qcom,smp2p";
0647 qcom,smem = <435>, <428>;
0648 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
0649 IPCC_MPROC_SIGNAL_SMP2P
0650 IRQ_TYPE_EDGE_RISING>;
0651 mboxes = <&ipcc IPCC_CLIENT_MPSS
0652 IPCC_MPROC_SIGNAL_SMP2P>;
0653
0654 qcom,local-pid = <0>;
0655 qcom,remote-pid = <1>;
0656
0657 smp2p_modem_out: master-kernel {
0658 qcom,entry-name = "master-kernel";
0659 #qcom,smem-state-cells = <1>;
0660 };
0661
0662 smp2p_modem_in: slave-kernel {
0663 qcom,entry-name = "slave-kernel";
0664 interrupt-controller;
0665 #interrupt-cells = <2>;
0666 };
0667
0668 ipa_smp2p_out: ipa-ap-to-modem {
0669 qcom,entry-name = "ipa";
0670 #qcom,smem-state-cells = <1>;
0671 };
0672
0673 ipa_smp2p_in: ipa-modem-to-ap {
0674 qcom,entry-name = "ipa";
0675 interrupt-controller;
0676 #interrupt-cells = <2>;
0677 };
0678 };
0679
0680 smp2p-slpi {
0681 compatible = "qcom,smp2p";
0682 qcom,smem = <481>, <430>;
0683 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
0684 IPCC_MPROC_SIGNAL_SMP2P
0685 IRQ_TYPE_EDGE_RISING>;
0686 mboxes = <&ipcc IPCC_CLIENT_SLPI
0687 IPCC_MPROC_SIGNAL_SMP2P>;
0688
0689 qcom,local-pid = <0>;
0690 qcom,remote-pid = <3>;
0691
0692 smp2p_slpi_out: master-kernel {
0693 qcom,entry-name = "master-kernel";
0694 #qcom,smem-state-cells = <1>;
0695 };
0696
0697 smp2p_slpi_in: slave-kernel {
0698 qcom,entry-name = "slave-kernel";
0699 interrupt-controller;
0700 #interrupt-cells = <2>;
0701 };
0702 };
0703
0704 soc: soc@0 {
0705 #address-cells = <2>;
0706 #size-cells = <2>;
0707 ranges = <0 0 0 0 0x10 0>;
0708 dma-ranges = <0 0 0 0 0x10 0>;
0709 compatible = "simple-bus";
0710
0711 gcc: clock-controller@100000 {
0712 compatible = "qcom,gcc-sm8450";
0713 reg = <0x0 0x00100000 0x0 0x1f4200>;
0714 #clock-cells = <1>;
0715 #reset-cells = <1>;
0716 #power-domain-cells = <1>;
0717 clocks = <&rpmhcc RPMH_CXO_CLK>,
0718 <&pcie0_lane>,
0719 <&pcie1_lane>,
0720 <&sleep_clk>;
0721 clock-names = "bi_tcxo",
0722 "pcie_0_pipe_clk",
0723 "pcie_1_pipe_clk",
0724 "sleep_clk";
0725 };
0726
0727 gpi_dma2: dma-controller@800000 {
0728 compatible = "qcom,sm8450-gpi-dma";
0729 #dma-cells = <3>;
0730 reg = <0 0x800000 0 0x60000>;
0731 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
0732 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
0733 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
0734 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
0735 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
0736 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
0737 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
0738 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
0739 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
0740 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
0741 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
0742 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
0743 dma-channels = <12>;
0744 dma-channel-mask = <0x7e>;
0745 iommus = <&apps_smmu 0x496 0x0>;
0746 status = "disabled";
0747 };
0748
0749 qupv3_id_2: geniqup@8c0000 {
0750 compatible = "qcom,geni-se-qup";
0751 reg = <0x0 0x008c0000 0x0 0x2000>;
0752 clock-names = "m-ahb", "s-ahb";
0753 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
0754 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
0755 iommus = <&apps_smmu 0x483 0x0>;
0756 #address-cells = <2>;
0757 #size-cells = <2>;
0758 ranges;
0759 status = "disabled";
0760
0761 i2c15: i2c@880000 {
0762 compatible = "qcom,geni-i2c";
0763 reg = <0x0 0x00880000 0x0 0x4000>;
0764 clock-names = "se";
0765 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
0766 pinctrl-names = "default";
0767 pinctrl-0 = <&qup_i2c15_data_clk>;
0768 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
0769 #address-cells = <1>;
0770 #size-cells = <0>;
0771 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0772 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
0773 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0774 interconnect-names = "qup-core", "qup-config", "qup-memory";
0775 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
0776 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
0777 dma-names = "tx", "rx";
0778 status = "disabled";
0779 };
0780
0781 spi15: spi@880000 {
0782 compatible = "qcom,geni-spi";
0783 reg = <0x0 0x00880000 0x0 0x4000>;
0784 clock-names = "se";
0785 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
0786 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
0787 pinctrl-names = "default";
0788 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
0789 spi-max-frequency = <50000000>;
0790 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0791 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
0792 interconnect-names = "qup-core", "qup-config";
0793 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
0794 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
0795 dma-names = "tx", "rx";
0796 #address-cells = <1>;
0797 #size-cells = <0>;
0798 status = "disabled";
0799 };
0800
0801 i2c16: i2c@884000 {
0802 compatible = "qcom,geni-i2c";
0803 reg = <0x0 0x00884000 0x0 0x4000>;
0804 clock-names = "se";
0805 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
0806 pinctrl-names = "default";
0807 pinctrl-0 = <&qup_i2c16_data_clk>;
0808 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
0809 #address-cells = <1>;
0810 #size-cells = <0>;
0811 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0812 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
0813 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0814 interconnect-names = "qup-core", "qup-config", "qup-memory";
0815 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
0816 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
0817 dma-names = "tx", "rx";
0818 status = "disabled";
0819 };
0820
0821 spi16: spi@884000 {
0822 compatible = "qcom,geni-spi";
0823 reg = <0x0 0x00884000 0x0 0x4000>;
0824 clock-names = "se";
0825 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
0826 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
0827 pinctrl-names = "default";
0828 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
0829 spi-max-frequency = <50000000>;
0830 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0831 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
0832 interconnect-names = "qup-core", "qup-config";
0833 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
0834 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
0835 dma-names = "tx", "rx";
0836 #address-cells = <1>;
0837 #size-cells = <0>;
0838 status = "disabled";
0839 };
0840
0841 i2c17: i2c@888000 {
0842 compatible = "qcom,geni-i2c";
0843 reg = <0x0 0x00888000 0x0 0x4000>;
0844 clock-names = "se";
0845 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
0846 pinctrl-names = "default";
0847 pinctrl-0 = <&qup_i2c17_data_clk>;
0848 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
0849 #address-cells = <1>;
0850 #size-cells = <0>;
0851 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0852 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
0853 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0854 interconnect-names = "qup-core", "qup-config", "qup-memory";
0855 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
0856 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
0857 dma-names = "tx", "rx";
0858 status = "disabled";
0859 };
0860
0861 spi17: spi@888000 {
0862 compatible = "qcom,geni-spi";
0863 reg = <0x0 0x00888000 0x0 0x4000>;
0864 clock-names = "se";
0865 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
0866 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
0867 pinctrl-names = "default";
0868 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
0869 spi-max-frequency = <50000000>;
0870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
0872 interconnect-names = "qup-core", "qup-config";
0873 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
0874 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
0875 dma-names = "tx", "rx";
0876 #address-cells = <1>;
0877 #size-cells = <0>;
0878 status = "disabled";
0879 };
0880
0881 i2c18: i2c@88c000 {
0882 compatible = "qcom,geni-i2c";
0883 reg = <0x0 0x0088c000 0x0 0x4000>;
0884 clock-names = "se";
0885 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
0886 pinctrl-names = "default";
0887 pinctrl-0 = <&qup_i2c18_data_clk>;
0888 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
0889 #address-cells = <1>;
0890 #size-cells = <0>;
0891 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0892 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
0893 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0894 interconnect-names = "qup-core", "qup-config", "qup-memory";
0895 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
0896 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
0897 dma-names = "tx", "rx";
0898 status = "disabled";
0899 };
0900
0901 spi18: spi@88c000 {
0902 compatible = "qcom,geni-spi";
0903 reg = <0 0x0088c000 0 0x4000>;
0904 clock-names = "se";
0905 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
0906 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
0907 pinctrl-names = "default";
0908 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
0909 spi-max-frequency = <50000000>;
0910 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0911 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
0912 interconnect-names = "qup-core", "qup-config";
0913 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
0914 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
0915 dma-names = "tx", "rx";
0916 #address-cells = <1>;
0917 #size-cells = <0>;
0918 status = "disabled";
0919 };
0920
0921 i2c19: i2c@890000 {
0922 compatible = "qcom,geni-i2c";
0923 reg = <0x0 0x00890000 0x0 0x4000>;
0924 clock-names = "se";
0925 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
0926 pinctrl-names = "default";
0927 pinctrl-0 = <&qup_i2c19_data_clk>;
0928 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
0929 #address-cells = <1>;
0930 #size-cells = <0>;
0931 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0932 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
0933 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0934 interconnect-names = "qup-core", "qup-config", "qup-memory";
0935 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
0936 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
0937 dma-names = "tx", "rx";
0938 status = "disabled";
0939 };
0940
0941 spi19: spi@890000 {
0942 compatible = "qcom,geni-spi";
0943 reg = <0 0x00890000 0 0x4000>;
0944 clock-names = "se";
0945 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
0946 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
0947 pinctrl-names = "default";
0948 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
0949 spi-max-frequency = <50000000>;
0950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
0952 interconnect-names = "qup-core", "qup-config";
0953 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
0954 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
0955 dma-names = "tx", "rx";
0956 #address-cells = <1>;
0957 #size-cells = <0>;
0958 status = "disabled";
0959 };
0960
0961 i2c20: i2c@894000 {
0962 compatible = "qcom,geni-i2c";
0963 reg = <0x0 0x00894000 0x0 0x4000>;
0964 clock-names = "se";
0965 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
0966 pinctrl-names = "default";
0967 pinctrl-0 = <&qup_i2c20_data_clk>;
0968 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
0969 #address-cells = <1>;
0970 #size-cells = <0>;
0971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
0973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0974 interconnect-names = "qup-core", "qup-config", "qup-memory";
0975 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
0976 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
0977 dma-names = "tx", "rx";
0978 status = "disabled";
0979 };
0980
0981 uart20: serial@894000 {
0982 compatible = "qcom,geni-uart";
0983 reg = <0 0x00894000 0 0x4000>;
0984 clock-names = "se";
0985 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
0986 pinctrl-names = "default";
0987 pinctrl-0 = <&qup_uart20_default>;
0988 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
0989 #address-cells = <1>;
0990 #size-cells = <0>;
0991 status = "disabled";
0992 };
0993
0994 spi20: spi@894000 {
0995 compatible = "qcom,geni-spi";
0996 reg = <0 0x00894000 0 0x4000>;
0997 clock-names = "se";
0998 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
0999 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1002 spi-max-frequency = <50000000>;
1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1005 interconnect-names = "qup-core", "qup-config";
1006 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1007 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1008 dma-names = "tx", "rx";
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 status = "disabled";
1012 };
1013
1014 i2c21: i2c@898000 {
1015 compatible = "qcom,geni-i2c";
1016 reg = <0x0 0x00898000 0x0 0x4000>;
1017 clock-names = "se";
1018 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_i2c21_data_clk>;
1021 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1024 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1025 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1026 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1027 interconnect-names = "qup-core", "qup-config", "qup-memory";
1028 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1029 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1030 dma-names = "tx", "rx";
1031 status = "disabled";
1032 };
1033
1034 spi21: spi@898000 {
1035 compatible = "qcom,geni-spi";
1036 reg = <0 0x00898000 0 0x4000>;
1037 clock-names = "se";
1038 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1039 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1040 pinctrl-names = "default";
1041 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1042 spi-max-frequency = <50000000>;
1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1044 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1045 interconnect-names = "qup-core", "qup-config";
1046 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1047 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1048 dma-names = "tx", "rx";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051 status = "disabled";
1052 };
1053 };
1054
1055 gpi_dma0: dma-controller@900000 {
1056 compatible = "qcom,sm8450-gpi-dma";
1057 #dma-cells = <3>;
1058 reg = <0 0x900000 0 0x60000>;
1059 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1063 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1070 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1071 dma-channels = <12>;
1072 dma-channel-mask = <0x7e>;
1073 iommus = <&apps_smmu 0x5b6 0x0>;
1074 status = "disabled";
1075 };
1076
1077 qupv3_id_0: geniqup@9c0000 {
1078 compatible = "qcom,geni-se-qup";
1079 reg = <0x0 0x009c0000 0x0 0x2000>;
1080 clock-names = "m-ahb", "s-ahb";
1081 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1082 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1083 iommus = <&apps_smmu 0x5a3 0x0>;
1084 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1085 interconnect-names = "qup-core";
1086 #address-cells = <2>;
1087 #size-cells = <2>;
1088 ranges;
1089 status = "disabled";
1090
1091 i2c0: i2c@980000 {
1092 compatible = "qcom,geni-i2c";
1093 reg = <0x0 0x00980000 0x0 0x4000>;
1094 clock-names = "se";
1095 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&qup_i2c0_data_clk>;
1098 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1102 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1103 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1104 interconnect-names = "qup-core", "qup-config", "qup-memory";
1105 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1106 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1107 dma-names = "tx", "rx";
1108 status = "disabled";
1109 };
1110
1111 spi0: spi@980000 {
1112 compatible = "qcom,geni-spi";
1113 reg = <0x0 0x00980000 0x0 0x4000>;
1114 clock-names = "se";
1115 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1116 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1119 power-domains = <&rpmhpd SM8450_CX>;
1120 operating-points-v2 = <&qup_opp_table_100mhz>;
1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1122 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1123 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1124 interconnect-names = "qup-core", "qup-config", "qup-memory";
1125 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1126 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1127 dma-names = "tx", "rx";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 status = "disabled";
1131 };
1132
1133 i2c1: i2c@984000 {
1134 compatible = "qcom,geni-i2c";
1135 reg = <0x0 0x00984000 0x0 0x4000>;
1136 clock-names = "se";
1137 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&qup_i2c1_data_clk>;
1140 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1144 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1145 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1146 interconnect-names = "qup-core", "qup-config", "qup-memory";
1147 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1148 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1149 dma-names = "tx", "rx";
1150 status = "disabled";
1151 };
1152
1153 spi1: spi@984000 {
1154 compatible = "qcom,geni-spi";
1155 reg = <0x0 0x00984000 0x0 0x4000>;
1156 clock-names = "se";
1157 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1158 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1159 pinctrl-names = "default";
1160 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1162 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1163 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1164 interconnect-names = "qup-core", "qup-config", "qup-memory";
1165 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1166 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1167 dma-names = "tx", "rx";
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170 status = "disabled";
1171 };
1172
1173 i2c2: i2c@988000 {
1174 compatible = "qcom,geni-i2c";
1175 reg = <0x0 0x00988000 0x0 0x4000>;
1176 clock-names = "se";
1177 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1178 pinctrl-names = "default";
1179 pinctrl-0 = <&qup_i2c2_data_clk>;
1180 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1184 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1185 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1186 interconnect-names = "qup-core", "qup-config", "qup-memory";
1187 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1188 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1189 dma-names = "tx", "rx";
1190 status = "disabled";
1191 };
1192
1193 spi2: spi@988000 {
1194 compatible = "qcom,geni-spi";
1195 reg = <0x0 0x00988000 0x0 0x4000>;
1196 clock-names = "se";
1197 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1198 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1199 pinctrl-names = "default";
1200 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1201 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1202 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1203 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1204 interconnect-names = "qup-core", "qup-config", "qup-memory";
1205 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1206 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1207 dma-names = "tx", "rx";
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1210 status = "disabled";
1211 };
1212
1213
1214 i2c3: i2c@98c000 {
1215 compatible = "qcom,geni-i2c";
1216 reg = <0x0 0x0098c000 0x0 0x4000>;
1217 clock-names = "se";
1218 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1219 pinctrl-names = "default";
1220 pinctrl-0 = <&qup_i2c3_data_clk>;
1221 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1227 interconnect-names = "qup-core", "qup-config", "qup-memory";
1228 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1229 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1230 dma-names = "tx", "rx";
1231 status = "disabled";
1232 };
1233
1234 spi3: spi@98c000 {
1235 compatible = "qcom,geni-spi";
1236 reg = <0x0 0x0098c000 0x0 0x4000>;
1237 clock-names = "se";
1238 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1239 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1246 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1247 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1248 dma-names = "tx", "rx";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 status = "disabled";
1252 };
1253
1254 i2c4: i2c@990000 {
1255 compatible = "qcom,geni-i2c";
1256 reg = <0x0 0x00990000 0x0 0x4000>;
1257 clock-names = "se";
1258 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&qup_i2c4_data_clk>;
1261 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1264 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1265 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1266 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1267 interconnect-names = "qup-core", "qup-config", "qup-memory";
1268 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1269 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1270 dma-names = "tx", "rx";
1271 status = "disabled";
1272 };
1273
1274 spi4: spi@990000 {
1275 compatible = "qcom,geni-spi";
1276 reg = <0x0 0x00990000 0x0 0x4000>;
1277 clock-names = "se";
1278 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1279 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1282 power-domains = <&rpmhpd SM8450_CX>;
1283 operating-points-v2 = <&qup_opp_table_100mhz>;
1284 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1285 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1286 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1287 interconnect-names = "qup-core", "qup-config", "qup-memory";
1288 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1289 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1290 dma-names = "tx", "rx";
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1293 status = "disabled";
1294 };
1295
1296 i2c5: i2c@994000 {
1297 compatible = "qcom,geni-i2c";
1298 reg = <0x0 0x00994000 0x0 0x4000>;
1299 clock-names = "se";
1300 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_i2c5_data_clk>;
1303 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1307 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1308 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1309 interconnect-names = "qup-core", "qup-config", "qup-memory";
1310 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1311 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1312 dma-names = "tx", "rx";
1313 status = "disabled";
1314 };
1315
1316 spi5: spi@994000 {
1317 compatible = "qcom,geni-spi";
1318 reg = <0x0 0x00994000 0x0 0x4000>;
1319 clock-names = "se";
1320 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1321 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1322 pinctrl-names = "default";
1323 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1324 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1325 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1326 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1327 interconnect-names = "qup-core", "qup-config", "qup-memory";
1328 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1329 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1330 dma-names = "tx", "rx";
1331 #address-cells = <1>;
1332 #size-cells = <0>;
1333 status = "disabled";
1334 };
1335
1336
1337 i2c6: i2c@998000 {
1338 compatible = "qcom,geni-i2c";
1339 reg = <0x0 0x998000 0x0 0x4000>;
1340 clock-names = "se";
1341 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1342 pinctrl-names = "default";
1343 pinctrl-0 = <&qup_i2c6_data_clk>;
1344 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1351 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1352 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1353 dma-names = "tx", "rx";
1354 status = "disabled";
1355 };
1356
1357 spi6: spi@998000 {
1358 compatible = "qcom,geni-spi";
1359 reg = <0x0 0x998000 0x0 0x4000>;
1360 clock-names = "se";
1361 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1362 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1363 pinctrl-names = "default";
1364 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1368 interconnect-names = "qup-core", "qup-config", "qup-memory";
1369 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1370 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1371 dma-names = "tx", "rx";
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1374 status = "disabled";
1375 };
1376
1377 uart7: serial@99c000 {
1378 compatible = "qcom,geni-debug-uart";
1379 reg = <0 0x0099c000 0 0x4000>;
1380 clock-names = "se";
1381 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1384 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1387 status = "disabled";
1388 };
1389 };
1390
1391 gpi_dma1: dma-controller@a00000 {
1392 compatible = "qcom,sm8450-gpi-dma";
1393 #dma-cells = <3>;
1394 reg = <0 0xa00000 0 0x60000>;
1395 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1407 dma-channels = <12>;
1408 dma-channel-mask = <0x7e>;
1409 iommus = <&apps_smmu 0x56 0x0>;
1410 status = "disabled";
1411 };
1412
1413 qupv3_id_1: geniqup@ac0000 {
1414 compatible = "qcom,geni-se-qup";
1415 reg = <0x0 0x00ac0000 0x0 0x6000>;
1416 clock-names = "m-ahb", "s-ahb";
1417 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1418 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1419 iommus = <&apps_smmu 0x43 0x0>;
1420 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1421 interconnect-names = "qup-core";
1422 #address-cells = <2>;
1423 #size-cells = <2>;
1424 ranges;
1425 status = "disabled";
1426
1427 i2c8: i2c@a80000 {
1428 compatible = "qcom,geni-i2c";
1429 reg = <0x0 0x00a80000 0x0 0x4000>;
1430 clock-names = "se";
1431 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&qup_i2c8_data_clk>;
1434 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1437 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1438 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1439 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1440 interconnect-names = "qup-core", "qup-config", "qup-memory";
1441 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1442 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1443 dma-names = "tx", "rx";
1444 status = "disabled";
1445 };
1446
1447 spi8: spi@a80000 {
1448 compatible = "qcom,geni-spi";
1449 reg = <0x0 0x00a80000 0x0 0x4000>;
1450 clock-names = "se";
1451 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1452 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1453 pinctrl-names = "default";
1454 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1455 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1456 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1457 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1459 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1460 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1461 dma-names = "tx", "rx";
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464 status = "disabled";
1465 };
1466
1467 i2c9: i2c@a84000 {
1468 compatible = "qcom,geni-i2c";
1469 reg = <0x0 0x00a84000 0x0 0x4000>;
1470 clock-names = "se";
1471 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_i2c9_data_clk>;
1474 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1477 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1478 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1479 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1480 interconnect-names = "qup-core", "qup-config", "qup-memory";
1481 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1482 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1483 dma-names = "tx", "rx";
1484 status = "disabled";
1485 };
1486
1487 spi9: spi@a84000 {
1488 compatible = "qcom,geni-spi";
1489 reg = <0x0 0x00a84000 0x0 0x4000>;
1490 clock-names = "se";
1491 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1492 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1497 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1500 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1501 dma-names = "tx", "rx";
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504 status = "disabled";
1505 };
1506
1507 i2c10: i2c@a88000 {
1508 compatible = "qcom,geni-i2c";
1509 reg = <0x0 0x00a88000 0x0 0x4000>;
1510 clock-names = "se";
1511 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1512 pinctrl-names = "default";
1513 pinctrl-0 = <&qup_i2c10_data_clk>;
1514 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1518 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1520 interconnect-names = "qup-core", "qup-config", "qup-memory";
1521 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1522 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1523 dma-names = "tx", "rx";
1524 status = "disabled";
1525 };
1526
1527 spi10: spi@a88000 {
1528 compatible = "qcom,geni-spi";
1529 reg = <0x0 0x00a88000 0x0 0x4000>;
1530 clock-names = "se";
1531 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1532 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1533 pinctrl-names = "default";
1534 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1536 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1537 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1538 interconnect-names = "qup-core", "qup-config", "qup-memory";
1539 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1540 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1541 dma-names = "tx", "rx";
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 status = "disabled";
1545 };
1546
1547 i2c11: i2c@a8c000 {
1548 compatible = "qcom,geni-i2c";
1549 reg = <0x0 0x00a8c000 0x0 0x4000>;
1550 clock-names = "se";
1551 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1552 pinctrl-names = "default";
1553 pinctrl-0 = <&qup_i2c11_data_clk>;
1554 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1557 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1558 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1559 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1560 interconnect-names = "qup-core", "qup-config", "qup-memory";
1561 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1562 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1563 dma-names = "tx", "rx";
1564 status = "disabled";
1565 };
1566
1567 spi11: spi@a8c000 {
1568 compatible = "qcom,geni-spi";
1569 reg = <0x0 0x00a8c000 0x0 0x4000>;
1570 clock-names = "se";
1571 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1572 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1573 pinctrl-names = "default";
1574 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1577 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1580 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1581 dma-names = "tx", "rx";
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1584 status = "disabled";
1585 };
1586
1587 i2c12: i2c@a90000 {
1588 compatible = "qcom,geni-i2c";
1589 reg = <0x0 0x00a90000 0x0 0x4000>;
1590 clock-names = "se";
1591 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1592 pinctrl-names = "default";
1593 pinctrl-0 = <&qup_i2c12_data_clk>;
1594 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1597 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1598 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1599 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1600 interconnect-names = "qup-core", "qup-config", "qup-memory";
1601 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1602 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1603 dma-names = "tx", "rx";
1604 status = "disabled";
1605 };
1606
1607 spi12: spi@a90000 {
1608 compatible = "qcom,geni-spi";
1609 reg = <0x0 0x00a90000 0x0 0x4000>;
1610 clock-names = "se";
1611 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1612 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1613 pinctrl-names = "default";
1614 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1616 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1617 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1618 interconnect-names = "qup-core", "qup-config", "qup-memory";
1619 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1620 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1621 dma-names = "tx", "rx";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1624 status = "disabled";
1625 };
1626
1627 i2c13: i2c@a94000 {
1628 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00a94000 0 0x4000>;
1630 clock-names = "se";
1631 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1632 pinctrl-names = "default";
1633 pinctrl-0 = <&qup_i2c13_data_clk>;
1634 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1635 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1636 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1637 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1638 interconnect-names = "qup-core", "qup-config", "qup-memory";
1639 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1640 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1641 dma-names = "tx", "rx";
1642 #address-cells = <1>;
1643 #size-cells = <0>;
1644 status = "disabled";
1645 };
1646
1647 spi13: spi@a94000 {
1648 compatible = "qcom,geni-spi";
1649 reg = <0x0 0x00a94000 0x0 0x4000>;
1650 clock-names = "se";
1651 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1652 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1657 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1660 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1661 dma-names = "tx", "rx";
1662 #address-cells = <1>;
1663 #size-cells = <0>;
1664 status = "disabled";
1665 };
1666
1667 i2c14: i2c@a98000 {
1668 compatible = "qcom,geni-i2c";
1669 reg = <0 0x00a98000 0 0x4000>;
1670 clock-names = "se";
1671 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&qup_i2c14_data_clk>;
1674 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1675 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1676 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1677 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1678 interconnect-names = "qup-core", "qup-config", "qup-memory";
1679 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1680 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1681 dma-names = "tx", "rx";
1682 #address-cells = <1>;
1683 #size-cells = <0>;
1684 status = "disabled";
1685 };
1686
1687 spi14: spi@a98000 {
1688 compatible = "qcom,geni-spi";
1689 reg = <0x0 0x00a98000 0x0 0x4000>;
1690 clock-names = "se";
1691 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1692 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1693 pinctrl-names = "default";
1694 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1695 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1696 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1697 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1698 interconnect-names = "qup-core", "qup-config", "qup-memory";
1699 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1700 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1701 dma-names = "tx", "rx";
1702 #address-cells = <1>;
1703 #size-cells = <0>;
1704 status = "disabled";
1705 };
1706 };
1707
1708 pcie0: pci@1c00000 {
1709 compatible = "qcom,pcie-sm8450-pcie0";
1710 reg = <0 0x01c00000 0 0x3000>,
1711 <0 0x60000000 0 0xf1d>,
1712 <0 0x60000f20 0 0xa8>,
1713 <0 0x60001000 0 0x1000>,
1714 <0 0x60100000 0 0x100000>;
1715 reg-names = "parf", "dbi", "elbi", "atu", "config";
1716 device_type = "pci";
1717 linux,pci-domain = <0>;
1718 bus-range = <0x00 0xff>;
1719 num-lanes = <1>;
1720
1721 #address-cells = <3>;
1722 #size-cells = <2>;
1723
1724 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1725 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1726
1727 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1728 interrupt-names = "msi";
1729 #interrupt-cells = <1>;
1730 interrupt-map-mask = <0 0 0 0x7>;
1731 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1732 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1733 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1734 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1735
1736 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1737 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1738 <&pcie0_lane>,
1739 <&rpmhcc RPMH_CXO_CLK>,
1740 <&gcc GCC_PCIE_0_AUX_CLK>,
1741 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1742 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1743 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1744 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1745 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1746 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1747 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1748 clock-names = "pipe",
1749 "pipe_mux",
1750 "phy_pipe",
1751 "ref",
1752 "aux",
1753 "cfg",
1754 "bus_master",
1755 "bus_slave",
1756 "slave_q2a",
1757 "ddrss_sf_tbu",
1758 "aggre0",
1759 "aggre1";
1760
1761 iommus = <&apps_smmu 0x1c00 0x7f>;
1762 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1763 <0x100 &apps_smmu 0x1c01 0x1>;
1764
1765 resets = <&gcc GCC_PCIE_0_BCR>;
1766 reset-names = "pci";
1767
1768 power-domains = <&gcc PCIE_0_GDSC>;
1769 power-domain-names = "gdsc";
1770
1771 phys = <&pcie0_lane>;
1772 phy-names = "pciephy";
1773
1774 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1775 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1776
1777 pinctrl-names = "default";
1778 pinctrl-0 = <&pcie0_default_state>;
1779
1780 status = "disabled";
1781 };
1782
1783 pcie0_phy: phy@1c06000 {
1784 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1785 reg = <0 0x01c06000 0 0x200>;
1786 #address-cells = <2>;
1787 #size-cells = <2>;
1788 ranges;
1789 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1790 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1791 <&gcc GCC_PCIE_0_CLKREF_EN>,
1792 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1793 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1794
1795 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1796 reset-names = "phy";
1797
1798 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1799 assigned-clock-rates = <100000000>;
1800
1801 status = "disabled";
1802
1803 pcie0_lane: phy@1c06200 {
1804 reg = <0 0x1c06e00 0 0x200>, /* tx */
1805 <0 0x1c07000 0 0x200>, /* rx */
1806 <0 0x1c06200 0 0x200>, /* pcs */
1807 <0 0x1c06600 0 0x200>; /* pcs_pcie */
1808 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1809 clock-names = "pipe0";
1810
1811 #clock-cells = <0>;
1812 #phy-cells = <0>;
1813 clock-output-names = "pcie_0_pipe_clk";
1814 };
1815 };
1816
1817 pcie1: pci@1c08000 {
1818 compatible = "qcom,pcie-sm8450-pcie1";
1819 reg = <0 0x01c08000 0 0x3000>,
1820 <0 0x40000000 0 0xf1d>,
1821 <0 0x40000f20 0 0xa8>,
1822 <0 0x40001000 0 0x1000>,
1823 <0 0x40100000 0 0x100000>;
1824 reg-names = "parf", "dbi", "elbi", "atu", "config";
1825 device_type = "pci";
1826 linux,pci-domain = <1>;
1827 bus-range = <0x00 0xff>;
1828 num-lanes = <2>;
1829
1830 #address-cells = <3>;
1831 #size-cells = <2>;
1832
1833 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1834 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1835
1836 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1837 interrupt-names = "msi";
1838 #interrupt-cells = <1>;
1839 interrupt-map-mask = <0 0 0 0x7>;
1840 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1841 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1842 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1843 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1844
1845 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1846 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1847 <&pcie1_lane>,
1848 <&rpmhcc RPMH_CXO_CLK>,
1849 <&gcc GCC_PCIE_1_AUX_CLK>,
1850 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1851 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1852 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1853 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1854 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1855 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1856 clock-names = "pipe",
1857 "pipe_mux",
1858 "phy_pipe",
1859 "ref",
1860 "aux",
1861 "cfg",
1862 "bus_master",
1863 "bus_slave",
1864 "slave_q2a",
1865 "ddrss_sf_tbu",
1866 "aggre1";
1867
1868 iommus = <&apps_smmu 0x1c80 0x7f>;
1869 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1870 <0x100 &apps_smmu 0x1c81 0x1>;
1871
1872 resets = <&gcc GCC_PCIE_1_BCR>;
1873 reset-names = "pci";
1874
1875 power-domains = <&gcc PCIE_1_GDSC>;
1876 power-domain-names = "gdsc";
1877
1878 phys = <&pcie1_lane>;
1879 phy-names = "pciephy";
1880
1881 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
1882 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1883
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&pcie1_default_state>;
1886
1887 status = "disabled";
1888 };
1889
1890 pcie1_phy: phy@1c0f000 {
1891 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1892 reg = <0 0x01c0f000 0 0x200>;
1893 #address-cells = <2>;
1894 #size-cells = <2>;
1895 ranges;
1896 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1897 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1898 <&gcc GCC_PCIE_1_CLKREF_EN>,
1899 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1900 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1901
1902 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1903 reset-names = "phy";
1904
1905 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1906 assigned-clock-rates = <100000000>;
1907
1908 status = "disabled";
1909
1910 pcie1_lane: phy@1c0e000 {
1911 reg = <0 0x1c0e000 0 0x200>, /* tx */
1912 <0 0x1c0e200 0 0x300>, /* rx */
1913 <0 0x1c0f200 0 0x200>, /* pcs */
1914 <0 0x1c0e800 0 0x200>, /* tx */
1915 <0 0x1c0ea00 0 0x300>, /* rx */
1916 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
1917 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1918 clock-names = "pipe0";
1919
1920 #clock-cells = <0>;
1921 #phy-cells = <0>;
1922 clock-output-names = "pcie_1_pipe_clk";
1923 };
1924 };
1925
1926 config_noc: interconnect@1500000 {
1927 compatible = "qcom,sm8450-config-noc";
1928 reg = <0 0x01500000 0 0x1c000>;
1929 #interconnect-cells = <2>;
1930 qcom,bcm-voters = <&apps_bcm_voter>;
1931 };
1932
1933 system_noc: interconnect@1680000 {
1934 compatible = "qcom,sm8450-system-noc";
1935 reg = <0 0x01680000 0 0x1e200>;
1936 #interconnect-cells = <2>;
1937 qcom,bcm-voters = <&apps_bcm_voter>;
1938 };
1939
1940 pcie_noc: interconnect@16c0000 {
1941 compatible = "qcom,sm8450-pcie-anoc";
1942 reg = <0 0x016c0000 0 0xe280>;
1943 #interconnect-cells = <2>;
1944 qcom,bcm-voters = <&apps_bcm_voter>;
1945 };
1946
1947 aggre1_noc: interconnect@16e0000 {
1948 compatible = "qcom,sm8450-aggre1-noc";
1949 reg = <0 0x016e0000 0 0x1c080>;
1950 #interconnect-cells = <2>;
1951 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1952 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1953 qcom,bcm-voters = <&apps_bcm_voter>;
1954 };
1955
1956 aggre2_noc: interconnect@1700000 {
1957 compatible = "qcom,sm8450-aggre2-noc";
1958 reg = <0 0x01700000 0 0x31080>;
1959 #interconnect-cells = <2>;
1960 qcom,bcm-voters = <&apps_bcm_voter>;
1961 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1962 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1963 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1964 <&rpmhcc RPMH_IPA_CLK>;
1965 };
1966
1967 mmss_noc: interconnect@1740000 {
1968 compatible = "qcom,sm8450-mmss-noc";
1969 reg = <0 0x01740000 0 0x1f080>;
1970 #interconnect-cells = <2>;
1971 qcom,bcm-voters = <&apps_bcm_voter>;
1972 };
1973
1974 tcsr_mutex: hwlock@1f40000 {
1975 compatible = "qcom,tcsr-mutex";
1976 reg = <0x0 0x01f40000 0x0 0x40000>;
1977 #hwlock-cells = <1>;
1978 };
1979
1980 usb_1_hsphy: phy@88e3000 {
1981 compatible = "qcom,sm8450-usb-hs-phy",
1982 "qcom,usb-snps-hs-7nm-phy";
1983 reg = <0 0x088e3000 0 0x400>;
1984 status = "disabled";
1985 #phy-cells = <0>;
1986
1987 clocks = <&rpmhcc RPMH_CXO_CLK>;
1988 clock-names = "ref";
1989
1990 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1991 };
1992
1993 usb_1_qmpphy: phy-wrapper@88e9000 {
1994 compatible = "qcom,sm8450-qmp-usb3-phy";
1995 reg = <0 0x088e9000 0 0x200>,
1996 <0 0x088e8000 0 0x20>;
1997 status = "disabled";
1998 #address-cells = <2>;
1999 #size-cells = <2>;
2000 ranges;
2001
2002 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2003 <&rpmhcc RPMH_CXO_CLK>,
2004 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2005 clock-names = "aux", "ref_clk_src", "com_aux";
2006
2007 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2008 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2009 reset-names = "phy", "common";
2010
2011 usb_1_ssphy: phy@88e9200 {
2012 reg = <0 0x088e9200 0 0x200>,
2013 <0 0x088e9400 0 0x200>,
2014 <0 0x088e9c00 0 0x400>,
2015 <0 0x088e9600 0 0x200>,
2016 <0 0x088e9800 0 0x200>,
2017 <0 0x088e9a00 0 0x100>;
2018 #phy-cells = <0>;
2019 #clock-cells = <0>;
2020 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2021 clock-names = "pipe0";
2022 clock-output-names = "usb3_phy_pipe_clk_src";
2023 };
2024 };
2025
2026 remoteproc_slpi: remoteproc@2400000 {
2027 compatible = "qcom,sm8450-slpi-pas";
2028 reg = <0 0x02400000 0 0x4000>;
2029
2030 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2031 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2032 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2033 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2034 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2035 interrupt-names = "wdog", "fatal", "ready",
2036 "handover", "stop-ack";
2037
2038 clocks = <&rpmhcc RPMH_CXO_CLK>;
2039 clock-names = "xo";
2040
2041 power-domains = <&rpmhpd SM8450_LCX>,
2042 <&rpmhpd SM8450_LMX>;
2043 power-domain-names = "lcx", "lmx";
2044
2045 memory-region = <&slpi_mem>;
2046
2047 qcom,qmp = <&aoss_qmp>;
2048
2049 qcom,smem-states = <&smp2p_slpi_out 0>;
2050 qcom,smem-state-names = "stop";
2051
2052 status = "disabled";
2053
2054 glink-edge {
2055 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2056 IPCC_MPROC_SIGNAL_GLINK_QMP
2057 IRQ_TYPE_EDGE_RISING>;
2058 mboxes = <&ipcc IPCC_CLIENT_SLPI
2059 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2060
2061 label = "slpi";
2062 qcom,remote-pid = <3>;
2063
2064 fastrpc {
2065 compatible = "qcom,fastrpc";
2066 qcom,glink-channels = "fastrpcglink-apps-dsp";
2067 label = "sdsp";
2068 #address-cells = <1>;
2069 #size-cells = <0>;
2070
2071 compute-cb@1 {
2072 compatible = "qcom,fastrpc-compute-cb";
2073 reg = <1>;
2074 iommus = <&apps_smmu 0x0541 0x0>;
2075 };
2076
2077 compute-cb@2 {
2078 compatible = "qcom,fastrpc-compute-cb";
2079 reg = <2>;
2080 iommus = <&apps_smmu 0x0542 0x0>;
2081 };
2082
2083 compute-cb@3 {
2084 compatible = "qcom,fastrpc-compute-cb";
2085 reg = <3>;
2086 iommus = <&apps_smmu 0x0543 0x0>;
2087 /* note: shared-cb = <4> in downstream */
2088 };
2089 };
2090 };
2091 };
2092
2093 remoteproc_adsp: remoteproc@30000000 {
2094 compatible = "qcom,sm8450-adsp-pas";
2095 reg = <0 0x030000000 0 0x100>;
2096
2097 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2098 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2099 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2100 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2101 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2102 interrupt-names = "wdog", "fatal", "ready",
2103 "handover", "stop-ack";
2104
2105 clocks = <&rpmhcc RPMH_CXO_CLK>;
2106 clock-names = "xo";
2107
2108 power-domains = <&rpmhpd SM8450_LCX>,
2109 <&rpmhpd SM8450_LMX>;
2110 power-domain-names = "lcx", "lmx";
2111
2112 memory-region = <&adsp_mem>;
2113
2114 qcom,qmp = <&aoss_qmp>;
2115
2116 qcom,smem-states = <&smp2p_adsp_out 0>;
2117 qcom,smem-state-names = "stop";
2118
2119 status = "disabled";
2120
2121 remoteproc_adsp_glink: glink-edge {
2122 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2123 IPCC_MPROC_SIGNAL_GLINK_QMP
2124 IRQ_TYPE_EDGE_RISING>;
2125 mboxes = <&ipcc IPCC_CLIENT_LPASS
2126 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2127
2128 label = "lpass";
2129 qcom,remote-pid = <2>;
2130
2131 fastrpc {
2132 compatible = "qcom,fastrpc";
2133 qcom,glink-channels = "fastrpcglink-apps-dsp";
2134 label = "adsp";
2135 #address-cells = <1>;
2136 #size-cells = <0>;
2137
2138 compute-cb@3 {
2139 compatible = "qcom,fastrpc-compute-cb";
2140 reg = <3>;
2141 iommus = <&apps_smmu 0x1803 0x0>;
2142 };
2143
2144 compute-cb@4 {
2145 compatible = "qcom,fastrpc-compute-cb";
2146 reg = <4>;
2147 iommus = <&apps_smmu 0x1804 0x0>;
2148 };
2149
2150 compute-cb@5 {
2151 compatible = "qcom,fastrpc-compute-cb";
2152 reg = <5>;
2153 iommus = <&apps_smmu 0x1805 0x0>;
2154 };
2155 };
2156 };
2157 };
2158
2159 remoteproc_cdsp: remoteproc@32300000 {
2160 compatible = "qcom,sm8450-cdsp-pas";
2161 reg = <0 0x032300000 0 0x1400000>;
2162
2163 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2164 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2165 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2166 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2167 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2168 interrupt-names = "wdog", "fatal", "ready",
2169 "handover", "stop-ack";
2170
2171 clocks = <&rpmhcc RPMH_CXO_CLK>;
2172 clock-names = "xo";
2173
2174 power-domains = <&rpmhpd SM8450_CX>,
2175 <&rpmhpd SM8450_MXC>;
2176 power-domain-names = "cx", "mxc";
2177
2178 memory-region = <&cdsp_mem>;
2179
2180 qcom,qmp = <&aoss_qmp>;
2181
2182 qcom,smem-states = <&smp2p_cdsp_out 0>;
2183 qcom,smem-state-names = "stop";
2184
2185 status = "disabled";
2186
2187 glink-edge {
2188 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2189 IPCC_MPROC_SIGNAL_GLINK_QMP
2190 IRQ_TYPE_EDGE_RISING>;
2191 mboxes = <&ipcc IPCC_CLIENT_CDSP
2192 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2193
2194 label = "cdsp";
2195 qcom,remote-pid = <5>;
2196
2197 fastrpc {
2198 compatible = "qcom,fastrpc";
2199 qcom,glink-channels = "fastrpcglink-apps-dsp";
2200 label = "cdsp";
2201 #address-cells = <1>;
2202 #size-cells = <0>;
2203
2204 compute-cb@1 {
2205 compatible = "qcom,fastrpc-compute-cb";
2206 reg = <1>;
2207 iommus = <&apps_smmu 0x2161 0x0400>,
2208 <&apps_smmu 0x1021 0x1420>;
2209 };
2210
2211 compute-cb@2 {
2212 compatible = "qcom,fastrpc-compute-cb";
2213 reg = <2>;
2214 iommus = <&apps_smmu 0x2162 0x0400>,
2215 <&apps_smmu 0x1022 0x1420>;
2216 };
2217
2218 compute-cb@3 {
2219 compatible = "qcom,fastrpc-compute-cb";
2220 reg = <3>;
2221 iommus = <&apps_smmu 0x2163 0x0400>,
2222 <&apps_smmu 0x1023 0x1420>;
2223 };
2224
2225 compute-cb@4 {
2226 compatible = "qcom,fastrpc-compute-cb";
2227 reg = <4>;
2228 iommus = <&apps_smmu 0x2164 0x0400>,
2229 <&apps_smmu 0x1024 0x1420>;
2230 };
2231
2232 compute-cb@5 {
2233 compatible = "qcom,fastrpc-compute-cb";
2234 reg = <5>;
2235 iommus = <&apps_smmu 0x2165 0x0400>,
2236 <&apps_smmu 0x1025 0x1420>;
2237 };
2238
2239 compute-cb@6 {
2240 compatible = "qcom,fastrpc-compute-cb";
2241 reg = <6>;
2242 iommus = <&apps_smmu 0x2166 0x0400>,
2243 <&apps_smmu 0x1026 0x1420>;
2244 };
2245
2246 compute-cb@7 {
2247 compatible = "qcom,fastrpc-compute-cb";
2248 reg = <7>;
2249 iommus = <&apps_smmu 0x2167 0x0400>,
2250 <&apps_smmu 0x1027 0x1420>;
2251 };
2252
2253 compute-cb@8 {
2254 compatible = "qcom,fastrpc-compute-cb";
2255 reg = <8>;
2256 iommus = <&apps_smmu 0x2168 0x0400>,
2257 <&apps_smmu 0x1028 0x1420>;
2258 };
2259
2260 /* note: secure cb9 in downstream */
2261 };
2262 };
2263 };
2264
2265 remoteproc_mpss: remoteproc@4080000 {
2266 compatible = "qcom,sm8450-mpss-pas";
2267 reg = <0x0 0x04080000 0x0 0x4040>;
2268
2269 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2270 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2271 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2272 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2273 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2274 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2275 interrupt-names = "wdog", "fatal", "ready", "handover",
2276 "stop-ack", "shutdown-ack";
2277
2278 clocks = <&rpmhcc RPMH_CXO_CLK>;
2279 clock-names = "xo";
2280
2281 power-domains = <&rpmhpd 0>,
2282 <&rpmhpd 12>;
2283 power-domain-names = "cx", "mss";
2284
2285 memory-region = <&mpss_mem>;
2286
2287 qcom,qmp = <&aoss_qmp>;
2288
2289 qcom,smem-states = <&smp2p_modem_out 0>;
2290 qcom,smem-state-names = "stop";
2291
2292 status = "disabled";
2293
2294 glink-edge {
2295 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2296 IPCC_MPROC_SIGNAL_GLINK_QMP
2297 IRQ_TYPE_EDGE_RISING>;
2298 mboxes = <&ipcc IPCC_CLIENT_MPSS
2299 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2300 label = "modem";
2301 qcom,remote-pid = <1>;
2302 };
2303 };
2304
2305 camcc: clock-controller@ade0000 {
2306 compatible = "qcom,sm8450-camcc";
2307 reg = <0 0x0ade0000 0 0x20000>;
2308 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2309 <&rpmhcc RPMH_CXO_CLK>,
2310 <&rpmhcc RPMH_CXO_CLK_A>,
2311 <&sleep_clk>;
2312 power-domains = <&rpmhpd SM8450_MMCX>;
2313 required-opps = <&rpmhpd_opp_low_svs>;
2314 #clock-cells = <1>;
2315 #reset-cells = <1>;
2316 #power-domain-cells = <1>;
2317 status = "disabled";
2318 };
2319
2320 pdc: interrupt-controller@b220000 {
2321 compatible = "qcom,sm8450-pdc", "qcom,pdc";
2322 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2323 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
2324 <94 609 31>, <125 63 1>, <126 716 12>;
2325 #interrupt-cells = <2>;
2326 interrupt-parent = <&intc>;
2327 interrupt-controller;
2328 };
2329
2330 tsens0: thermal-sensor@c263000 {
2331 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2332 reg = <0 0x0c263000 0 0x1000>, /* TM */
2333 <0 0x0c222000 0 0x1000>; /* SROT */
2334 #qcom,sensors = <16>;
2335 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2336 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2337 interrupt-names = "uplow", "critical";
2338 #thermal-sensor-cells = <1>;
2339 };
2340
2341 tsens1: thermal-sensor@c265000 {
2342 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2343 reg = <0 0x0c265000 0 0x1000>, /* TM */
2344 <0 0x0c223000 0 0x1000>; /* SROT */
2345 #qcom,sensors = <16>;
2346 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2348 interrupt-names = "uplow", "critical";
2349 #thermal-sensor-cells = <1>;
2350 };
2351
2352 aoss_qmp: power-controller@c300000 {
2353 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
2354 reg = <0 0x0c300000 0 0x400>;
2355 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2356 IRQ_TYPE_EDGE_RISING>;
2357 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2358
2359 #clock-cells = <0>;
2360 };
2361
2362 ipcc: mailbox@ed18000 {
2363 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
2364 reg = <0 0x0ed18000 0 0x1000>;
2365 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
2366 interrupt-controller;
2367 #interrupt-cells = <3>;
2368 #mbox-cells = <2>;
2369 };
2370
2371 tlmm: pinctrl@f100000 {
2372 compatible = "qcom,sm8450-tlmm";
2373 reg = <0 0x0f100000 0 0x300000>;
2374 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2375 gpio-controller;
2376 #gpio-cells = <2>;
2377 interrupt-controller;
2378 #interrupt-cells = <2>;
2379 gpio-ranges = <&tlmm 0 0 211>;
2380 wakeup-parent = <&pdc>;
2381
2382 pcie0_default_state: pcie0-default-state {
2383 perst {
2384 pins = "gpio94";
2385 function = "gpio";
2386 drive-strength = <2>;
2387 bias-pull-down;
2388 };
2389
2390 clkreq {
2391 pins = "gpio95";
2392 function = "pcie0_clkreqn";
2393 drive-strength = <2>;
2394 bias-pull-up;
2395 };
2396
2397 wake {
2398 pins = "gpio96";
2399 function = "gpio";
2400 drive-strength = <2>;
2401 bias-pull-up;
2402 };
2403 };
2404
2405 pcie1_default_state: pcie1-default-state {
2406 perst {
2407 pins = "gpio97";
2408 function = "gpio";
2409 drive-strength = <2>;
2410 bias-pull-down;
2411 };
2412
2413 clkreq {
2414 pins = "gpio98";
2415 function = "pcie1_clkreqn";
2416 drive-strength = <2>;
2417 bias-pull-up;
2418 };
2419
2420 wake {
2421 pins = "gpio99";
2422 function = "gpio";
2423 drive-strength = <2>;
2424 bias-pull-up;
2425 };
2426 };
2427
2428 qup_i2c0_data_clk: qup-i2c0-data-clk {
2429 pins = "gpio0", "gpio1";
2430 function = "qup0";
2431 };
2432
2433 qup_i2c1_data_clk: qup-i2c1-data-clk {
2434 pins = "gpio4", "gpio5";
2435 function = "qup1";
2436 };
2437
2438 qup_i2c2_data_clk: qup-i2c2-data-clk {
2439 pins = "gpio8", "gpio9";
2440 function = "qup2";
2441 };
2442
2443 qup_i2c3_data_clk: qup-i2c3-data-clk {
2444 pins = "gpio12", "gpio13";
2445 function = "qup3";
2446 };
2447
2448 qup_i2c4_data_clk: qup-i2c4-data-clk {
2449 pins = "gpio16", "gpio17";
2450 function = "qup4";
2451 };
2452
2453 qup_i2c5_data_clk: qup-i2c5-data-clk {
2454 pins = "gpio206", "gpio207";
2455 function = "qup5";
2456 };
2457
2458 qup_i2c6_data_clk: qup-i2c6-data-clk {
2459 pins = "gpio20", "gpio21";
2460 function = "qup6";
2461 };
2462
2463 qup_i2c8_data_clk: qup-i2c8-data-clk {
2464 pins = "gpio28", "gpio29";
2465 function = "qup8";
2466 };
2467
2468 qup_i2c9_data_clk: qup-i2c9-data-clk {
2469 pins = "gpio32", "gpio33";
2470 function = "qup9";
2471 };
2472
2473 qup_i2c10_data_clk: qup-i2c10-data-clk {
2474 pins = "gpio36", "gpio37";
2475 function = "qup10";
2476 };
2477
2478 qup_i2c11_data_clk: qup-i2c11-data-clk {
2479 pins = "gpio40", "gpio41";
2480 function = "qup11";
2481 };
2482
2483 qup_i2c12_data_clk: qup-i2c12-data-clk {
2484 pins = "gpio44", "gpio45";
2485 function = "qup12";
2486 };
2487
2488 qup_i2c13_data_clk: qup-i2c13-data-clk {
2489 pins = "gpio48", "gpio49";
2490 function = "qup13";
2491 drive-strength = <2>;
2492 bias-pull-up;
2493 };
2494
2495 qup_i2c14_data_clk: qup-i2c14-data-clk {
2496 pins = "gpio52", "gpio53";
2497 function = "qup14";
2498 drive-strength = <2>;
2499 bias-pull-up;
2500 };
2501
2502 qup_i2c15_data_clk: qup-i2c15-data-clk {
2503 pins = "gpio56", "gpio57";
2504 function = "qup15";
2505 };
2506
2507 qup_i2c16_data_clk: qup-i2c16-data-clk {
2508 pins = "gpio60", "gpio61";
2509 function = "qup16";
2510 };
2511
2512 qup_i2c17_data_clk: qup-i2c17-data-clk {
2513 pins = "gpio64", "gpio65";
2514 function = "qup17";
2515 };
2516
2517 qup_i2c18_data_clk: qup-i2c18-data-clk {
2518 pins = "gpio68", "gpio69";
2519 function = "qup18";
2520 };
2521
2522 qup_i2c19_data_clk: qup-i2c19-data-clk {
2523 pins = "gpio72", "gpio73";
2524 function = "qup19";
2525 };
2526
2527 qup_i2c20_data_clk: qup-i2c20-data-clk {
2528 pins = "gpio76", "gpio77";
2529 function = "qup20";
2530 };
2531
2532 qup_i2c21_data_clk: qup-i2c21-data-clk {
2533 pins = "gpio80", "gpio81";
2534 function = "qup21";
2535 };
2536
2537 qup_spi0_cs: qup-spi0-cs {
2538 pins = "gpio3";
2539 function = "qup0";
2540 };
2541
2542 qup_spi0_data_clk: qup-spi0-data-clk {
2543 pins = "gpio0", "gpio1", "gpio2";
2544 function = "qup0";
2545 };
2546
2547 qup_spi1_cs: qup-spi1-cs {
2548 pins = "gpio7";
2549 function = "qup1";
2550 };
2551
2552 qup_spi1_data_clk: qup-spi1-data-clk {
2553 pins = "gpio4", "gpio5", "gpio6";
2554 function = "qup1";
2555 };
2556
2557 qup_spi2_cs: qup-spi2-cs {
2558 pins = "gpio11";
2559 function = "qup2";
2560 };
2561
2562 qup_spi2_data_clk: qup-spi2-data-clk {
2563 pins = "gpio8", "gpio9", "gpio10";
2564 function = "qup2";
2565 };
2566
2567 qup_spi3_cs: qup-spi3-cs {
2568 pins = "gpio15";
2569 function = "qup3";
2570 };
2571
2572 qup_spi3_data_clk: qup-spi3-data-clk {
2573 pins = "gpio12", "gpio13", "gpio14";
2574 function = "qup3";
2575 };
2576
2577 qup_spi4_cs: qup-spi4-cs {
2578 pins = "gpio19";
2579 function = "qup4";
2580 drive-strength = <6>;
2581 bias-disable;
2582 };
2583
2584 qup_spi4_data_clk: qup-spi4-data-clk {
2585 pins = "gpio16", "gpio17", "gpio18";
2586 function = "qup4";
2587 };
2588
2589 qup_spi5_cs: qup-spi5-cs {
2590 pins = "gpio85";
2591 function = "qup5";
2592 };
2593
2594 qup_spi5_data_clk: qup-spi5-data-clk {
2595 pins = "gpio206", "gpio207", "gpio84";
2596 function = "qup5";
2597 };
2598
2599 qup_spi6_cs: qup-spi6-cs {
2600 pins = "gpio23";
2601 function = "qup6";
2602 };
2603
2604 qup_spi6_data_clk: qup-spi6-data-clk {
2605 pins = "gpio20", "gpio21", "gpio22";
2606 function = "qup6";
2607 };
2608
2609 qup_spi8_cs: qup-spi8-cs {
2610 pins = "gpio31";
2611 function = "qup8";
2612 };
2613
2614 qup_spi8_data_clk: qup-spi8-data-clk {
2615 pins = "gpio28", "gpio29", "gpio30";
2616 function = "qup8";
2617 };
2618
2619 qup_spi9_cs: qup-spi9-cs {
2620 pins = "gpio35";
2621 function = "qup9";
2622 };
2623
2624 qup_spi9_data_clk: qup-spi9-data-clk {
2625 pins = "gpio32", "gpio33", "gpio34";
2626 function = "qup9";
2627 };
2628
2629 qup_spi10_cs: qup-spi10-cs {
2630 pins = "gpio39";
2631 function = "qup10";
2632 };
2633
2634 qup_spi10_data_clk: qup-spi10-data-clk {
2635 pins = "gpio36", "gpio37", "gpio38";
2636 function = "qup10";
2637 };
2638
2639 qup_spi11_cs: qup-spi11-cs {
2640 pins = "gpio43";
2641 function = "qup11";
2642 };
2643
2644 qup_spi11_data_clk: qup-spi11-data-clk {
2645 pins = "gpio40", "gpio41", "gpio42";
2646 function = "qup11";
2647 };
2648
2649 qup_spi12_cs: qup-spi12-cs {
2650 pins = "gpio47";
2651 function = "qup12";
2652 };
2653
2654 qup_spi12_data_clk: qup-spi12-data-clk {
2655 pins = "gpio44", "gpio45", "gpio46";
2656 function = "qup12";
2657 };
2658
2659 qup_spi13_cs: qup-spi13-cs {
2660 pins = "gpio51";
2661 function = "qup13";
2662 };
2663
2664 qup_spi13_data_clk: qup-spi13-data-clk {
2665 pins = "gpio48", "gpio49", "gpio50";
2666 function = "qup13";
2667 };
2668
2669 qup_spi14_cs: qup-spi14-cs {
2670 pins = "gpio55";
2671 function = "qup14";
2672 };
2673
2674 qup_spi14_data_clk: qup-spi14-data-clk {
2675 pins = "gpio52", "gpio53", "gpio54";
2676 function = "qup14";
2677 };
2678
2679 qup_spi15_cs: qup-spi15-cs {
2680 pins = "gpio59";
2681 function = "qup15";
2682 };
2683
2684 qup_spi15_data_clk: qup-spi15-data-clk {
2685 pins = "gpio56", "gpio57", "gpio58";
2686 function = "qup15";
2687 };
2688
2689 qup_spi16_cs: qup-spi16-cs {
2690 pins = "gpio63";
2691 function = "qup16";
2692 };
2693
2694 qup_spi16_data_clk: qup-spi16-data-clk {
2695 pins = "gpio60", "gpio61", "gpio62";
2696 function = "qup16";
2697 };
2698
2699 qup_spi17_cs: qup-spi17-cs {
2700 pins = "gpio67";
2701 function = "qup17";
2702 };
2703
2704 qup_spi17_data_clk: qup-spi17-data-clk {
2705 pins = "gpio64", "gpio65", "gpio66";
2706 function = "qup17";
2707 };
2708
2709 qup_spi18_cs: qup-spi18-cs {
2710 pins = "gpio71";
2711 function = "qup18";
2712 drive-strength = <6>;
2713 bias-disable;
2714 };
2715
2716 qup_spi18_data_clk: qup-spi18-data-clk {
2717 pins = "gpio68", "gpio69", "gpio70";
2718 function = "qup18";
2719 drive-strength = <6>;
2720 bias-disable;
2721 };
2722
2723 qup_spi19_cs: qup-spi19-cs {
2724 pins = "gpio75";
2725 function = "qup19";
2726 drive-strength = <6>;
2727 bias-disable;
2728 };
2729
2730 qup_spi19_data_clk: qup-spi19-data-clk {
2731 pins = "gpio72", "gpio73", "gpio74";
2732 function = "qup19";
2733 drive-strength = <6>;
2734 bias-disable;
2735 };
2736
2737 qup_spi20_cs: qup-spi20-cs {
2738 pins = "gpio79";
2739 function = "qup20";
2740 };
2741
2742 qup_spi20_data_clk: qup-spi20-data-clk {
2743 pins = "gpio76", "gpio77", "gpio78";
2744 function = "qup20";
2745 };
2746
2747 qup_spi21_cs: qup-spi21-cs {
2748 pins = "gpio83";
2749 function = "qup21";
2750 };
2751
2752 qup_spi21_data_clk: qup-spi21-data-clk {
2753 pins = "gpio80", "gpio81", "gpio82";
2754 function = "qup21";
2755 };
2756
2757 qup_uart7_rx: qup-uart7-rx {
2758 pins = "gpio26";
2759 function = "qup7";
2760 drive-strength = <2>;
2761 bias-disable;
2762 };
2763
2764 qup_uart7_tx: qup-uart7-tx {
2765 pins = "gpio27";
2766 function = "qup7";
2767 drive-strength = <2>;
2768 bias-disable;
2769 };
2770
2771 qup_uart20_default: qup-uart20-default {
2772 pins = "gpio76", "gpio77", "gpio78", "gpio79";
2773 function = "qup20";
2774 };
2775
2776 };
2777
2778 apps_smmu: iommu@15000000 {
2779 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
2780 reg = <0 0x15000000 0 0x100000>;
2781 #iommu-cells = <2>;
2782 #global-interrupts = <1>;
2783 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2785 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2786 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2787 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2788 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2789 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2790 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2791 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2792 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2793 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2794 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2795 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2796 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2798 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2799 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2800 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2801 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2802 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2803 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2804 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2805 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2806 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2807 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2808 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2809 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2810 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2811 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2813 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2814 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2815 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2816 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2817 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2818 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2819 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2820 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2821 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2822 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2823 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2824 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2825 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2826 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2827 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2828 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2829 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2830 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2831 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2832 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2833 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2834 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2835 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2836 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2837 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2838 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2839 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2840 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2841 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2842 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2843 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2844 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2845 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2846 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2847 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2848 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2849 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2850 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2851 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2852 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2853 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2854 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2855 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2856 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2857 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2858 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2859 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2860 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2861 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2862 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2863 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2864 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2865 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2866 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2867 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2868 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2869 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2870 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2871 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2872 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2873 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2874 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2875 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2876 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2877 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2878 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2879 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
2880 };
2881
2882 intc: interrupt-controller@17100000 {
2883 compatible = "arm,gic-v3";
2884 #interrupt-cells = <3>;
2885 interrupt-controller;
2886 #redistributor-regions = <1>;
2887 redistributor-stride = <0x0 0x40000>;
2888 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
2889 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
2890 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2891 #address-cells = <2>;
2892 #size-cells = <2>;
2893 ranges;
2894
2895 gic_its: msi-controller@17140000 {
2896 compatible = "arm,gic-v3-its";
2897 reg = <0x0 0x17140000 0x0 0x20000>;
2898 msi-controller;
2899 #msi-cells = <1>;
2900 };
2901 };
2902
2903 timer@17420000 {
2904 compatible = "arm,armv7-timer-mem";
2905 #address-cells = <1>;
2906 #size-cells = <1>;
2907 ranges = <0 0 0 0x20000000>;
2908 reg = <0x0 0x17420000 0x0 0x1000>;
2909 clock-frequency = <19200000>;
2910
2911 frame@17421000 {
2912 frame-number = <0>;
2913 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2914 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2915 reg = <0x17421000 0x1000>,
2916 <0x17422000 0x1000>;
2917 };
2918
2919 frame@17423000 {
2920 frame-number = <1>;
2921 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2922 reg = <0x17423000 0x1000>;
2923 status = "disabled";
2924 };
2925
2926 frame@17425000 {
2927 frame-number = <2>;
2928 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2929 reg = <0x17425000 0x1000>;
2930 status = "disabled";
2931 };
2932
2933 frame@17427000 {
2934 frame-number = <3>;
2935 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2936 reg = <0x17427000 0x1000>;
2937 status = "disabled";
2938 };
2939
2940 frame@17429000 {
2941 frame-number = <4>;
2942 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2943 reg = <0x17429000 0x1000>;
2944 status = "disabled";
2945 };
2946
2947 frame@1742b000 {
2948 frame-number = <5>;
2949 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2950 reg = <0x1742b000 0x1000>;
2951 status = "disabled";
2952 };
2953
2954 frame@1742d000 {
2955 frame-number = <6>;
2956 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2957 reg = <0x1742d000 0x1000>;
2958 status = "disabled";
2959 };
2960 };
2961
2962 apps_rsc: rsc@17a00000 {
2963 label = "apps_rsc";
2964 compatible = "qcom,rpmh-rsc";
2965 reg = <0x0 0x17a00000 0x0 0x10000>,
2966 <0x0 0x17a10000 0x0 0x10000>,
2967 <0x0 0x17a20000 0x0 0x10000>,
2968 <0x0 0x17a30000 0x0 0x10000>;
2969 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
2970 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2971 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2972 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2973 qcom,tcs-offset = <0xd00>;
2974 qcom,drv-id = <2>;
2975 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
2976 <WAKE_TCS 2>, <CONTROL_TCS 0>;
2977
2978 apps_bcm_voter: bcm-voter {
2979 compatible = "qcom,bcm-voter";
2980 };
2981
2982 rpmhcc: clock-controller {
2983 compatible = "qcom,sm8450-rpmh-clk";
2984 #clock-cells = <1>;
2985 clock-names = "xo";
2986 clocks = <&xo_board>;
2987 };
2988
2989 rpmhpd: power-controller {
2990 compatible = "qcom,sm8450-rpmhpd";
2991 #power-domain-cells = <1>;
2992 operating-points-v2 = <&rpmhpd_opp_table>;
2993
2994 rpmhpd_opp_table: opp-table {
2995 compatible = "operating-points-v2";
2996
2997 rpmhpd_opp_ret: opp1 {
2998 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2999 };
3000
3001 rpmhpd_opp_min_svs: opp2 {
3002 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3003 };
3004
3005 rpmhpd_opp_low_svs: opp3 {
3006 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3007 };
3008
3009 rpmhpd_opp_svs: opp4 {
3010 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3011 };
3012
3013 rpmhpd_opp_svs_l1: opp5 {
3014 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3015 };
3016
3017 rpmhpd_opp_nom: opp6 {
3018 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3019 };
3020
3021 rpmhpd_opp_nom_l1: opp7 {
3022 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3023 };
3024
3025 rpmhpd_opp_nom_l2: opp8 {
3026 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3027 };
3028
3029 rpmhpd_opp_turbo: opp9 {
3030 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3031 };
3032
3033 rpmhpd_opp_turbo_l1: opp10 {
3034 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3035 };
3036 };
3037 };
3038 };
3039
3040 cpufreq_hw: cpufreq@17d91000 {
3041 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
3042 reg = <0 0x17d91000 0 0x1000>,
3043 <0 0x17d92000 0 0x1000>,
3044 <0 0x17d93000 0 0x1000>;
3045 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3046 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3047 clock-names = "xo", "alternate";
3048 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3049 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3050 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3051 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3052 #freq-domain-cells = <1>;
3053 };
3054
3055 gem_noc: interconnect@19100000 {
3056 compatible = "qcom,sm8450-gem-noc";
3057 reg = <0 0x19100000 0 0xbb800>;
3058 #interconnect-cells = <2>;
3059 qcom,bcm-voters = <&apps_bcm_voter>;
3060 };
3061
3062 system-cache-controller@19200000 {
3063 compatible = "qcom,sm8450-llcc";
3064 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
3065 reg-names = "llcc_base", "llcc_broadcast_base";
3066 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3067 };
3068
3069 ufs_mem_hc: ufshc@1d84000 {
3070 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
3071 "jedec,ufs-2.0";
3072 reg = <0 0x01d84000 0 0x3000>;
3073 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
3074 phys = <&ufs_mem_phy_lanes>;
3075 phy-names = "ufsphy";
3076 lanes-per-direction = <2>;
3077 #reset-cells = <1>;
3078 resets = <&gcc GCC_UFS_PHY_BCR>;
3079 reset-names = "rst";
3080
3081 power-domains = <&gcc UFS_PHY_GDSC>;
3082
3083 iommus = <&apps_smmu 0xe0 0x0>;
3084
3085 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
3086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
3087 interconnect-names = "ufs-ddr", "cpu-ufs";
3088 clock-names =
3089 "core_clk",
3090 "bus_aggr_clk",
3091 "iface_clk",
3092 "core_clk_unipro",
3093 "ref_clk",
3094 "tx_lane0_sync_clk",
3095 "rx_lane0_sync_clk",
3096 "rx_lane1_sync_clk";
3097 clocks =
3098 <&gcc GCC_UFS_PHY_AXI_CLK>,
3099 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
3100 <&gcc GCC_UFS_PHY_AHB_CLK>,
3101 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
3102 <&rpmhcc RPMH_CXO_CLK>,
3103 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
3104 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
3105 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
3106 freq-table-hz =
3107 <75000000 300000000>,
3108 <0 0>,
3109 <0 0>,
3110 <75000000 300000000>,
3111 <75000000 300000000>,
3112 <0 0>,
3113 <0 0>,
3114 <0 0>;
3115 status = "disabled";
3116 };
3117
3118 ufs_mem_phy: phy@1d87000 {
3119 compatible = "qcom,sm8450-qmp-ufs-phy";
3120 reg = <0 0x01d87000 0 0xe10>;
3121 #address-cells = <2>;
3122 #size-cells = <2>;
3123 ranges;
3124 clock-names = "ref", "ref_aux", "qref";
3125 clocks = <&rpmhcc RPMH_CXO_CLK>,
3126 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
3127 <&gcc GCC_UFS_0_CLKREF_EN>;
3128
3129 resets = <&ufs_mem_hc 0>;
3130 reset-names = "ufsphy";
3131 status = "disabled";
3132
3133 ufs_mem_phy_lanes: phy@1d87400 {
3134 reg = <0 0x01d87400 0 0x108>,
3135 <0 0x01d87600 0 0x1e0>,
3136 <0 0x01d87c00 0 0x1dc>,
3137 <0 0x01d87800 0 0x108>,
3138 <0 0x01d87a00 0 0x1e0>;
3139 #phy-cells = <0>;
3140 };
3141 };
3142
3143 usb_1: usb@a6f8800 {
3144 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
3145 reg = <0 0x0a6f8800 0 0x400>;
3146 status = "disabled";
3147 #address-cells = <2>;
3148 #size-cells = <2>;
3149 ranges;
3150
3151 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3152 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3153 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3154 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3155 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3156 <&gcc GCC_USB3_0_CLKREF_EN>;
3157 clock-names = "cfg_noc",
3158 "core",
3159 "iface",
3160 "sleep",
3161 "mock_utmi",
3162 "xo";
3163
3164 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3165 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3166 assigned-clock-rates = <19200000>, <200000000>;
3167
3168 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3169 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3170 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3171 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3172 interrupt-names = "hs_phy_irq",
3173 "ss_phy_irq",
3174 "dm_hs_phy_irq",
3175 "dp_hs_phy_irq";
3176
3177 power-domains = <&gcc USB30_PRIM_GDSC>;
3178
3179 resets = <&gcc GCC_USB30_PRIM_BCR>;
3180
3181 usb_1_dwc3: usb@a600000 {
3182 compatible = "snps,dwc3";
3183 reg = <0 0x0a600000 0 0xcd00>;
3184 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3185 iommus = <&apps_smmu 0x0 0x0>;
3186 snps,dis_u2_susphy_quirk;
3187 snps,dis_enblslpm_quirk;
3188 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3189 phy-names = "usb2-phy", "usb3-phy";
3190 };
3191 };
3192
3193 nsp_noc: interconnect@320c0000 {
3194 compatible = "qcom,sm8450-nsp-noc";
3195 reg = <0 0x320c0000 0 0x10000>;
3196 #interconnect-cells = <2>;
3197 qcom,bcm-voters = <&apps_bcm_voter>;
3198 };
3199
3200 lpass_ag_noc: interconnect@3c40000 {
3201 compatible = "qcom,sm8450-lpass-ag-noc";
3202 reg = <0 0x3c40000 0 0x17200>;
3203 #interconnect-cells = <2>;
3204 qcom,bcm-voters = <&apps_bcm_voter>;
3205 };
3206 };
3207
3208 thermal-zones {
3209 aoss0-thermal {
3210 polling-delay-passive = <0>;
3211 polling-delay = <0>;
3212 thermal-sensors = <&tsens0 0>;
3213
3214 trips {
3215 thermal-engine-config {
3216 temperature = <125000>;
3217 hysteresis = <1000>;
3218 type = "passive";
3219 };
3220
3221 reset-mon-cfg {
3222 temperature = <115000>;
3223 hysteresis = <5000>;
3224 type = "passive";
3225 };
3226 };
3227 };
3228
3229 cpuss0-thermal {
3230 polling-delay-passive = <0>;
3231 polling-delay = <0>;
3232 thermal-sensors = <&tsens0 1>;
3233
3234 trips {
3235 thermal-engine-config {
3236 temperature = <125000>;
3237 hysteresis = <1000>;
3238 type = "passive";
3239 };
3240
3241 reset-mon-cfg {
3242 temperature = <115000>;
3243 hysteresis = <5000>;
3244 type = "passive";
3245 };
3246 };
3247 };
3248
3249 cpuss1-thermal {
3250 polling-delay-passive = <0>;
3251 polling-delay = <0>;
3252 thermal-sensors = <&tsens0 2>;
3253
3254 trips {
3255 thermal-engine-config {
3256 temperature = <125000>;
3257 hysteresis = <1000>;
3258 type = "passive";
3259 };
3260
3261 reset-mon-cfg {
3262 temperature = <115000>;
3263 hysteresis = <5000>;
3264 type = "passive";
3265 };
3266 };
3267 };
3268
3269 cpuss3-thermal {
3270 polling-delay-passive = <0>;
3271 polling-delay = <0>;
3272 thermal-sensors = <&tsens0 3>;
3273
3274 trips {
3275 thermal-engine-config {
3276 temperature = <125000>;
3277 hysteresis = <1000>;
3278 type = "passive";
3279 };
3280
3281 reset-mon-cfg {
3282 temperature = <115000>;
3283 hysteresis = <5000>;
3284 type = "passive";
3285 };
3286 };
3287 };
3288
3289 cpuss4-thermal {
3290 polling-delay-passive = <0>;
3291 polling-delay = <0>;
3292 thermal-sensors = <&tsens0 4>;
3293
3294 trips {
3295 thermal-engine-config {
3296 temperature = <125000>;
3297 hysteresis = <1000>;
3298 type = "passive";
3299 };
3300
3301 reset-mon-cfg {
3302 temperature = <115000>;
3303 hysteresis = <5000>;
3304 type = "passive";
3305 };
3306 };
3307 };
3308
3309 cpu4-top-thermal {
3310 polling-delay-passive = <0>;
3311 polling-delay = <0>;
3312 thermal-sensors = <&tsens0 5>;
3313
3314 trips {
3315 cpu4_top_alert0: trip-point0 {
3316 temperature = <90000>;
3317 hysteresis = <2000>;
3318 type = "passive";
3319 };
3320
3321 cpu4_top_alert1: trip-point1 {
3322 temperature = <95000>;
3323 hysteresis = <2000>;
3324 type = "passive";
3325 };
3326
3327 cpu4_top_crit: cpu_crit {
3328 temperature = <110000>;
3329 hysteresis = <1000>;
3330 type = "critical";
3331 };
3332 };
3333 };
3334
3335 cpu4-bottom-thermal {
3336 polling-delay-passive = <0>;
3337 polling-delay = <0>;
3338 thermal-sensors = <&tsens0 6>;
3339
3340 trips {
3341 cpu4_bottom_alert0: trip-point0 {
3342 temperature = <90000>;
3343 hysteresis = <2000>;
3344 type = "passive";
3345 };
3346
3347 cpu4_bottom_alert1: trip-point1 {
3348 temperature = <95000>;
3349 hysteresis = <2000>;
3350 type = "passive";
3351 };
3352
3353 cpu4_bottom_crit: cpu_crit {
3354 temperature = <110000>;
3355 hysteresis = <1000>;
3356 type = "critical";
3357 };
3358 };
3359 };
3360
3361 cpu5-top-thermal {
3362 polling-delay-passive = <0>;
3363 polling-delay = <0>;
3364 thermal-sensors = <&tsens0 7>;
3365
3366 trips {
3367 cpu5_top_alert0: trip-point0 {
3368 temperature = <90000>;
3369 hysteresis = <2000>;
3370 type = "passive";
3371 };
3372
3373 cpu5_top_alert1: trip-point1 {
3374 temperature = <95000>;
3375 hysteresis = <2000>;
3376 type = "passive";
3377 };
3378
3379 cpu5_top_crit: cpu_crit {
3380 temperature = <110000>;
3381 hysteresis = <1000>;
3382 type = "critical";
3383 };
3384 };
3385 };
3386
3387 cpu5-bottom-thermal {
3388 polling-delay-passive = <0>;
3389 polling-delay = <0>;
3390 thermal-sensors = <&tsens0 8>;
3391
3392 trips {
3393 cpu5_bottom_alert0: trip-point0 {
3394 temperature = <90000>;
3395 hysteresis = <2000>;
3396 type = "passive";
3397 };
3398
3399 cpu5_bottom_alert1: trip-point1 {
3400 temperature = <95000>;
3401 hysteresis = <2000>;
3402 type = "passive";
3403 };
3404
3405 cpu5_bottom_crit: cpu_crit {
3406 temperature = <110000>;
3407 hysteresis = <1000>;
3408 type = "critical";
3409 };
3410 };
3411 };
3412
3413 cpu6-top-thermal {
3414 polling-delay-passive = <0>;
3415 polling-delay = <0>;
3416 thermal-sensors = <&tsens0 9>;
3417
3418 trips {
3419 cpu6_top_alert0: trip-point0 {
3420 temperature = <90000>;
3421 hysteresis = <2000>;
3422 type = "passive";
3423 };
3424
3425 cpu6_top_alert1: trip-point1 {
3426 temperature = <95000>;
3427 hysteresis = <2000>;
3428 type = "passive";
3429 };
3430
3431 cpu6_top_crit: cpu_crit {
3432 temperature = <110000>;
3433 hysteresis = <1000>;
3434 type = "critical";
3435 };
3436 };
3437 };
3438
3439 cpu6-bottom-thermal {
3440 polling-delay-passive = <0>;
3441 polling-delay = <0>;
3442 thermal-sensors = <&tsens0 10>;
3443
3444 trips {
3445 cpu6_bottom_alert0: trip-point0 {
3446 temperature = <90000>;
3447 hysteresis = <2000>;
3448 type = "passive";
3449 };
3450
3451 cpu6_bottom_alert1: trip-point1 {
3452 temperature = <95000>;
3453 hysteresis = <2000>;
3454 type = "passive";
3455 };
3456
3457 cpu6_bottom_crit: cpu_crit {
3458 temperature = <110000>;
3459 hysteresis = <1000>;
3460 type = "critical";
3461 };
3462 };
3463 };
3464
3465 cpu7-top-thermal {
3466 polling-delay-passive = <0>;
3467 polling-delay = <0>;
3468 thermal-sensors = <&tsens0 11>;
3469
3470 trips {
3471 cpu7_top_alert0: trip-point0 {
3472 temperature = <90000>;
3473 hysteresis = <2000>;
3474 type = "passive";
3475 };
3476
3477 cpu7_top_alert1: trip-point1 {
3478 temperature = <95000>;
3479 hysteresis = <2000>;
3480 type = "passive";
3481 };
3482
3483 cpu7_top_crit: cpu_crit {
3484 temperature = <110000>;
3485 hysteresis = <1000>;
3486 type = "critical";
3487 };
3488 };
3489 };
3490
3491 cpu7-middle-thermal {
3492 polling-delay-passive = <0>;
3493 polling-delay = <0>;
3494 thermal-sensors = <&tsens0 12>;
3495
3496 trips {
3497 cpu7_middle_alert0: trip-point0 {
3498 temperature = <90000>;
3499 hysteresis = <2000>;
3500 type = "passive";
3501 };
3502
3503 cpu7_middle_alert1: trip-point1 {
3504 temperature = <95000>;
3505 hysteresis = <2000>;
3506 type = "passive";
3507 };
3508
3509 cpu7_middle_crit: cpu_crit {
3510 temperature = <110000>;
3511 hysteresis = <1000>;
3512 type = "critical";
3513 };
3514 };
3515 };
3516
3517 cpu7-bottom-thermal {
3518 polling-delay-passive = <0>;
3519 polling-delay = <0>;
3520 thermal-sensors = <&tsens0 13>;
3521
3522 trips {
3523 cpu7_bottom_alert0: trip-point0 {
3524 temperature = <90000>;
3525 hysteresis = <2000>;
3526 type = "passive";
3527 };
3528
3529 cpu7_bottom_alert1: trip-point1 {
3530 temperature = <95000>;
3531 hysteresis = <2000>;
3532 type = "passive";
3533 };
3534
3535 cpu7_bottom_crit: cpu_crit {
3536 temperature = <110000>;
3537 hysteresis = <1000>;
3538 type = "critical";
3539 };
3540 };
3541 };
3542
3543 gpu-top-thermal {
3544 polling-delay-passive = <10>;
3545 polling-delay = <0>;
3546 thermal-sensors = <&tsens0 14>;
3547
3548 trips {
3549 thermal-engine-config {
3550 temperature = <125000>;
3551 hysteresis = <1000>;
3552 type = "passive";
3553 };
3554
3555 thermal-hal-config {
3556 temperature = <125000>;
3557 hysteresis = <1000>;
3558 type = "passive";
3559 };
3560
3561 reset-mon-cfg {
3562 temperature = <115000>;
3563 hysteresis = <5000>;
3564 type = "passive";
3565 };
3566
3567 gpu0_tj_cfg: tj_cfg {
3568 temperature = <95000>;
3569 hysteresis = <5000>;
3570 type = "passive";
3571 };
3572 };
3573 };
3574
3575 gpu-bottom-thermal {
3576 polling-delay-passive = <10>;
3577 polling-delay = <0>;
3578 thermal-sensors = <&tsens0 15>;
3579
3580 trips {
3581 thermal-engine-config {
3582 temperature = <125000>;
3583 hysteresis = <1000>;
3584 type = "passive";
3585 };
3586
3587 thermal-hal-config {
3588 temperature = <125000>;
3589 hysteresis = <1000>;
3590 type = "passive";
3591 };
3592
3593 reset-mon-cfg {
3594 temperature = <115000>;
3595 hysteresis = <5000>;
3596 type = "passive";
3597 };
3598
3599 gpu1_tj_cfg: tj_cfg {
3600 temperature = <95000>;
3601 hysteresis = <5000>;
3602 type = "passive";
3603 };
3604 };
3605 };
3606
3607 aoss1-thermal {
3608 polling-delay-passive = <0>;
3609 polling-delay = <0>;
3610 thermal-sensors = <&tsens1 0>;
3611
3612 trips {
3613 thermal-engine-config {
3614 temperature = <125000>;
3615 hysteresis = <1000>;
3616 type = "passive";
3617 };
3618
3619 reset-mon-cfg {
3620 temperature = <115000>;
3621 hysteresis = <5000>;
3622 type = "passive";
3623 };
3624 };
3625 };
3626
3627 cpu0-thermal {
3628 polling-delay-passive = <0>;
3629 polling-delay = <0>;
3630 thermal-sensors = <&tsens1 1>;
3631
3632 trips {
3633 cpu0_alert0: trip-point0 {
3634 temperature = <90000>;
3635 hysteresis = <2000>;
3636 type = "passive";
3637 };
3638
3639 cpu0_alert1: trip-point1 {
3640 temperature = <95000>;
3641 hysteresis = <2000>;
3642 type = "passive";
3643 };
3644
3645 cpu0_crit: cpu_crit {
3646 temperature = <110000>;
3647 hysteresis = <1000>;
3648 type = "critical";
3649 };
3650 };
3651 };
3652
3653 cpu1-thermal {
3654 polling-delay-passive = <0>;
3655 polling-delay = <0>;
3656 thermal-sensors = <&tsens1 2>;
3657
3658 trips {
3659 cpu1_alert0: trip-point0 {
3660 temperature = <90000>;
3661 hysteresis = <2000>;
3662 type = "passive";
3663 };
3664
3665 cpu1_alert1: trip-point1 {
3666 temperature = <95000>;
3667 hysteresis = <2000>;
3668 type = "passive";
3669 };
3670
3671 cpu1_crit: cpu_crit {
3672 temperature = <110000>;
3673 hysteresis = <1000>;
3674 type = "critical";
3675 };
3676 };
3677 };
3678
3679 cpu2-thermal {
3680 polling-delay-passive = <0>;
3681 polling-delay = <0>;
3682 thermal-sensors = <&tsens1 3>;
3683
3684 trips {
3685 cpu2_alert0: trip-point0 {
3686 temperature = <90000>;
3687 hysteresis = <2000>;
3688 type = "passive";
3689 };
3690
3691 cpu2_alert1: trip-point1 {
3692 temperature = <95000>;
3693 hysteresis = <2000>;
3694 type = "passive";
3695 };
3696
3697 cpu2_crit: cpu_crit {
3698 temperature = <110000>;
3699 hysteresis = <1000>;
3700 type = "critical";
3701 };
3702 };
3703 };
3704
3705 cpu3-thermal {
3706 polling-delay-passive = <0>;
3707 polling-delay = <0>;
3708 thermal-sensors = <&tsens1 4>;
3709
3710 trips {
3711 cpu3_alert0: trip-point0 {
3712 temperature = <90000>;
3713 hysteresis = <2000>;
3714 type = "passive";
3715 };
3716
3717 cpu3_alert1: trip-point1 {
3718 temperature = <95000>;
3719 hysteresis = <2000>;
3720 type = "passive";
3721 };
3722
3723 cpu3_crit: cpu_crit {
3724 temperature = <110000>;
3725 hysteresis = <1000>;
3726 type = "critical";
3727 };
3728 };
3729 };
3730
3731 cdsp0-thermal {
3732 polling-delay-passive = <10>;
3733 polling-delay = <0>;
3734 thermal-sensors = <&tsens1 5>;
3735
3736 trips {
3737 thermal-engine-config {
3738 temperature = <125000>;
3739 hysteresis = <1000>;
3740 type = "passive";
3741 };
3742
3743 thermal-hal-config {
3744 temperature = <125000>;
3745 hysteresis = <1000>;
3746 type = "passive";
3747 };
3748
3749 reset-mon-cfg {
3750 temperature = <115000>;
3751 hysteresis = <5000>;
3752 type = "passive";
3753 };
3754
3755 cdsp_0_config: junction-config {
3756 temperature = <95000>;
3757 hysteresis = <5000>;
3758 type = "passive";
3759 };
3760 };
3761 };
3762
3763 cdsp1-thermal {
3764 polling-delay-passive = <10>;
3765 polling-delay = <0>;
3766 thermal-sensors = <&tsens1 6>;
3767
3768 trips {
3769 thermal-engine-config {
3770 temperature = <125000>;
3771 hysteresis = <1000>;
3772 type = "passive";
3773 };
3774
3775 thermal-hal-config {
3776 temperature = <125000>;
3777 hysteresis = <1000>;
3778 type = "passive";
3779 };
3780
3781 reset-mon-cfg {
3782 temperature = <115000>;
3783 hysteresis = <5000>;
3784 type = "passive";
3785 };
3786
3787 cdsp_1_config: junction-config {
3788 temperature = <95000>;
3789 hysteresis = <5000>;
3790 type = "passive";
3791 };
3792 };
3793 };
3794
3795 cdsp2-thermal {
3796 polling-delay-passive = <10>;
3797 polling-delay = <0>;
3798 thermal-sensors = <&tsens1 7>;
3799
3800 trips {
3801 thermal-engine-config {
3802 temperature = <125000>;
3803 hysteresis = <1000>;
3804 type = "passive";
3805 };
3806
3807 thermal-hal-config {
3808 temperature = <125000>;
3809 hysteresis = <1000>;
3810 type = "passive";
3811 };
3812
3813 reset-mon-cfg {
3814 temperature = <115000>;
3815 hysteresis = <5000>;
3816 type = "passive";
3817 };
3818
3819 cdsp_2_config: junction-config {
3820 temperature = <95000>;
3821 hysteresis = <5000>;
3822 type = "passive";
3823 };
3824 };
3825 };
3826
3827 video-thermal {
3828 polling-delay-passive = <0>;
3829 polling-delay = <0>;
3830 thermal-sensors = <&tsens1 8>;
3831
3832 trips {
3833 thermal-engine-config {
3834 temperature = <125000>;
3835 hysteresis = <1000>;
3836 type = "passive";
3837 };
3838
3839 reset-mon-cfg {
3840 temperature = <115000>;
3841 hysteresis = <5000>;
3842 type = "passive";
3843 };
3844 };
3845 };
3846
3847 mem-thermal {
3848 polling-delay-passive = <10>;
3849 polling-delay = <0>;
3850 thermal-sensors = <&tsens1 9>;
3851
3852 trips {
3853 thermal-engine-config {
3854 temperature = <125000>;
3855 hysteresis = <1000>;
3856 type = "passive";
3857 };
3858
3859 ddr_config0: ddr0-config {
3860 temperature = <90000>;
3861 hysteresis = <5000>;
3862 type = "passive";
3863 };
3864
3865 reset-mon-cfg {
3866 temperature = <115000>;
3867 hysteresis = <5000>;
3868 type = "passive";
3869 };
3870 };
3871 };
3872
3873 modem0-thermal {
3874 polling-delay-passive = <0>;
3875 polling-delay = <0>;
3876 thermal-sensors = <&tsens1 10>;
3877
3878 trips {
3879 thermal-engine-config {
3880 temperature = <125000>;
3881 hysteresis = <1000>;
3882 type = "passive";
3883 };
3884
3885 mdmss0_config0: mdmss0-config0 {
3886 temperature = <102000>;
3887 hysteresis = <3000>;
3888 type = "passive";
3889 };
3890
3891 mdmss0_config1: mdmss0-config1 {
3892 temperature = <105000>;
3893 hysteresis = <3000>;
3894 type = "passive";
3895 };
3896
3897 reset-mon-cfg {
3898 temperature = <115000>;
3899 hysteresis = <5000>;
3900 type = "passive";
3901 };
3902 };
3903 };
3904
3905 modem1-thermal {
3906 polling-delay-passive = <0>;
3907 polling-delay = <0>;
3908 thermal-sensors = <&tsens1 11>;
3909
3910 trips {
3911 thermal-engine-config {
3912 temperature = <125000>;
3913 hysteresis = <1000>;
3914 type = "passive";
3915 };
3916
3917 mdmss1_config0: mdmss1-config0 {
3918 temperature = <102000>;
3919 hysteresis = <3000>;
3920 type = "passive";
3921 };
3922
3923 mdmss1_config1: mdmss1-config1 {
3924 temperature = <105000>;
3925 hysteresis = <3000>;
3926 type = "passive";
3927 };
3928
3929 reset-mon-cfg {
3930 temperature = <115000>;
3931 hysteresis = <5000>;
3932 type = "passive";
3933 };
3934 };
3935 };
3936
3937 modem2-thermal {
3938 polling-delay-passive = <0>;
3939 polling-delay = <0>;
3940 thermal-sensors = <&tsens1 12>;
3941
3942 trips {
3943 thermal-engine-config {
3944 temperature = <125000>;
3945 hysteresis = <1000>;
3946 type = "passive";
3947 };
3948
3949 mdmss2_config0: mdmss2-config0 {
3950 temperature = <102000>;
3951 hysteresis = <3000>;
3952 type = "passive";
3953 };
3954
3955 mdmss2_config1: mdmss2-config1 {
3956 temperature = <105000>;
3957 hysteresis = <3000>;
3958 type = "passive";
3959 };
3960
3961 reset-mon-cfg {
3962 temperature = <115000>;
3963 hysteresis = <5000>;
3964 type = "passive";
3965 };
3966 };
3967 };
3968
3969 modem3-thermal {
3970 polling-delay-passive = <0>;
3971 polling-delay = <0>;
3972 thermal-sensors = <&tsens1 13>;
3973
3974 trips {
3975 thermal-engine-config {
3976 temperature = <125000>;
3977 hysteresis = <1000>;
3978 type = "passive";
3979 };
3980
3981 mdmss3_config0: mdmss3-config0 {
3982 temperature = <102000>;
3983 hysteresis = <3000>;
3984 type = "passive";
3985 };
3986
3987 mdmss3_config1: mdmss3-config1 {
3988 temperature = <105000>;
3989 hysteresis = <3000>;
3990 type = "passive";
3991 };
3992
3993 reset-mon-cfg {
3994 temperature = <115000>;
3995 hysteresis = <5000>;
3996 type = "passive";
3997 };
3998 };
3999 };
4000
4001 camera0-thermal {
4002 polling-delay-passive = <0>;
4003 polling-delay = <0>;
4004 thermal-sensors = <&tsens1 14>;
4005
4006 trips {
4007 thermal-engine-config {
4008 temperature = <125000>;
4009 hysteresis = <1000>;
4010 type = "passive";
4011 };
4012
4013 reset-mon-cfg {
4014 temperature = <115000>;
4015 hysteresis = <5000>;
4016 type = "passive";
4017 };
4018 };
4019 };
4020
4021 camera1-thermal {
4022 polling-delay-passive = <0>;
4023 polling-delay = <0>;
4024 thermal-sensors = <&tsens1 15>;
4025
4026 trips {
4027 thermal-engine-config {
4028 temperature = <125000>;
4029 hysteresis = <1000>;
4030 type = "passive";
4031 };
4032
4033 reset-mon-cfg {
4034 temperature = <115000>;
4035 hysteresis = <5000>;
4036 type = "passive";
4037 };
4038 };
4039 };
4040 };
4041
4042 timer {
4043 compatible = "arm,armv8-timer";
4044 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4045 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4046 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4047 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4048 clock-frequency = <19200000>;
4049 };
4050 };
