0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
0004 */
0005
0006 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
0007 #include <dt-bindings/clock/qcom,rpmh.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/mailbox/qcom-ipcc.h>
0011 #include <dt-bindings/power/qcom-rpmpd.h>
0012 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0013
0014 / {
0015 interrupt-parent = <&intc>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 clocks {
0020 xo_board: xo-board {
0021 compatible = "fixed-clock";
0022 #clock-cells = <0>;
0023 clock-frequency = <76800000>;
0024 clock-output-names = "xo_board";
0025 };
0026
0027 sleep_clk: sleep-clk {
0028 compatible = "fixed-clock";
0029 clock-frequency = <32764>;
0030 #clock-cells = <0>;
0031 };
0032 };
0033
0034 cpus {
0035 #address-cells = <2>;
0036 #size-cells = <0>;
0037
0038 CPU0: cpu@0 {
0039 device_type = "cpu";
0040 compatible = "qcom,kryo560";
0041 reg = <0x0 0x0>;
0042 enable-method = "psci";
0043 capacity-dmips-mhz = <1024>;
0044 dynamic-power-coefficient = <100>;
0045 next-level-cache = <&L2_0>;
0046 qcom,freq-domain = <&cpufreq_hw 0>;
0047 #cooling-cells = <2>;
0048 L2_0: l2-cache {
0049 compatible = "cache";
0050 next-level-cache = <&L3_0>;
0051 L3_0: l3-cache {
0052 compatible = "cache";
0053 };
0054 };
0055 };
0056
0057 CPU1: cpu@100 {
0058 device_type = "cpu";
0059 compatible = "qcom,kryo560";
0060 reg = <0x0 0x100>;
0061 enable-method = "psci";
0062 capacity-dmips-mhz = <1024>;
0063 dynamic-power-coefficient = <100>;
0064 next-level-cache = <&L2_100>;
0065 qcom,freq-domain = <&cpufreq_hw 0>;
0066 #cooling-cells = <2>;
0067 L2_100: l2-cache {
0068 compatible = "cache";
0069 next-level-cache = <&L3_0>;
0070 };
0071 };
0072
0073 CPU2: cpu@200 {
0074 device_type = "cpu";
0075 compatible = "qcom,kryo560";
0076 reg = <0x0 0x200>;
0077 enable-method = "psci";
0078 capacity-dmips-mhz = <1024>;
0079 dynamic-power-coefficient = <100>;
0080 next-level-cache = <&L2_200>;
0081 qcom,freq-domain = <&cpufreq_hw 0>;
0082 #cooling-cells = <2>;
0083 L2_200: l2-cache {
0084 compatible = "cache";
0085 next-level-cache = <&L3_0>;
0086 };
0087 };
0088
0089 CPU3: cpu@300 {
0090 device_type = "cpu";
0091 compatible = "qcom,kryo560";
0092 reg = <0x0 0x300>;
0093 enable-method = "psci";
0094 capacity-dmips-mhz = <1024>;
0095 dynamic-power-coefficient = <100>;
0096 next-level-cache = <&L2_300>;
0097 qcom,freq-domain = <&cpufreq_hw 0>;
0098 #cooling-cells = <2>;
0099 L2_300: l2-cache {
0100 compatible = "cache";
0101 next-level-cache = <&L3_0>;
0102 };
0103 };
0104
0105 CPU4: cpu@400 {
0106 device_type = "cpu";
0107 compatible = "qcom,kryo560";
0108 reg = <0x0 0x400>;
0109 enable-method = "psci";
0110 capacity-dmips-mhz = <1024>;
0111 dynamic-power-coefficient = <100>;
0112 next-level-cache = <&L2_400>;
0113 qcom,freq-domain = <&cpufreq_hw 0>;
0114 #cooling-cells = <2>;
0115 L2_400: l2-cache {
0116 compatible = "cache";
0117 next-level-cache = <&L3_0>;
0118 };
0119 };
0120
0121 CPU5: cpu@500 {
0122 device_type = "cpu";
0123 compatible = "qcom,kryo560";
0124 reg = <0x0 0x500>;
0125 enable-method = "psci";
0126 capacity-dmips-mhz = <1024>;
0127 dynamic-power-coefficient = <100>;
0128 next-level-cache = <&L2_500>;
0129 qcom,freq-domain = <&cpufreq_hw 0>;
0130 #cooling-cells = <2>;
0131 L2_500: l2-cache {
0132 compatible = "cache";
0133 next-level-cache = <&L3_0>;
0134 };
0135
0136 };
0137
0138 CPU6: cpu@600 {
0139 device_type = "cpu";
0140 compatible = "qcom,kryo560";
0141 reg = <0x0 0x600>;
0142 enable-method = "psci";
0143 capacity-dmips-mhz = <1894>;
0144 dynamic-power-coefficient = <703>;
0145 next-level-cache = <&L2_600>;
0146 qcom,freq-domain = <&cpufreq_hw 1>;
0147 #cooling-cells = <2>;
0148 L2_600: l2-cache {
0149 compatible = "cache";
0150 next-level-cache = <&L3_0>;
0151 };
0152 };
0153
0154 CPU7: cpu@700 {
0155 device_type = "cpu";
0156 compatible = "qcom,kryo560";
0157 reg = <0x0 0x700>;
0158 enable-method = "psci";
0159 capacity-dmips-mhz = <1894>;
0160 dynamic-power-coefficient = <703>;
0161 next-level-cache = <&L2_700>;
0162 qcom,freq-domain = <&cpufreq_hw 1>;
0163 #cooling-cells = <2>;
0164 L2_700: l2-cache {
0165 compatible = "cache";
0166 next-level-cache = <&L3_0>;
0167 };
0168 };
0169
0170 cpu-map {
0171 cluster0 {
0172 core0 {
0173 cpu = <&CPU0>;
0174 };
0175
0176 core1 {
0177 cpu = <&CPU1>;
0178 };
0179
0180 core2 {
0181 cpu = <&CPU2>;
0182 };
0183
0184 core3 {
0185 cpu = <&CPU3>;
0186 };
0187
0188 core4 {
0189 cpu = <&CPU4>;
0190 };
0191
0192 core5 {
0193 cpu = <&CPU5>;
0194 };
0195
0196 core6 {
0197 cpu = <&CPU6>;
0198 };
0199
0200 core7 {
0201 cpu = <&CPU7>;
0202 };
0203 };
0204 };
0205 };
0206
0207 firmware {
0208 scm: scm {
0209 compatible = "qcom,scm-sm6350", "qcom,scm";
0210 #reset-cells = <1>;
0211 };
0212 };
0213
0214 memory@80000000 {
0215 device_type = "memory";
0216 /* We expect the bootloader to fill in the size */
0217 reg = <0x0 0x80000000 0x0 0x0>;
0218 };
0219
0220 pmu {
0221 compatible = "arm,armv8-pmuv3";
0222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
0223 };
0224
0225 psci {
0226 compatible = "arm,psci-1.0";
0227 method = "smc";
0228 };
0229
0230 reserved_memory: reserved-memory {
0231 #address-cells = <2>;
0232 #size-cells = <2>;
0233 ranges;
0234
0235 hyp_mem: memory@80000000 {
0236 reg = <0 0x80000000 0 0x600000>;
0237 no-map;
0238 };
0239
0240 xbl_aop_mem: memory@80700000 {
0241 reg = <0 0x80700000 0 0x160000>;
0242 no-map;
0243 };
0244
0245 cmd_db: memory@80860000 {
0246 compatible = "qcom,cmd-db";
0247 reg = <0 0x80860000 0 0x20000>;
0248 no-map;
0249 };
0250
0251 sec_apps_mem: memory@808ff000 {
0252 reg = <0 0x808ff000 0 0x1000>;
0253 no-map;
0254 };
0255
0256 smem_mem: memory@80900000 {
0257 reg = <0 0x80900000 0 0x200000>;
0258 no-map;
0259 };
0260
0261 cdsp_sec_mem: memory@80b00000 {
0262 reg = <0 0x80b00000 0 0x1e00000>;
0263 no-map;
0264 };
0265
0266 pil_camera_mem: memory@86000000 {
0267 reg = <0 0x86000000 0 0x500000>;
0268 no-map;
0269 };
0270
0271 pil_npu_mem: memory@86500000 {
0272 reg = <0 0x86500000 0 0x500000>;
0273 no-map;
0274 };
0275
0276 pil_video_mem: memory@86a00000 {
0277 reg = <0 0x86a00000 0 0x500000>;
0278 no-map;
0279 };
0280
0281 pil_cdsp_mem: memory@86f00000 {
0282 reg = <0 0x86f00000 0 0x1e00000>;
0283 no-map;
0284 };
0285
0286 pil_adsp_mem: memory@88d00000 {
0287 reg = <0 0x88d00000 0 0x2800000>;
0288 no-map;
0289 };
0290
0291 wlan_fw_mem: memory@8b500000 {
0292 reg = <0 0x8b500000 0 0x200000>;
0293 no-map;
0294 };
0295
0296 pil_ipa_fw_mem: memory@8b700000 {
0297 reg = <0 0x8b700000 0 0x10000>;
0298 no-map;
0299 };
0300
0301 pil_ipa_gsi_mem: memory@8b710000 {
0302 reg = <0 0x8b710000 0 0x5400>;
0303 no-map;
0304 };
0305
0306 pil_gpu_mem: memory@8b715400 {
0307 reg = <0 0x8b715400 0 0x2000>;
0308 no-map;
0309 };
0310
0311 pil_modem_mem: memory@8b800000 {
0312 reg = <0 0x8b800000 0 0xf800000>;
0313 no-map;
0314 };
0315
0316 cont_splash_memory: memory@a0000000 {
0317 reg = <0 0xa0000000 0 0x2300000>;
0318 no-map;
0319 };
0320
0321 dfps_data_memory: memory@a2300000 {
0322 reg = <0 0xa2300000 0 0x100000>;
0323 no-map;
0324 };
0325
0326 removed_region: memory@c0000000 {
0327 reg = <0 0xc0000000 0 0x3900000>;
0328 no-map;
0329 };
0330
0331 debug_region: memory@ffb00000 {
0332 reg = <0 0xffb00000 0 0xc0000>;
0333 no-map;
0334 };
0335
0336 last_log_region: memory@ffbc0000 {
0337 reg = <0 0xffbc0000 0 0x40000>;
0338 no-map;
0339 };
0340
0341 ramoops: ramoops@ffc00000 {
0342 compatible = "removed-dma-pool", "ramoops";
0343 reg = <0 0xffc00000 0 0x00100000>;
0344 record-size = <0x1000>;
0345 console-size = <0x40000>;
0346 ftrace-size = <0x0>;
0347 msg-size = <0x20000 0x20000>;
0348 cc-size = <0x0>;
0349 no-map;
0350 };
0351
0352 cmdline_region: memory@ffd00000 {
0353 reg = <0 0xffd00000 0 0x1000>;
0354 no-map;
0355 };
0356 };
0357
0358 smem {
0359 compatible = "qcom,smem";
0360 memory-region = <&smem_mem>;
0361 hwlocks = <&tcsr_mutex 3>;
0362 };
0363
0364 smp2p-adsp {
0365 compatible = "qcom,smp2p";
0366 qcom,smem = <443>, <429>;
0367 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
0368 IPCC_MPROC_SIGNAL_SMP2P
0369 IRQ_TYPE_EDGE_RISING>;
0370 mboxes = <&ipcc IPCC_CLIENT_LPASS
0371 IPCC_MPROC_SIGNAL_SMP2P>;
0372
0373 qcom,local-pid = <0>;
0374 qcom,remote-pid = <2>;
0375
0376 smp2p_adsp_out: master-kernel {
0377 qcom,entry-name = "master-kernel";
0378 #qcom,smem-state-cells = <1>;
0379 };
0380
0381 smp2p_adsp_in: slave-kernel {
0382 qcom,entry-name = "slave-kernel";
0383 interrupt-controller;
0384 #interrupt-cells = <2>;
0385 };
0386 };
0387
0388 smp2p-cdsp {
0389 compatible = "qcom,smp2p";
0390 qcom,smem = <94>, <432>;
0391 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
0392 IPCC_MPROC_SIGNAL_SMP2P
0393 IRQ_TYPE_EDGE_RISING>;
0394 mboxes = <&ipcc IPCC_CLIENT_CDSP
0395 IPCC_MPROC_SIGNAL_SMP2P>;
0396
0397 qcom,local-pid = <0>;
0398 qcom,remote-pid = <5>;
0399
0400 smp2p_cdsp_out: master-kernel {
0401 qcom,entry-name = "master-kernel";
0402 #qcom,smem-state-cells = <1>;
0403 };
0404
0405 smp2p_cdsp_in: slave-kernel {
0406 qcom,entry-name = "slave-kernel";
0407 interrupt-controller;
0408 #interrupt-cells = <2>;
0409 };
0410 };
0411
0412 smp2p-mpss {
0413 compatible = "qcom,smp2p";
0414 qcom,smem = <435>, <428>;
0415
0416 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
0417 IPCC_MPROC_SIGNAL_SMP2P
0418 IRQ_TYPE_EDGE_RISING>;
0419 mboxes = <&ipcc IPCC_CLIENT_MPSS
0420 IPCC_MPROC_SIGNAL_SMP2P>;
0421
0422 qcom,local-pid = <0>;
0423 qcom,remote-pid = <1>;
0424
0425 modem_smp2p_out: master-kernel {
0426 qcom,entry-name = "master-kernel";
0427 #qcom,smem-state-cells = <1>;
0428 };
0429
0430 modem_smp2p_in: slave-kernel {
0431 qcom,entry-name = "slave-kernel";
0432
0433 interrupt-controller;
0434 #interrupt-cells = <2>;
0435 };
0436 };
0437
0438 soc: soc@0 {
0439 #address-cells = <2>;
0440 #size-cells = <2>;
0441 ranges = <0 0 0 0 0x10 0>;
0442 dma-ranges = <0 0 0 0 0x10 0>;
0443 compatible = "simple-bus";
0444
0445 gcc: clock-controller@100000 {
0446 compatible = "qcom,gcc-sm6350";
0447 reg = <0 0x00100000 0 0x1f0000>;
0448 #clock-cells = <1>;
0449 #reset-cells = <1>;
0450 #power-domain-cells = <1>;
0451 clock-names = "bi_tcxo",
0452 "bi_tcxo_ao",
0453 "sleep_clk";
0454 clocks = <&rpmhcc RPMH_CXO_CLK>,
0455 <&rpmhcc RPMH_CXO_CLK_A>,
0456 <&sleep_clk>;
0457 };
0458
0459 ipcc: mailbox@408000 {
0460 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
0461 reg = <0 0x00408000 0 0x1000>;
0462 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
0463 interrupt-controller;
0464 #interrupt-cells = <3>;
0465 #mbox-cells = <2>;
0466 };
0467
0468 rng: rng@793000 {
0469 compatible = "qcom,prng-ee";
0470 reg = <0 0x00793000 0 0x1000>;
0471 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0472 clock-names = "core";
0473 };
0474
0475 sdhc_1: mmc@7c4000 {
0476 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
0477 reg = <0 0x007c4000 0 0x1000>,
0478 <0 0x007c5000 0 0x1000>,
0479 <0 0x007c8000 0 0x8000>;
0480 reg-names = "hc", "cqhci", "ice";
0481
0482 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
0483 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
0484 interrupt-names = "hc_irq", "pwr_irq";
0485
0486 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0487 <&gcc GCC_SDCC1_APPS_CLK>,
0488 <&rpmhcc RPMH_CXO_CLK>;
0489 clock-names = "iface", "core", "xo";
0490 qcom,dll-config = <0x000f642c>;
0491 qcom,ddr-config = <0x80040868>;
0492 power-domains = <&rpmhpd SM6350_CX>;
0493 operating-points-v2 = <&sdhc1_opp_table>;
0494 bus-width = <8>;
0495 non-removable;
0496 supports-cqe;
0497
0498 status = "disabled";
0499
0500 sdhc1_opp_table: opp-table {
0501 compatible = "operating-points-v2";
0502
0503 opp-19200000 {
0504 opp-hz = /bits/ 64 <19200000>;
0505 required-opps = <&rpmhpd_opp_min_svs>;
0506 };
0507
0508 opp-100000000 {
0509 opp-hz = /bits/ 64 <100000000>;
0510 required-opps = <&rpmhpd_opp_low_svs>;
0511 };
0512
0513 opp-384000000 {
0514 opp-hz = /bits/ 64 <384000000>;
0515 required-opps = <&rpmhpd_opp_svs_l1>;
0516 };
0517 };
0518 };
0519
0520 qupv3_id_0: geniqup@8c0000 {
0521 compatible = "qcom,geni-se-qup";
0522 reg = <0x0 0x8c0000 0x0 0x2000>;
0523 clock-names = "m-ahb", "s-ahb";
0524 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
0525 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
0526 #address-cells = <2>;
0527 #size-cells = <2>;
0528 iommus = <&apps_smmu 0x43 0x0>;
0529 ranges;
0530 status = "disabled";
0531
0532 i2c0: i2c@880000 {
0533 compatible = "qcom,geni-i2c";
0534 reg = <0 0x00880000 0 0x4000>;
0535 clock-names = "se";
0536 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
0537 pinctrl-names = "default";
0538 pinctrl-0 = <&qup_i2c0_default>;
0539 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
0540 #address-cells = <1>;
0541 #size-cells = <0>;
0542 status = "disabled";
0543 };
0544
0545 i2c2: i2c@888000 {
0546 compatible = "qcom,geni-i2c";
0547 reg = <0 0x00888000 0 0x4000>;
0548 clock-names = "se";
0549 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
0550 pinctrl-names = "default";
0551 pinctrl-0 = <&qup_i2c2_default>;
0552 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
0553 #address-cells = <1>;
0554 #size-cells = <0>;
0555 status = "disabled";
0556 };
0557 };
0558
0559 qupv3_id_1: geniqup@9c0000 {
0560 compatible = "qcom,geni-se-qup";
0561 reg = <0x0 0x9c0000 0x0 0x2000>;
0562 clock-names = "m-ahb", "s-ahb";
0563 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
0564 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
0565 #address-cells = <2>;
0566 #size-cells = <2>;
0567 iommus = <&apps_smmu 0x4c3 0x0>;
0568 ranges;
0569 status = "disabled";
0570
0571 i2c6: i2c@980000 {
0572 compatible = "qcom,geni-i2c";
0573 reg = <0 0x00980000 0 0x4000>;
0574 clock-names = "se";
0575 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
0576 pinctrl-names = "default";
0577 pinctrl-0 = <&qup_i2c6_default>;
0578 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
0579 #address-cells = <1>;
0580 #size-cells = <0>;
0581 status = "disabled";
0582 };
0583
0584 i2c7: i2c@984000 {
0585 compatible = "qcom,geni-i2c";
0586 reg = <0 0x00984000 0 0x4000>;
0587 clock-names = "se";
0588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
0589 pinctrl-names = "default";
0590 pinctrl-0 = <&qup_i2c7_default>;
0591 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
0592 #address-cells = <1>;
0593 #size-cells = <0>;
0594 status = "disabled";
0595 };
0596
0597 i2c8: i2c@988000 {
0598 compatible = "qcom,geni-i2c";
0599 reg = <0 0x00988000 0 0x4000>;
0600 clock-names = "se";
0601 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
0602 pinctrl-names = "default";
0603 pinctrl-0 = <&qup_i2c8_default>;
0604 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
0605 #address-cells = <1>;
0606 #size-cells = <0>;
0607 status = "disabled";
0608 };
0609
0610 uart9: serial@98c000 {
0611 compatible = "qcom,geni-debug-uart";
0612 reg = <0 0x98c000 0 0x4000>;
0613 clock-names = "se";
0614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
0615 pinctrl-names = "default";
0616 pinctrl-0 = <&qup_uart9_default>;
0617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
0618 status = "disabled";
0619 };
0620
0621 i2c10: i2c@990000 {
0622 compatible = "qcom,geni-i2c";
0623 reg = <0 0x00990000 0 0x4000>;
0624 clock-names = "se";
0625 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
0626 pinctrl-names = "default";
0627 pinctrl-0 = <&qup_i2c10_default>;
0628 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
0629 #address-cells = <1>;
0630 #size-cells = <0>;
0631 status = "disabled";
0632 };
0633
0634 };
0635
0636 ufs_mem_hc: ufs@1d84000 {
0637 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
0638 "jedec,ufs-2.0";
0639 reg = <0 0x01d84000 0 0x3000>,
0640 <0 0x01d90000 0 0x8000>;
0641 reg-names = "std", "ice";
0642 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
0643 phys = <&ufs_mem_phy_lanes>;
0644 phy-names = "ufsphy";
0645 lanes-per-direction = <2>;
0646 #reset-cells = <1>;
0647 resets = <&gcc GCC_UFS_PHY_BCR>;
0648 reset-names = "rst";
0649
0650 power-domains = <&gcc UFS_PHY_GDSC>;
0651
0652 iommus = <&apps_smmu 0x80 0x0>;
0653
0654 clock-names = "core_clk",
0655 "bus_aggr_clk",
0656 "iface_clk",
0657 "core_clk_unipro",
0658 "ref_clk",
0659 "tx_lane0_sync_clk",
0660 "rx_lane0_sync_clk",
0661 "rx_lane1_sync_clk",
0662 "ice_core_clk";
0663 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
0664 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
0665 <&gcc GCC_UFS_PHY_AHB_CLK>,
0666 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
0667 <&rpmhcc RPMH_QLINK_CLK>,
0668 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
0669 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
0670 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
0671 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
0672 freq-table-hz =
0673 <50000000 200000000>,
0674 <0 0>,
0675 <0 0>,
0676 <37500000 150000000>,
0677 <75000000 300000000>,
0678 <0 0>,
0679 <0 0>,
0680 <0 0>,
0681 <0 0>;
0682
0683 status = "disabled";
0684 };
0685
0686 ufs_mem_phy: phy@1d87000 {
0687 compatible = "qcom,sm6350-qmp-ufs-phy";
0688 reg = <0 0x01d87000 0 0x18c>;
0689 #address-cells = <2>;
0690 #size-cells = <2>;
0691 ranges;
0692
0693 clock-names = "ref",
0694 "ref_aux";
0695 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
0696 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
0697
0698 resets = <&ufs_mem_hc 0>;
0699 reset-names = "ufsphy";
0700
0701 status = "disabled";
0702
0703 ufs_mem_phy_lanes: phy@1d87400 {
0704 reg = <0 0x01d87400 0 0x128>,
0705 <0 0x01d87600 0 0x1fc>,
0706 <0 0x01d87c00 0 0x1dc>,
0707 <0 0x01d87800 0 0x128>,
0708 <0 0x01d87a00 0 0x1fc>;
0709 #phy-cells = <0>;
0710 };
0711 };
0712
0713 tcsr_mutex: hwlock@1f40000 {
0714 compatible = "qcom,tcsr-mutex";
0715 reg = <0x0 0x01f40000 0x0 0x40000>;
0716 #hwlock-cells = <1>;
0717 };
0718
0719 adsp: remoteproc@3000000 {
0720 compatible = "qcom,sm6350-adsp-pas";
0721 reg = <0 0x03000000 0 0x100>;
0722
0723 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
0724 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
0725 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
0726 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
0727 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
0728 interrupt-names = "wdog", "fatal", "ready",
0729 "handover", "stop-ack";
0730
0731 clocks = <&rpmhcc RPMH_CXO_CLK>;
0732 clock-names = "xo";
0733
0734 power-domains = <&rpmhpd SM6350_LCX>,
0735 <&rpmhpd SM6350_LMX>;
0736 power-domain-names = "lcx", "lmx";
0737
0738 memory-region = <&pil_adsp_mem>;
0739
0740 qcom,qmp = <&aoss_qmp>;
0741
0742 qcom,smem-states = <&smp2p_adsp_out 0>;
0743 qcom,smem-state-names = "stop";
0744
0745 status = "disabled";
0746
0747 glink-edge {
0748 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
0749 IPCC_MPROC_SIGNAL_GLINK_QMP
0750 IRQ_TYPE_EDGE_RISING>;
0751 mboxes = <&ipcc IPCC_CLIENT_LPASS
0752 IPCC_MPROC_SIGNAL_GLINK_QMP>;
0753
0754 label = "lpass";
0755 qcom,remote-pid = <2>;
0756
0757 fastrpc {
0758 compatible = "qcom,fastrpc";
0759 qcom,glink-channels = "fastrpcglink-apps-dsp";
0760 label = "adsp";
0761 #address-cells = <1>;
0762 #size-cells = <0>;
0763
0764 compute-cb@3 {
0765 compatible = "qcom,fastrpc-compute-cb";
0766 reg = <3>;
0767 iommus = <&apps_smmu 0x1003 0x0>;
0768 };
0769
0770 compute-cb@4 {
0771 compatible = "qcom,fastrpc-compute-cb";
0772 reg = <4>;
0773 iommus = <&apps_smmu 0x1004 0x0>;
0774 };
0775
0776 compute-cb@5 {
0777 compatible = "qcom,fastrpc-compute-cb";
0778 reg = <5>;
0779 iommus = <&apps_smmu 0x1005 0x0>;
0780 qcom,nsessions = <5>;
0781 };
0782 };
0783 };
0784 };
0785
0786 mpss: remoteproc@4080000 {
0787 compatible = "qcom,sm6350-mpss-pas";
0788 reg = <0x0 0x04080000 0x0 0x4040>;
0789
0790 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
0791 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0792 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0793 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0794 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
0795 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
0796 interrupt-names = "wdog", "fatal", "ready", "handover",
0797 "stop-ack", "shutdown-ack";
0798
0799 clocks = <&rpmhcc RPMH_CXO_CLK>;
0800 clock-names = "xo";
0801
0802 power-domains = <&rpmhpd SM6350_CX>,
0803 <&rpmhpd SM6350_MSS>;
0804 power-domain-names = "cx", "mss";
0805
0806 memory-region = <&pil_modem_mem>;
0807
0808 qcom,qmp = <&aoss_qmp>;
0809
0810 qcom,smem-states = <&modem_smp2p_out 0>;
0811 qcom,smem-state-names = "stop";
0812
0813 status = "disabled";
0814
0815 glink-edge {
0816 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
0817 IPCC_MPROC_SIGNAL_GLINK_QMP
0818 IRQ_TYPE_EDGE_RISING>;
0819 mboxes = <&ipcc IPCC_CLIENT_MPSS
0820 IPCC_MPROC_SIGNAL_GLINK_QMP>;
0821 label = "modem";
0822 qcom,remote-pid = <1>;
0823 };
0824 };
0825
0826 cdsp: remoteproc@8300000 {
0827 compatible = "qcom,sm6350-cdsp-pas";
0828 reg = <0 0x08300000 0 0x10000>;
0829
0830 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
0831 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
0832 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
0833 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
0834 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
0835 interrupt-names = "wdog", "fatal", "ready",
0836 "handover", "stop-ack";
0837
0838 clocks = <&rpmhcc RPMH_CXO_CLK>;
0839 clock-names = "xo";
0840
0841 power-domains = <&rpmhpd SM6350_CX>,
0842 <&rpmhpd SM6350_MX>;
0843 power-domain-names = "cx", "mx";
0844
0845 memory-region = <&pil_cdsp_mem>;
0846
0847 qcom,qmp = <&aoss_qmp>;
0848
0849 qcom,smem-states = <&smp2p_cdsp_out 0>;
0850 qcom,smem-state-names = "stop";
0851
0852 status = "disabled";
0853
0854 glink-edge {
0855 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
0856 IPCC_MPROC_SIGNAL_GLINK_QMP
0857 IRQ_TYPE_EDGE_RISING>;
0858 mboxes = <&ipcc IPCC_CLIENT_CDSP
0859 IPCC_MPROC_SIGNAL_GLINK_QMP>;
0860
0861 label = "cdsp";
0862 qcom,remote-pid = <5>;
0863
0864 fastrpc {
0865 compatible = "qcom,fastrpc";
0866 qcom,glink-channels = "fastrpcglink-apps-dsp";
0867 label = "cdsp";
0868 #address-cells = <1>;
0869 #size-cells = <0>;
0870
0871 compute-cb@1 {
0872 compatible = "qcom,fastrpc-compute-cb";
0873 reg = <1>;
0874 iommus = <&apps_smmu 0x1401 0x20>;
0875 };
0876
0877 compute-cb@2 {
0878 compatible = "qcom,fastrpc-compute-cb";
0879 reg = <2>;
0880 iommus = <&apps_smmu 0x1402 0x20>;
0881 };
0882
0883 compute-cb@3 {
0884 compatible = "qcom,fastrpc-compute-cb";
0885 reg = <3>;
0886 iommus = <&apps_smmu 0x1403 0x20>;
0887 };
0888
0889 compute-cb@4 {
0890 compatible = "qcom,fastrpc-compute-cb";
0891 reg = <4>;
0892 iommus = <&apps_smmu 0x1404 0x20>;
0893 };
0894
0895 compute-cb@5 {
0896 compatible = "qcom,fastrpc-compute-cb";
0897 reg = <5>;
0898 iommus = <&apps_smmu 0x1405 0x20>;
0899 };
0900
0901 compute-cb@6 {
0902 compatible = "qcom,fastrpc-compute-cb";
0903 reg = <6>;
0904 iommus = <&apps_smmu 0x1406 0x20>;
0905 };
0906
0907 compute-cb@7 {
0908 compatible = "qcom,fastrpc-compute-cb";
0909 reg = <7>;
0910 iommus = <&apps_smmu 0x1407 0x20>;
0911 };
0912
0913 compute-cb@8 {
0914 compatible = "qcom,fastrpc-compute-cb";
0915 reg = <8>;
0916 iommus = <&apps_smmu 0x1408 0x20>;
0917 };
0918
0919 /* note: secure cb9 in downstream */
0920 };
0921 };
0922 };
0923
0924 sdhc_2: mmc@8804000 {
0925 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
0926 reg = <0 0x08804000 0 0x1000>;
0927
0928 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0929 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
0930 interrupt-names = "hc_irq", "pwr_irq";
0931
0932 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
0933 <&gcc GCC_SDCC2_APPS_CLK>,
0934 <&rpmhcc RPMH_CXO_CLK>;
0935 clock-names = "iface", "core", "xo";
0936 qcom,dll-config = <0x0007642c>;
0937 qcom,ddr-config = <0x80040868>;
0938 power-domains = <&rpmhpd SM6350_CX>;
0939 operating-points-v2 = <&sdhc2_opp_table>;
0940 bus-width = <4>;
0941
0942 status = "disabled";
0943
0944 sdhc2_opp_table: opp-table {
0945 compatible = "operating-points-v2";
0946
0947 opp-100000000 {
0948 opp-hz = /bits/ 64 <100000000>;
0949 required-opps = <&rpmhpd_opp_svs_l1>;
0950 };
0951
0952 opp-202000000 {
0953 opp-hz = /bits/ 64 <202000000>;
0954 required-opps = <&rpmhpd_opp_nom>;
0955 };
0956 };
0957 };
0958
0959 usb_1_hsphy: phy@88e3000 {
0960 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
0961 reg = <0 0x088e3000 0 0x400>;
0962 status = "disabled";
0963 #phy-cells = <0>;
0964
0965 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
0966 clock-names = "cfg_ahb", "ref";
0967
0968 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
0969 };
0970
0971 usb_1_qmpphy: phy@88e9000 {
0972 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
0973 reg = <0 0x088e9000 0 0x200>,
0974 <0 0x088e8000 0 0x40>,
0975 <0 0x088ea000 0 0x200>;
0976 status = "disabled";
0977 #address-cells = <2>;
0978 #size-cells = <2>;
0979 ranges;
0980
0981 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
0982 <&xo_board>,
0983 <&rpmhcc RPMH_QLINK_CLK>,
0984 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
0985 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
0986
0987 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
0988 <&gcc GCC_USB3_PHY_PRIM_BCR>;
0989 reset-names = "phy", "common";
0990
0991 usb_1_ssphy: usb3-phy@88e9200 {
0992 reg = <0 0x088e9200 0 0x200>,
0993 <0 0x088e9400 0 0x200>,
0994 <0 0x088e9c00 0 0x400>,
0995 <0 0x088e9600 0 0x200>,
0996 <0 0x088e9800 0 0x200>,
0997 <0 0x088e9a00 0 0x100>;
0998 #clock-cells = <0>;
0999 #phy-cells = <0>;
1000 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1001 clock-names = "pipe0";
1002 clock-output-names = "usb3_phy_pipe_clk_src";
1003 };
1004
1005 dp_phy: dp-phy@88ea200 {
1006 reg = <0 0x088ea200 0 0x200>,
1007 <0 0x088ea400 0 0x200>,
1008 <0 0x088eac00 0 0x400>,
1009 <0 0x088ea600 0 0x200>,
1010 <0 0x088ea800 0 0x200>,
1011 <0 0x088eaa00 0 0x100>;
1012 #phy-cells = <0>;
1013 #clock-cells = <1>;
1014 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1015 clock-names = "pipe0";
1016 clock-output-names = "usb3_phy_pipe_clk_src";
1017 };
1018 };
1019
1020 system-cache-controller@9200000 {
1021 compatible = "qcom,sm6350-llcc";
1022 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1023 reg-names = "llcc_base", "llcc_broadcast_base";
1024 };
1025
1026 usb_1: usb@a6f8800 {
1027 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1028 reg = <0 0x0a6f8800 0 0x400>;
1029 status = "disabled";
1030 #address-cells = <2>;
1031 #size-cells = <2>;
1032 ranges;
1033
1034 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1035 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1036 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1037 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1038 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1039 clock-names = "cfg_noc",
1040 "core",
1041 "iface",
1042 "sleep",
1043 "mock_utmi";
1044
1045 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1046 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1047 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1048 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
1049
1050 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1051 "dm_hs_phy_irq", "dp_hs_phy_irq";
1052
1053 power-domains = <&gcc USB30_PRIM_GDSC>;
1054
1055 resets = <&gcc GCC_USB30_PRIM_BCR>;
1056
1057 usb_1_dwc3: usb@a600000 {
1058 compatible = "snps,dwc3";
1059 reg = <0 0x0a600000 0 0xcd00>;
1060 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1061 iommus = <&apps_smmu 0x540 0x0>;
1062 snps,dis_u2_susphy_quirk;
1063 snps,dis_enblslpm_quirk;
1064 snps,has-lpm-erratum;
1065 snps,hird-threshold = /bits/ 8 <0x10>;
1066 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1067 phy-names = "usb2-phy", "usb3-phy";
1068 };
1069 };
1070
1071 pdc: interrupt-controller@b220000 {
1072 compatible = "qcom,sm6350-pdc", "qcom,pdc";
1073 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
1074 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1075 <125 63 1>, <126 655 12>, <138 139 15>;
1076 #interrupt-cells = <2>;
1077 interrupt-parent = <&intc>;
1078 interrupt-controller;
1079 };
1080
1081 tsens0: thermal-sensor@c263000 {
1082 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
1083 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1084 <0 0x0c222000 0 0x8>; /* SROT */
1085 #qcom,sensors = <16>;
1086 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1087 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1088 interrupt-names = "uplow", "critical";
1089 #thermal-sensor-cells = <1>;
1090 };
1091
1092 tsens1: thermal-sensor@c265000 {
1093 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
1094 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1095 <0 0x0c223000 0 0x8>; /* SROT */
1096 #qcom,sensors = <16>;
1097 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1098 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1099 interrupt-names = "uplow", "critical";
1100 #thermal-sensor-cells = <1>;
1101 };
1102
1103 aoss_qmp: power-controller@c300000 {
1104 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
1105 reg = <0 0x0c300000 0 0x1000>;
1106 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1107 IRQ_TYPE_EDGE_RISING>;
1108 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1109
1110 #clock-cells = <0>;
1111 };
1112
1113 spmi_bus: spmi@c440000 {
1114 compatible = "qcom,spmi-pmic-arb";
1115 reg = <0 0xc440000 0 0x1100>,
1116 <0 0xc600000 0 0x2000000>,
1117 <0 0xe600000 0 0x100000>,
1118 <0 0xe700000 0 0xa0000>,
1119 <0 0xc40a000 0 0x26000>;
1120 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1121 interrupt-names = "periph_irq";
1122 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1123 qcom,ee = <0>;
1124 qcom,channel = <0>;
1125 #address-cells = <2>;
1126 #size-cells = <0>;
1127 interrupt-controller;
1128 #interrupt-cells = <4>;
1129 };
1130
1131 tlmm: pinctrl@f100000 {
1132 compatible = "qcom,sm6350-tlmm";
1133 reg = <0 0x0f100000 0 0x300000>;
1134 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1143 gpio-controller;
1144 #gpio-cells = <2>;
1145 interrupt-controller;
1146 #interrupt-cells = <2>;
1147 gpio-ranges = <&tlmm 0 0 157>;
1148
1149 qup_uart9_default: qup-uart9-default {
1150 pins = "gpio25", "gpio26";
1151 function = "qup13_f2";
1152 drive-strength = <2>;
1153 bias-disable;
1154 };
1155
1156 qup_i2c0_default: qup-i2c0-default {
1157 pins = "gpio0", "gpio1";
1158 function = "qup00";
1159 drive-strength = <2>;
1160 bias-pull-up;
1161 };
1162
1163 qup_i2c2_default: qup-i2c2-default {
1164 pins = "gpio45", "gpio46";
1165 function = "qup02";
1166 drive-strength = <2>;
1167 bias-pull-up;
1168 };
1169
1170 qup_i2c6_default: qup-i2c6-default {
1171 pins = "gpio13", "gpio14";
1172 function = "qup10";
1173 drive-strength = <2>;
1174 bias-pull-up;
1175 };
1176
1177 qup_i2c7_default: qup-i2c7-default {
1178 pins = "gpio27", "gpio28";
1179 function = "qup11";
1180 drive-strength = <2>;
1181 bias-pull-up;
1182 };
1183
1184 qup_i2c8_default: qup-i2c8-default {
1185 pins = "gpio19", "gpio20";
1186 function = "qup12";
1187 drive-strength = <2>;
1188 bias-pull-up;
1189 };
1190
1191 qup_i2c10_default: qup-i2c10-default {
1192 pins = "gpio4", "gpio5";
1193 function = "qup14";
1194 drive-strength = <2>;
1195 bias-pull-up;
1196 };
1197 };
1198
1199 apps_smmu: iommu@15000000 {
1200 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
1201 reg = <0 0x15000000 0 0x100000>;
1202 #iommu-cells = <2>;
1203 #global-interrupts = <1>;
1204 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1285 };
1286
1287 intc: interrupt-controller@17a00000 {
1288 compatible = "arm,gic-v3";
1289 #interrupt-cells = <3>;
1290 interrupt-controller;
1291 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1292 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1293 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
1294 };
1295
1296 watchdog@17c10000 {
1297 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
1298 reg = <0 0x17c10000 0 0x1000>;
1299 clocks = <&sleep_clk>;
1300 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1301 };
1302
1303 timer@17c20000 {
1304 compatible = "arm,armv7-timer-mem";
1305 reg = <0x0 0x17c20000 0x0 0x1000>;
1306 clock-frequency = <19200000>;
1307 #address-cells = <1>;
1308 #size-cells = <1>;
1309 ranges = <0 0 0 0x20000000>;
1310
1311 frame@17c21000 {
1312 frame-number = <0>;
1313 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1315 reg = <0x17c21000 0x1000>,
1316 <0x17c22000 0x1000>;
1317 };
1318
1319 frame@17c23000 {
1320 frame-number = <1>;
1321 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1322 reg = <0x17c23000 0x1000>;
1323 status = "disabled";
1324 };
1325
1326 frame@17c25000 {
1327 frame-number = <2>;
1328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1329 reg = <0x17c25000 0x1000>;
1330 status = "disabled";
1331 };
1332
1333 frame@17c27000 {
1334 frame-number = <3>;
1335 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1336 reg = <0x17c27000 0x1000>;
1337 status = "disabled";
1338 };
1339
1340 frame@17c29000 {
1341 frame-number = <4>;
1342 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1343 reg = <0x17c29000 0x1000>;
1344 status = "disabled";
1345 };
1346
1347 frame@17c2b000 {
1348 frame-number = <5>;
1349 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1350 reg = <0x17c2b000 0x1000>;
1351 status = "disabled";
1352 };
1353
1354 frame@17c2d000 {
1355 frame-number = <6>;
1356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1357 reg = <0x17c2d000 0x1000>;
1358 status = "disabled";
1359 };
1360 };
1361
1362 wifi: wifi@18800000 {
1363 compatible = "qcom,wcn3990-wifi";
1364 reg = <0 0x18800000 0 0x800000>;
1365 reg-names = "membase";
1366 memory-region = <&wlan_fw_mem>;
1367 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1379 iommus = <&apps_smmu 0x20 0x1>;
1380 qcom,msa-fixed-perm;
1381 status = "disabled";
1382 };
1383
1384 apps_rsc: rsc@18200000 {
1385 compatible = "qcom,rpmh-rsc";
1386 label = "apps_rsc";
1387 reg = <0x0 0x18200000 0x0 0x10000>,
1388 <0x0 0x18210000 0x0 0x10000>,
1389 <0x0 0x18220000 0x0 0x10000>;
1390 reg-names = "drv-0", "drv-1", "drv-2";
1391 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1394 qcom,tcs-offset = <0xd00>;
1395 qcom,drv-id = <2>;
1396 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1397 <WAKE_TCS 3>, <CONTROL_TCS 1>;
1398
1399 rpmhcc: clock-controller {
1400 compatible = "qcom,sm6350-rpmh-clk";
1401 #clock-cells = <1>;
1402 clock-names = "xo";
1403 clocks = <&xo_board>;
1404 };
1405
1406 rpmhpd: power-controller {
1407 compatible = "qcom,sm6350-rpmhpd";
1408 #power-domain-cells = <1>;
1409 operating-points-v2 = <&rpmhpd_opp_table>;
1410
1411 rpmhpd_opp_table: opp-table {
1412 compatible = "operating-points-v2";
1413
1414 rpmhpd_opp_ret: opp1 {
1415 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1416 };
1417
1418 rpmhpd_opp_min_svs: opp2 {
1419 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1420 };
1421
1422 rpmhpd_opp_low_svs: opp3 {
1423 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1424 };
1425
1426 rpmhpd_opp_svs: opp4 {
1427 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1428 };
1429
1430 rpmhpd_opp_svs_l1: opp5 {
1431 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1432 };
1433
1434 rpmhpd_opp_nom: opp6 {
1435 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1436 };
1437
1438 rpmhpd_opp_nom_l1: opp7 {
1439 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1440 };
1441
1442 rpmhpd_opp_nom_l2: opp8 {
1443 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1444 };
1445
1446 rpmhpd_opp_turbo: opp9 {
1447 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1448 };
1449
1450 rpmhpd_opp_turbo_l1: opp10 {
1451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1452 };
1453 };
1454 };
1455
1456 apps_bcm_voter: bcm-voter {
1457 compatible = "qcom,bcm-voter";
1458 };
1459 };
1460
1461 cpufreq_hw: cpufreq@18323000 {
1462 compatible = "qcom,cpufreq-hw";
1463 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
1464 reg-names = "freq-domain0", "freq-domain1";
1465 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1466 clock-names = "xo", "alternate";
1467
1468 #freq-domain-cells = <1>;
1469 };
1470 };
1471
1472 timer {
1473 compatible = "arm,armv8-timer";
1474 clock-frequency = <19200000>;
1475 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1476 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1477 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1478 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1479 };
1480 };
