0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
0004 */
0005
0006 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
0007 #include <dt-bindings/clock/qcom,rpmcc.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/power/qcom-rpmpd.h>
0011
0012 / {
0013 interrupt-parent = <&intc>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 chosen { };
0018
0019 clocks {
0020 xo_board: xo-board {
0021 compatible = "fixed-clock";
0022 #clock-cells = <0>;
0023 clock-frequency = <19200000>;
0024 clock-output-names = "xo_board";
0025 };
0026
0027 sleep_clk: sleep-clk {
0028 compatible = "fixed-clock";
0029 #clock-cells = <0>;
0030 clock-frequency = <32000>;
0031 clock-output-names = "sleep_clk";
0032 };
0033 };
0034
0035 cpus {
0036 #address-cells = <2>;
0037 #size-cells = <0>;
0038
0039 CPU0: cpu@0 {
0040 device_type = "cpu";
0041 compatible = "qcom,kryo260";
0042 reg = <0x0 0x0>;
0043 enable-method = "psci";
0044 capacity-dmips-mhz = <1024>;
0045 next-level-cache = <&L2_0>;
0046 L2_0: l2-cache {
0047 compatible = "cache";
0048 };
0049 };
0050
0051 CPU1: cpu@1 {
0052 device_type = "cpu";
0053 compatible = "qcom,kryo260";
0054 reg = <0x0 0x1>;
0055 enable-method = "psci";
0056 capacity-dmips-mhz = <1024>;
0057 next-level-cache = <&L2_0>;
0058 };
0059
0060 CPU2: cpu@2 {
0061 device_type = "cpu";
0062 compatible = "qcom,kryo260";
0063 reg = <0x0 0x2>;
0064 enable-method = "psci";
0065 capacity-dmips-mhz = <1024>;
0066 next-level-cache = <&L2_0>;
0067 };
0068
0069 CPU3: cpu@3 {
0070 device_type = "cpu";
0071 compatible = "qcom,kryo260";
0072 reg = <0x0 0x3>;
0073 enable-method = "psci";
0074 capacity-dmips-mhz = <1024>;
0075 next-level-cache = <&L2_0>;
0076 };
0077
0078 CPU4: cpu@100 {
0079 device_type = "cpu";
0080 compatible = "qcom,kryo260";
0081 reg = <0x0 0x100>;
0082 enable-method = "psci";
0083 capacity-dmips-mhz = <1638>;
0084 next-level-cache = <&L2_1>;
0085 L2_1: l2-cache {
0086 compatible = "cache";
0087 };
0088 };
0089
0090 CPU5: cpu@101 {
0091 device_type = "cpu";
0092 compatible = "qcom,kryo260";
0093 reg = <0x0 0x101>;
0094 enable-method = "psci";
0095 capacity-dmips-mhz = <1638>;
0096 next-level-cache = <&L2_1>;
0097 };
0098
0099 CPU6: cpu@102 {
0100 device_type = "cpu";
0101 compatible = "qcom,kryo260";
0102 reg = <0x0 0x102>;
0103 enable-method = "psci";
0104 capacity-dmips-mhz = <1638>;
0105 next-level-cache = <&L2_1>;
0106 };
0107
0108 CPU7: cpu@103 {
0109 device_type = "cpu";
0110 compatible = "qcom,kryo260";
0111 reg = <0x0 0x103>;
0112 enable-method = "psci";
0113 capacity-dmips-mhz = <1638>;
0114 next-level-cache = <&L2_1>;
0115 };
0116
0117 cpu-map {
0118 cluster0 {
0119 core0 {
0120 cpu = <&CPU0>;
0121 };
0122
0123 core1 {
0124 cpu = <&CPU1>;
0125 };
0126
0127 core2 {
0128 cpu = <&CPU2>;
0129 };
0130
0131 core3 {
0132 cpu = <&CPU3>;
0133 };
0134 };
0135
0136 cluster1 {
0137 core0 {
0138 cpu = <&CPU4>;
0139 };
0140
0141 core1 {
0142 cpu = <&CPU5>;
0143 };
0144
0145 core2 {
0146 cpu = <&CPU6>;
0147 };
0148
0149 core3 {
0150 cpu = <&CPU7>;
0151 };
0152 };
0153 };
0154 };
0155
0156 firmware {
0157 scm: scm {
0158 compatible = "qcom,scm-sm6125", "qcom,scm";
0159 #reset-cells = <1>;
0160 };
0161 };
0162
0163 memory@40000000 {
0164 /* We expect the bootloader to fill in the size */
0165 reg = <0x0 0x40000000 0x0 0x0>;
0166 device_type = "memory";
0167 };
0168
0169 pmu {
0170 compatible = "arm,armv8-pmuv3";
0171 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
0172 };
0173
0174 psci {
0175 compatible = "arm,psci-1.0";
0176 method = "smc";
0177 };
0178
0179 reserved_memory: reserved-memory {
0180 #address-cells = <2>;
0181 #size-cells = <2>;
0182 ranges;
0183
0184 hyp_mem: memory@45700000 {
0185 reg = <0x0 0x45700000 0x0 0x600000>;
0186 no-map;
0187 };
0188
0189 xbl_aop_mem: memory@45e00000 {
0190 reg = <0x0 0x45e00000 0x0 0x140000>;
0191 no-map;
0192 };
0193
0194 sec_apps_mem: memory@45fff000 {
0195 reg = <0x0 0x45fff000 0x0 0x1000>;
0196 no-map;
0197 };
0198
0199 smem_mem: memory@46000000 {
0200 reg = <0x0 0x46000000 0x0 0x200000>;
0201 no-map;
0202 };
0203
0204 reserved_mem1: memory@46200000 {
0205 reg = <0x0 0x46200000 0x0 0x2d00000>;
0206 no-map;
0207 };
0208
0209 camera_mem: memory@4ab00000 {
0210 reg = <0x0 0x4ab00000 0x0 0x500000>;
0211 no-map;
0212 };
0213
0214 modem_mem: memory@4b000000 {
0215 reg = <0x0 0x4b000000 0x0 0x7e00000>;
0216 no-map;
0217 };
0218
0219 venus_mem: memory@52e00000 {
0220 reg = <0x0 0x52e00000 0x0 0x500000>;
0221 no-map;
0222 };
0223
0224 wlan_msa_mem: memory@53300000 {
0225 reg = <0x0 0x53300000 0x0 0x200000>;
0226 no-map;
0227 };
0228
0229 cdsp_mem: memory@53500000 {
0230 reg = <0x0 0x53500000 0x0 0x1e00000>;
0231 no-map;
0232 };
0233
0234 adsp_pil_mem: memory@55300000 {
0235 reg = <0x0 0x55300000 0x0 0x1e00000>;
0236 no-map;
0237 };
0238
0239 ipa_fw_mem: memory@57100000 {
0240 reg = <0x0 0x57100000 0x0 0x10000>;
0241 no-map;
0242 };
0243
0244 ipa_gsi_mem: memory@57110000 {
0245 reg = <0x0 0x57110000 0x0 0x5000>;
0246 no-map;
0247 };
0248
0249 gpu_mem: memory@57115000 {
0250 reg = <0x0 0x57115000 0x0 0x2000>;
0251 no-map;
0252 };
0253
0254 cont_splash_mem: memory@5c000000 {
0255 reg = <0x0 0x5c000000 0x0 0x00f00000>;
0256 no-map;
0257 };
0258
0259 dfps_data_mem: memory@5cf00000 {
0260 reg = <0x0 0x5cf00000 0x0 0x0100000>;
0261 no-map;
0262 };
0263
0264 cdsp_sec_mem: memory@5f800000 {
0265 reg = <0x0 0x5f800000 0x0 0x1e00000>;
0266 no-map;
0267 };
0268
0269 qseecom_mem: memory@5e400000 {
0270 reg = <0x0 0x5e400000 0x0 0x1400000>;
0271 no-map;
0272 };
0273
0274 sdsp_mem: memory@f3000000 {
0275 reg = <0x0 0xf3000000 0x0 0x400000>;
0276 no-map;
0277 };
0278
0279 adsp_mem: memory@f3400000 {
0280 reg = <0x0 0xf3400000 0x0 0x800000>;
0281 no-map;
0282 };
0283
0284 qseecom_ta_mem: memory@13fc00000 {
0285 reg = <0x1 0x3fc00000 0x0 0x400000>;
0286 no-map;
0287 };
0288 };
0289
0290 rpm-glink {
0291 compatible = "qcom,glink-rpm";
0292
0293 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
0294 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0295 mboxes = <&apcs_glb 0>;
0296
0297 rpm_requests: rpm-requests {
0298 compatible = "qcom,rpm-sm6125";
0299 qcom,glink-channels = "rpm_requests";
0300
0301 rpmcc: clock-controller {
0302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
0303 #clock-cells = <1>;
0304 };
0305
0306 rpmpd: power-controller {
0307 compatible = "qcom,sm6125-rpmpd";
0308 #power-domain-cells = <1>;
0309 operating-points-v2 = <&rpmpd_opp_table>;
0310
0311 rpmpd_opp_table: opp-table {
0312 compatible = "operating-points-v2";
0313
0314 rpmpd_opp_ret: opp1 {
0315 opp-level = <RPM_SMD_LEVEL_RETENTION>;
0316 };
0317
0318 rpmpd_opp_ret_plus: opp2 {
0319 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
0320 };
0321
0322 rpmpd_opp_min_svs: opp3 {
0323 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
0324 };
0325
0326 rpmpd_opp_low_svs: opp4 {
0327 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
0328 };
0329
0330 rpmpd_opp_svs: opp5 {
0331 opp-level = <RPM_SMD_LEVEL_SVS>;
0332 };
0333
0334 rpmpd_opp_svs_plus: opp6 {
0335 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
0336 };
0337
0338 rpmpd_opp_nom: opp7 {
0339 opp-level = <RPM_SMD_LEVEL_NOM>;
0340 };
0341
0342 rpmpd_opp_nom_plus: opp8 {
0343 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
0344 };
0345
0346 rpmpd_opp_turbo: opp9 {
0347 opp-level = <RPM_SMD_LEVEL_TURBO>;
0348 };
0349
0350 rpmpd_opp_turbo_no_cpr: opp10 {
0351 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
0352 };
0353 };
0354 };
0355 };
0356 };
0357
0358 smem: smem {
0359 compatible = "qcom,smem";
0360 memory-region = <&smem_mem>;
0361 hwlocks = <&tcsr_mutex 3>;
0362 };
0363
0364 soc {
0365 #address-cells = <1>;
0366 #size-cells = <1>;
0367 ranges = <0x00 0x00 0x00 0xffffffff>;
0368 compatible = "simple-bus";
0369
0370 tcsr_mutex: hwlock@340000 {
0371 compatible = "qcom,tcsr-mutex";
0372 reg = <0x00340000 0x20000>;
0373 #hwlock-cells = <1>;
0374 };
0375
0376 tlmm: pinctrl@500000 {
0377 compatible = "qcom,sm6125-tlmm";
0378 reg = <0x00500000 0x400000>,
0379 <0x00900000 0x400000>,
0380 <0x00d00000 0x400000>;
0381 reg-names = "west", "south", "east";
0382 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0383 gpio-controller;
0384 gpio-ranges = <&tlmm 0 0 134>;
0385 #gpio-cells = <2>;
0386 interrupt-controller;
0387 #interrupt-cells = <2>;
0388
0389 sdc2_off_state: sdc2-off-state {
0390 clk {
0391 pins = "sdc2_clk";
0392 drive-strength = <2>;
0393 bias-disable;
0394 };
0395
0396 cmd {
0397 pins = "sdc2_cmd";
0398 drive-strength = <2>;
0399 bias-pull-up;
0400 };
0401
0402 data {
0403 pins = "sdc2_data";
0404 drive-strength = <2>;
0405 bias-pull-up;
0406 };
0407 };
0408
0409 sdc2_on_state: sdc2-on-state {
0410 clk {
0411 pins = "sdc2_clk";
0412 drive-strength = <16>;
0413 bias-disable;
0414 };
0415
0416 cmd {
0417 pins = "sdc2_cmd";
0418 drive-strength = <10>;
0419 bias-pull-up;
0420 };
0421
0422 data {
0423 pins = "sdc2_data";
0424 drive-strength = <10>;
0425 bias-pull-up;
0426 };
0427 };
0428 };
0429
0430 gcc: clock-controller@1400000 {
0431 compatible = "qcom,gcc-sm6125";
0432 reg = <0x01400000 0x1f0000>;
0433 #clock-cells = <1>;
0434 #reset-cells = <1>;
0435 #power-domain-cells = <1>;
0436 clock-names = "bi_tcxo", "sleep_clk";
0437 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
0438 };
0439
0440 hsusb_phy1: phy@1613000 {
0441 compatible = "qcom,msm8996-qusb2-phy";
0442 reg = <0x01613000 0x180>;
0443 #phy-cells = <0>;
0444
0445 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
0446 <&gcc GCC_AHB2PHY_USB_CLK>;
0447 clock-names = "ref", "cfg_ahb";
0448
0449 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
0450 status = "disabled";
0451 };
0452
0453 rpm_msg_ram: sram@45f0000 {
0454 compatible = "qcom,rpm-msg-ram";
0455 reg = <0x045f0000 0x7000>;
0456 };
0457
0458 sdhc_1: mmc@4744000 {
0459 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
0460 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
0461 reg-names = "hc", "core";
0462
0463 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
0464 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
0465 interrupt-names = "hc_irq", "pwr_irq";
0466
0467 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0468 <&gcc GCC_SDCC1_APPS_CLK>,
0469 <&xo_board>;
0470 clock-names = "iface", "core", "xo";
0471
0472 power-domains = <&rpmpd SM6125_VDDCX>;
0473
0474 qcom,dll-config = <0x000f642c>;
0475 qcom,ddr-config = <0x80040873>;
0476
0477 bus-width = <8>;
0478 non-removable;
0479 status = "disabled";
0480 };
0481
0482 sdhc_2: mmc@4784000 {
0483 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
0484 reg = <0x04784000 0x1000>;
0485 reg-names = "hc";
0486
0487 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
0488 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
0489 interrupt-names = "hc_irq", "pwr_irq";
0490
0491 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
0492 <&gcc GCC_SDCC2_APPS_CLK>,
0493 <&xo_board>;
0494 clock-names = "iface", "core", "xo";
0495
0496 pinctrl-0 = <&sdc2_on_state>;
0497 pinctrl-1 = <&sdc2_off_state>;
0498 pinctrl-names = "default", "sleep";
0499
0500 power-domains = <&rpmpd SM6125_VDDCX>;
0501
0502 qcom,dll-config = <0x0007642c>;
0503 qcom,ddr-config = <0x80040873>;
0504
0505 bus-width = <4>;
0506 status = "disabled";
0507 };
0508
0509 usb3: usb@4ef8800 {
0510 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
0511 reg = <0x04ef8800 0x400>;
0512 #address-cells = <1>;
0513 #size-cells = <1>;
0514 ranges;
0515
0516 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
0517 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
0518 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
0519 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
0520 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
0521 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
0522 clock-names = "cfg_noc",
0523 "core",
0524 "iface",
0525 "sleep",
0526 "mock_utmi",
0527 "xo";
0528
0529 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
0530 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
0531 assigned-clock-rates = <19200000>, <66666667>;
0532
0533 power-domains = <&gcc USB30_PRIM_GDSC>;
0534 qcom,select-utmi-as-pipe-clk;
0535 status = "disabled";
0536
0537 usb3_dwc3: usb@4e00000 {
0538 compatible = "snps,dwc3";
0539 reg = <0x04e00000 0xcd00>;
0540 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
0541 phys = <&hsusb_phy1>;
0542 phy-names = "usb2-phy";
0543 snps,dis_u2_susphy_quirk;
0544 snps,dis_enblslpm_quirk;
0545 maximum-speed = "high-speed";
0546 dr_mode = "peripheral";
0547 };
0548 };
0549
0550 sram@4690000 {
0551 compatible = "qcom,rpm-stats";
0552 reg = <0x04690000 0x10000>;
0553 };
0554
0555 spmi_bus: spmi@1c40000 {
0556 compatible = "qcom,spmi-pmic-arb";
0557 reg = <0x01c40000 0x1100>,
0558 <0x01e00000 0x2000000>,
0559 <0x03e00000 0x100000>,
0560 <0x03f00000 0xa0000>,
0561 <0x01c0a000 0x26000>;
0562 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
0563 interrupt-names = "periph_irq";
0564 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
0565 qcom,ee = <0>;
0566 qcom,channel = <0>;
0567 #address-cells = <2>;
0568 #size-cells = <0>;
0569 interrupt-controller;
0570 #interrupt-cells = <4>;
0571 cell-index = <0>;
0572 };
0573
0574 apcs_glb: mailbox@f111000 {
0575 compatible = "qcom,sm6125-apcs-hmss-global";
0576 reg = <0x0f111000 0x1000>;
0577
0578 #mbox-cells = <1>;
0579 };
0580
0581 timer@f120000 {
0582 compatible = "arm,armv7-timer-mem";
0583 #address-cells = <1>;
0584 #size-cells = <1>;
0585 ranges;
0586 reg = <0x0f120000 0x1000>;
0587 clock-frequency = <19200000>;
0588
0589 frame@f121000 {
0590 frame-number = <0>;
0591 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0592 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0593 reg = <0x0f121000 0x1000>,
0594 <0x0f122000 0x1000>;
0595 };
0596
0597 frame@f123000 {
0598 frame-number = <1>;
0599 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0600 reg = <0x0f123000 0x1000>;
0601 status = "disabled";
0602 };
0603
0604 frame@f124000 {
0605 frame-number = <2>;
0606 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0607 reg = <0x0f124000 0x1000>;
0608 status = "disabled";
0609 };
0610
0611 frame@f125000 {
0612 frame-number = <3>;
0613 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0614 reg = <0x0f125000 0x1000>;
0615 status = "disabled";
0616 };
0617
0618 frame@f126000 {
0619 frame-number = <4>;
0620 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0621 reg = <0x0f126000 0x1000>;
0622 status = "disabled";
0623 };
0624
0625 frame@f127000 {
0626 frame-number = <5>;
0627 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0628 reg = <0x0f127000 0x1000>;
0629 status = "disabled";
0630 };
0631
0632 frame@f128000 {
0633 frame-number = <6>;
0634 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0635 reg = <0x0f128000 0x1000>;
0636 status = "disabled";
0637 };
0638 };
0639
0640 intc: interrupt-controller@f200000 {
0641 compatible = "arm,gic-v3";
0642 reg = <0x0f200000 0x20000>,
0643 <0x0f300000 0x100000>;
0644 #interrupt-cells = <3>;
0645 interrupt-controller;
0646 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0647 };
0648 };
0649
0650 timer {
0651 compatible = "arm,armv8-timer";
0652 interrupts = <GIC_PPI 1 0xf08
0653 GIC_PPI 2 0xf08
0654 GIC_PPI 3 0xf08
0655 GIC_PPI 0 0xf08>;
0656 clock-frequency = <19200000>;
0657 };
0658 };
