0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Cheza device tree source (common between revisions)
0004 *
0005 * Copyright 2018 Google LLC.
0006 */
0007
0008 #include <dt-bindings/input/input.h>
0009 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
0010 #include "sdm845.dtsi"
0011
0012 /* PMICs depend on spmi_bus label and so must come after SoC */
0013 #include "pm8005.dtsi"
0014 #include "pm8998.dtsi"
0015
0016 / {
0017 aliases {
0018 bluetooth0 = &bluetooth;
0019 hsuart0 = &uart6;
0020 serial0 = &uart9;
0021 wifi0 = &wifi;
0022 };
0023
0024 chosen {
0025 stdout-path = "serial0:115200n8";
0026 };
0027
0028 backlight: backlight {
0029 compatible = "pwm-backlight";
0030 pwms = <&cros_ec_pwm 0>;
0031 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
0032 power-supply = <&ppvar_sys>;
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&ap_edp_bklten>;
0035 };
0036
0037 /* FIXED REGULATORS - parents above children */
0038
0039 /* This is the top level supply and variable voltage */
0040 ppvar_sys: ppvar-sys-regulator {
0041 compatible = "regulator-fixed";
0042 regulator-name = "ppvar_sys";
0043 regulator-always-on;
0044 regulator-boot-on;
0045 };
0046
0047 /* This divides ppvar_sys by 2, so voltage is variable */
0048 src_vph_pwr: src-vph-pwr-regulator {
0049 compatible = "regulator-fixed";
0050 regulator-name = "src_vph_pwr";
0051
0052 /* EC turns on with switchcap_on_l; always on for AP */
0053 regulator-always-on;
0054 regulator-boot-on;
0055
0056 vin-supply = <&ppvar_sys>;
0057 };
0058
0059 pp5000_a: pp5000-a-regulator {
0060 compatible = "regulator-fixed";
0061 regulator-name = "pp5000_a";
0062
0063 /* EC turns on with en_pp5000_a; always on for AP */
0064 regulator-always-on;
0065 regulator-boot-on;
0066 regulator-min-microvolt = <5000000>;
0067 regulator-max-microvolt = <5000000>;
0068
0069 vin-supply = <&ppvar_sys>;
0070 };
0071
0072 src_vreg_bob: src-vreg-bob-regulator {
0073 compatible = "regulator-fixed";
0074 regulator-name = "src_vreg_bob";
0075
0076 /* EC turns on with vbob_en; always on for AP */
0077 regulator-always-on;
0078 regulator-boot-on;
0079 regulator-min-microvolt = <3600000>;
0080 regulator-max-microvolt = <3600000>;
0081
0082 vin-supply = <&ppvar_sys>;
0083 };
0084
0085 pp3300_dx_edp: pp3300-dx-edp-regulator {
0086 compatible = "regulator-fixed";
0087 regulator-name = "pp3300_dx_edp";
0088
0089 regulator-min-microvolt = <3300000>;
0090 regulator-max-microvolt = <3300000>;
0091
0092 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
0093 enable-active-high;
0094 pinctrl-names = "default";
0095 pinctrl-0 = <&en_pp3300_dx_edp>;
0096 };
0097
0098 /*
0099 * Apparently RPMh does not provide support for PM8998 S4 because it
0100 * is always-on; model it as a fixed regulator.
0101 */
0102 src_pp1800_s4a: pm8998-smps4 {
0103 compatible = "regulator-fixed";
0104 regulator-name = "src_pp1800_s4a";
0105
0106 regulator-min-microvolt = <1800000>;
0107 regulator-max-microvolt = <1800000>;
0108
0109 regulator-always-on;
0110 regulator-boot-on;
0111
0112 vin-supply = <&src_vph_pwr>;
0113 };
0114
0115 /* BOARD-SPECIFIC TOP LEVEL NODES */
0116
0117 gpio-keys {
0118 compatible = "gpio-keys";
0119 pinctrl-names = "default";
0120 pinctrl-0 = <&pen_eject_odl>;
0121
0122 switch-pen-insert {
0123 label = "Pen Insert";
0124 /* Insert = low, eject = high */
0125 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
0126 linux,code = <SW_PEN_INSERTED>;
0127 linux,input-type = <EV_SW>;
0128 wakeup-source;
0129 };
0130 };
0131
0132 panel: panel {
0133 compatible = "innolux,p120zdg-bf1";
0134 power-supply = <&pp3300_dx_edp>;
0135 backlight = <&backlight>;
0136 no-hpd;
0137
0138 ports {
0139 panel_in: port {
0140 panel_in_edp: endpoint {
0141 remote-endpoint = <&sn65dsi86_out>;
0142 };
0143 };
0144 };
0145 };
0146 };
0147
0148 &psci {
0149 /delete-node/ cpu0;
0150 /delete-node/ cpu1;
0151 /delete-node/ cpu2;
0152 /delete-node/ cpu3;
0153 /delete-node/ cpu4;
0154 /delete-node/ cpu5;
0155 /delete-node/ cpu6;
0156 /delete-node/ cpu7;
0157 /delete-node/ cpu-cluster0;
0158 };
0159
0160 &cpus {
0161 /delete-node/ domain-idle-states;
0162 };
0163
0164 &cpu_idle_states {
0165 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
0166 compatible = "arm,idle-state";
0167 idle-state-name = "little-power-down";
0168 arm,psci-suspend-param = <0x40000003>;
0169 entry-latency-us = <350>;
0170 exit-latency-us = <461>;
0171 min-residency-us = <1890>;
0172 local-timer-stop;
0173 };
0174
0175 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
0176 compatible = "arm,idle-state";
0177 idle-state-name = "little-rail-power-down";
0178 arm,psci-suspend-param = <0x40000004>;
0179 entry-latency-us = <360>;
0180 exit-latency-us = <531>;
0181 min-residency-us = <3934>;
0182 local-timer-stop;
0183 };
0184
0185 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
0186 compatible = "arm,idle-state";
0187 idle-state-name = "big-power-down";
0188 arm,psci-suspend-param = <0x40000003>;
0189 entry-latency-us = <264>;
0190 exit-latency-us = <621>;
0191 min-residency-us = <952>;
0192 local-timer-stop;
0193 };
0194
0195 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
0196 compatible = "arm,idle-state";
0197 idle-state-name = "big-rail-power-down";
0198 arm,psci-suspend-param = <0x40000004>;
0199 entry-latency-us = <702>;
0200 exit-latency-us = <1061>;
0201 min-residency-us = <4488>;
0202 local-timer-stop;
0203 };
0204
0205 CLUSTER_SLEEP_0: cluster-sleep-0 {
0206 compatible = "arm,idle-state";
0207 idle-state-name = "cluster-power-down";
0208 arm,psci-suspend-param = <0x400000F4>;
0209 entry-latency-us = <3263>;
0210 exit-latency-us = <6562>;
0211 min-residency-us = <9987>;
0212 local-timer-stop;
0213 };
0214 };
0215
0216 &CPU0 {
0217 /delete-property/ power-domains;
0218 /delete-property/ power-domain-names;
0219 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
0220 &LITTLE_CPU_SLEEP_1
0221 &CLUSTER_SLEEP_0>;
0222 };
0223
0224 &CPU1 {
0225 /delete-property/ power-domains;
0226 /delete-property/ power-domain-names;
0227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
0228 &LITTLE_CPU_SLEEP_1
0229 &CLUSTER_SLEEP_0>;
0230 };
0231
0232 &CPU2 {
0233 /delete-property/ power-domains;
0234 /delete-property/ power-domain-names;
0235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
0236 &LITTLE_CPU_SLEEP_1
0237 &CLUSTER_SLEEP_0>;
0238 };
0239
0240 &CPU3 {
0241 /delete-property/ power-domains;
0242 /delete-property/ power-domain-names;
0243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
0244 &LITTLE_CPU_SLEEP_1
0245 &CLUSTER_SLEEP_0>;
0246 };
0247
0248 &CPU4 {
0249 /delete-property/ power-domains;
0250 /delete-property/ power-domain-names;
0251 cpu-idle-states = <&BIG_CPU_SLEEP_0
0252 &BIG_CPU_SLEEP_1
0253 &CLUSTER_SLEEP_0>;
0254 };
0255
0256 &CPU5 {
0257 /delete-property/ power-domains;
0258 /delete-property/ power-domain-names;
0259 cpu-idle-states = <&BIG_CPU_SLEEP_0
0260 &BIG_CPU_SLEEP_1
0261 &CLUSTER_SLEEP_0>;
0262 };
0263
0264 &CPU6 {
0265 /delete-property/ power-domains;
0266 /delete-property/ power-domain-names;
0267 cpu-idle-states = <&BIG_CPU_SLEEP_0
0268 &BIG_CPU_SLEEP_1
0269 &CLUSTER_SLEEP_0>;
0270 };
0271
0272 &CPU7 {
0273 /delete-property/ power-domains;
0274 /delete-property/ power-domain-names;
0275 cpu-idle-states = <&BIG_CPU_SLEEP_0
0276 &BIG_CPU_SLEEP_1
0277 &CLUSTER_SLEEP_0>;
0278 };
0279
0280 /*
0281 * Reserved memory changes
0282 *
0283 * Putting this all together (out of order with the rest of the file) to keep
0284 * all modifications to the memory map (from sdm845.dtsi) in one place.
0285 */
0286
0287 /*
0288 * Our mpss_region is 8MB bigger than the default one and that conflicts
0289 * with venus_mem and cdsp_mem.
0290 *
0291 * For venus_mem we'll delete and re-create at a different address.
0292 *
0293 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but
0294 * that also means we need to delete cdsp_pas.
0295 */
0296 /delete-node/ &venus_mem;
0297 /delete-node/ &cdsp_mem;
0298 /delete-node/ &cdsp_pas;
0299 /delete-node/ &gpu_mem;
0300
0301 /* Increase the size from 120 MB to 128 MB */
0302 &mpss_region {
0303 reg = <0 0x8e000000 0 0x8000000>;
0304 };
0305
0306 /* Increase the size from 2MB to 8MB */
0307 &rmtfs_mem {
0308 reg = <0 0x88f00000 0 0x800000>;
0309 };
0310
0311 / {
0312 reserved-memory {
0313 venus_mem: memory@96000000 {
0314 reg = <0 0x96000000 0 0x500000>;
0315 no-map;
0316 };
0317 };
0318 };
0319
0320 &qspi {
0321 status = "okay";
0322 pinctrl-names = "default";
0323 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
0324
0325 flash@0 {
0326 compatible = "jedec,spi-nor";
0327 reg = <0>;
0328
0329 /*
0330 * In theory chip supports up to 104 MHz and controller up
0331 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use
0332 * that for now. b:117440651
0333 */
0334 spi-max-frequency = <25000000>;
0335 spi-tx-bus-width = <2>;
0336 spi-rx-bus-width = <2>;
0337 };
0338 };
0339
0340
0341 &apps_rsc {
0342 pm8998-rpmh-regulators {
0343 compatible = "qcom,pm8998-rpmh-regulators";
0344 qcom,pmic-id = "a";
0345
0346 vdd-s1-supply = <&src_vph_pwr>;
0347 vdd-s2-supply = <&src_vph_pwr>;
0348 vdd-s3-supply = <&src_vph_pwr>;
0349 vdd-s4-supply = <&src_vph_pwr>;
0350 vdd-s5-supply = <&src_vph_pwr>;
0351 vdd-s6-supply = <&src_vph_pwr>;
0352 vdd-s7-supply = <&src_vph_pwr>;
0353 vdd-s8-supply = <&src_vph_pwr>;
0354 vdd-s9-supply = <&src_vph_pwr>;
0355 vdd-s10-supply = <&src_vph_pwr>;
0356 vdd-s11-supply = <&src_vph_pwr>;
0357 vdd-s12-supply = <&src_vph_pwr>;
0358 vdd-s13-supply = <&src_vph_pwr>;
0359 vdd-l1-l27-supply = <&src_pp1025_s7a>;
0360 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>;
0361 vdd-l3-l11-supply = <&src_pp1025_s7a>;
0362 vdd-l4-l5-supply = <&src_pp1025_s7a>;
0363 vdd-l6-supply = <&src_vph_pwr>;
0364 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>;
0365 vdd-l9-supply = <&src_pp2040_s5a>;
0366 vdd-l10-l23-l25-supply = <&src_vreg_bob>;
0367 vdd-l13-l19-l21-supply = <&src_vreg_bob>;
0368 vdd-l16-l28-supply = <&src_vreg_bob>;
0369 vdd-l18-l22-supply = <&src_vreg_bob>;
0370 vdd-l20-l24-supply = <&src_vreg_bob>;
0371 vdd-l26-supply = <&src_pp1350_s3a>;
0372 vin-lvs-1-2-supply = <&src_pp1800_s4a>;
0373
0374 src_pp1125_s2a: smps2 {
0375 regulator-min-microvolt = <1100000>;
0376 regulator-max-microvolt = <1100000>;
0377 };
0378
0379 src_pp1350_s3a: smps3 {
0380 regulator-min-microvolt = <1352000>;
0381 regulator-max-microvolt = <1352000>;
0382 };
0383
0384 src_pp2040_s5a: smps5 {
0385 regulator-min-microvolt = <1904000>;
0386 regulator-max-microvolt = <2040000>;
0387 };
0388
0389 src_pp1025_s7a: smps7 {
0390 regulator-min-microvolt = <900000>;
0391 regulator-max-microvolt = <1028000>;
0392 };
0393
0394 vdd_qusb_hs0:
0395 vdda_hp_pcie_core:
0396 vdda_mipi_csi0_0p9:
0397 vdda_mipi_csi1_0p9:
0398 vdda_mipi_csi2_0p9:
0399 vdda_mipi_dsi0_pll:
0400 vdda_mipi_dsi1_pll:
0401 vdda_qlink_lv:
0402 vdda_qlink_lv_ck:
0403 vdda_qrefs_0p875:
0404 vdda_pcie_core:
0405 vdda_pll_cc_ebi01:
0406 vdda_pll_cc_ebi23:
0407 vdda_sp_sensor:
0408 vdda_ufs1_core:
0409 vdda_ufs2_core:
0410 vdda_usb1_ss_core:
0411 vdda_usb2_ss_core:
0412 src_pp875_l1a: ldo1 {
0413 regulator-min-microvolt = <880000>;
0414 regulator-max-microvolt = <880000>;
0415 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0416 };
0417
0418 vddpx_10:
0419 src_pp1200_l2a: ldo2 {
0420 regulator-min-microvolt = <1200000>;
0421 regulator-max-microvolt = <1200000>;
0422 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0423
0424 /* TODO: why??? */
0425 regulator-always-on;
0426 };
0427
0428 pp1000_l3a_sdr845: ldo3 {
0429 regulator-min-microvolt = <1000000>;
0430 regulator-max-microvolt = <1000000>;
0431 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0432 };
0433
0434 vdd_wcss_cx:
0435 vdd_wcss_mx:
0436 vdda_wcss_pll:
0437 src_pp800_l5a: ldo5 {
0438 regulator-min-microvolt = <800000>;
0439 regulator-max-microvolt = <800000>;
0440 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0441 };
0442
0443 vddpx_13:
0444 src_pp1800_l6a: ldo6 {
0445 regulator-min-microvolt = <1856000>;
0446 regulator-max-microvolt = <1856000>;
0447 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0448 };
0449
0450 pp1800_l7a_wcn3990: ldo7 {
0451 regulator-min-microvolt = <1800000>;
0452 regulator-max-microvolt = <1800000>;
0453 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0454 };
0455
0456 src_pp1200_l8a: ldo8 {
0457 regulator-min-microvolt = <1200000>;
0458 regulator-max-microvolt = <1248000>;
0459 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0460 };
0461
0462 pp1800_dx_pen:
0463 src_pp1800_l9a: ldo9 {
0464 regulator-min-microvolt = <1800000>;
0465 regulator-max-microvolt = <1800000>;
0466 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0467 };
0468
0469 src_pp1800_l10a: ldo10 {
0470 regulator-min-microvolt = <1800000>;
0471 regulator-max-microvolt = <1800000>;
0472 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0473 };
0474
0475 pp1000_l11a_sdr845: ldo11 {
0476 regulator-min-microvolt = <1000000>;
0477 regulator-max-microvolt = <1048000>;
0478 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0479 };
0480
0481 vdd_qfprom:
0482 vdd_qfprom_sp:
0483 vdda_apc1_cs_1p8:
0484 vdda_gfx_cs_1p8:
0485 vdda_qrefs_1p8:
0486 vdda_qusb_hs0_1p8:
0487 vddpx_11:
0488 src_pp1800_l12a: ldo12 {
0489 regulator-min-microvolt = <1800000>;
0490 regulator-max-microvolt = <1800000>;
0491 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0492 };
0493
0494 vddpx_2:
0495 src_pp2950_l13a: ldo13 {
0496 regulator-min-microvolt = <1800000>;
0497 regulator-max-microvolt = <2960000>;
0498 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0499 };
0500
0501 src_pp1800_l14a: ldo14 {
0502 regulator-min-microvolt = <1800000>;
0503 regulator-max-microvolt = <1800000>;
0504 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0505 };
0506
0507 src_pp1800_l15a: ldo15 {
0508 regulator-min-microvolt = <1800000>;
0509 regulator-max-microvolt = <1800000>;
0510 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0511 };
0512
0513 pp2700_l16a: ldo16 {
0514 regulator-min-microvolt = <2704000>;
0515 regulator-max-microvolt = <2704000>;
0516 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0517 };
0518
0519 src_pp1300_l17a: ldo17 {
0520 regulator-min-microvolt = <1304000>;
0521 regulator-max-microvolt = <1304000>;
0522 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0523 };
0524
0525 pp2700_l18a: ldo18 {
0526 regulator-min-microvolt = <2704000>;
0527 regulator-max-microvolt = <2960000>;
0528 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0529 };
0530
0531 /*
0532 * NOTE: this rail should have been called
0533 * src_pp3300_l19a in the schematic
0534 */
0535 src_pp3000_l19a: ldo19 {
0536 regulator-min-microvolt = <3304000>;
0537 regulator-max-microvolt = <3304000>;
0538
0539 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0540 };
0541
0542 src_pp2950_l20a: ldo20 {
0543 regulator-min-microvolt = <2704000>;
0544 regulator-max-microvolt = <2960000>;
0545 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0546 };
0547
0548 src_pp2950_l21a: ldo21 {
0549 regulator-min-microvolt = <2704000>;
0550 regulator-max-microvolt = <2960000>;
0551 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0552 };
0553
0554 pp3300_hub:
0555 src_pp3300_l22a: ldo22 {
0556 regulator-min-microvolt = <3304000>;
0557 regulator-max-microvolt = <3304000>;
0558 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0559 /*
0560 * HACK: Should add a usb hub node and driver
0561 * to turn this on and off at suspend/resume time
0562 */
0563 regulator-boot-on;
0564 regulator-always-on;
0565 };
0566
0567 pp3300_l23a_ch1_wcn3990: ldo23 {
0568 regulator-min-microvolt = <3000000>;
0569 regulator-max-microvolt = <3312000>;
0570 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0571 };
0572
0573 vdda_qusb_hs0_3p1:
0574 src_pp3075_l24a: ldo24 {
0575 regulator-min-microvolt = <3088000>;
0576 regulator-max-microvolt = <3088000>;
0577 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0578 };
0579
0580 pp3300_l25a_ch0_wcn3990: ldo25 {
0581 regulator-min-microvolt = <3304000>;
0582 regulator-max-microvolt = <3304000>;
0583 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0584 };
0585
0586 pp1200_hub:
0587 vdda_hp_pcie_1p2:
0588 vdda_hv_ebi0:
0589 vdda_hv_ebi1:
0590 vdda_hv_ebi2:
0591 vdda_hv_ebi3:
0592 vdda_mipi_csi_1p25:
0593 vdda_mipi_dsi0_1p2:
0594 vdda_mipi_dsi1_1p2:
0595 vdda_pcie_1p2:
0596 vdda_ufs1_1p2:
0597 vdda_ufs2_1p2:
0598 vdda_usb1_ss_1p2:
0599 vdda_usb2_ss_1p2:
0600 src_pp1200_l26a: ldo26 {
0601 regulator-min-microvolt = <1200000>;
0602 regulator-max-microvolt = <1200000>;
0603 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0604 };
0605
0606 pp3300_dx_pen:
0607 src_pp3300_l28a: ldo28 {
0608 regulator-min-microvolt = <3304000>;
0609 regulator-max-microvolt = <3304000>;
0610 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
0611 };
0612
0613 src_pp1800_lvs1: lvs1 {
0614 regulator-min-microvolt = <1800000>;
0615 regulator-max-microvolt = <1800000>;
0616 };
0617
0618 src_pp1800_lvs2: lvs2 {
0619 regulator-min-microvolt = <1800000>;
0620 regulator-max-microvolt = <1800000>;
0621 };
0622 };
0623
0624 pm8005-rpmh-regulators {
0625 compatible = "qcom,pm8005-rpmh-regulators";
0626 qcom,pmic-id = "c";
0627
0628 vdd-s1-supply = <&src_vph_pwr>;
0629 vdd-s2-supply = <&src_vph_pwr>;
0630 vdd-s3-supply = <&src_vph_pwr>;
0631 vdd-s4-supply = <&src_vph_pwr>;
0632
0633 src_pp600_s3c: smps3 {
0634 regulator-min-microvolt = <600000>;
0635 regulator-max-microvolt = <600000>;
0636 };
0637 };
0638 };
0639
0640 &dsi0 {
0641 status = "okay";
0642 vdda-supply = <&vdda_mipi_dsi0_1p2>;
0643
0644 ports {
0645 port@1 {
0646 endpoint {
0647 remote-endpoint = <&sn65dsi86_in>;
0648 data-lanes = <0 1 2 3>;
0649 };
0650 };
0651 };
0652 };
0653
0654 &dsi0_phy {
0655 status = "okay";
0656 vdds-supply = <&vdda_mipi_dsi0_pll>;
0657 };
0658
0659 edp_brij_i2c: &i2c3 {
0660 status = "okay";
0661 clock-frequency = <400000>;
0662
0663 sn65dsi86_bridge: bridge@2d {
0664 compatible = "ti,sn65dsi86";
0665 reg = <0x2d>;
0666 pinctrl-names = "default";
0667 pinctrl-0 = <&edp_brij_en &edp_brij_irq>;
0668
0669 interrupt-parent = <&tlmm>;
0670 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
0671
0672 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
0673
0674 vpll-supply = <&src_pp1800_s4a>;
0675 vccio-supply = <&src_pp1800_s4a>;
0676 vcca-supply = <&src_pp1200_l2a>;
0677 vcc-supply = <&src_pp1200_l2a>;
0678
0679 clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
0680 clock-names = "refclk";
0681
0682 no-hpd;
0683
0684 ports {
0685 #address-cells = <1>;
0686 #size-cells = <0>;
0687
0688 port@0 {
0689 reg = <0>;
0690 sn65dsi86_in: endpoint {
0691 remote-endpoint = <&dsi0_out>;
0692 };
0693 };
0694
0695 port@1 {
0696 reg = <1>;
0697 sn65dsi86_out: endpoint {
0698 remote-endpoint = <&panel_in_edp>;
0699 };
0700 };
0701 };
0702 };
0703 };
0704
0705 ap_pen_1v8: &i2c11 {
0706 status = "okay";
0707 clock-frequency = <400000>;
0708
0709 digitizer@9 {
0710 compatible = "wacom,w9013", "hid-over-i2c";
0711 reg = <0x9>;
0712 pinctrl-names = "default";
0713 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
0714
0715 vdd-supply = <&pp3300_dx_pen>;
0716 vddl-supply = <&pp1800_dx_pen>;
0717 post-power-on-delay-ms = <100>;
0718
0719 interrupt-parent = <&tlmm>;
0720 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
0721
0722 hid-descr-addr = <0x1>;
0723 };
0724 };
0725
0726 amp_i2c: &i2c12 {
0727 status = "okay";
0728 clock-frequency = <400000>;
0729 };
0730
0731 ap_ts_i2c: &i2c14 {
0732 status = "okay";
0733 clock-frequency = <400000>;
0734
0735 touchscreen@10 {
0736 compatible = "elan,ekth3500";
0737 reg = <0x10>;
0738 pinctrl-names = "default";
0739 pinctrl-0 = <&ts_int_l &ts_reset_l>;
0740
0741 interrupt-parent = <&tlmm>;
0742 interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
0743
0744 vcc33-supply = <&src_pp3300_l28a>;
0745
0746 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
0747 };
0748 };
0749
0750 &gmu {
0751 status = "okay";
0752 };
0753
0754 &gpu {
0755 status = "okay";
0756 };
0757
0758 &ipa {
0759 status = "okay";
0760 modem-init;
0761 };
0762
0763 &lpasscc {
0764 status = "okay";
0765 };
0766
0767 &mdss {
0768 status = "okay";
0769 };
0770
0771 /*
0772 * Cheza fw does not properly program the GPU aperture to allow the
0773 * GPU to update the SMMU pagetables for context switches. Work
0774 * around this by dropping the "qcom,adreno-smmu" compat string.
0775 */
0776 &adreno_smmu {
0777 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
0778 };
0779
0780 &mss_pil {
0781 status = "okay";
0782
0783 iommus = <&apps_smmu 0x781 0x0>,
0784 <&apps_smmu 0x724 0x3>;
0785 };
0786
0787 &pm8998_pwrkey {
0788 status = "disabled";
0789 };
0790
0791 &qupv3_id_0 {
0792 status = "okay";
0793 iommus = <&apps_smmu 0x0 0x3>;
0794 };
0795
0796 &qupv3_id_1 {
0797 status = "okay";
0798 iommus = <&apps_smmu 0x6c0 0x3>;
0799 };
0800
0801 &sdhc_2 {
0802 status = "okay";
0803
0804 pinctrl-names = "default";
0805 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>;
0806
0807 vmmc-supply = <&src_pp2950_l21a>;
0808 vqmmc-supply = <&vddpx_2>;
0809
0810 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
0811 };
0812
0813 &spi0 {
0814 status = "okay";
0815 };
0816
0817 &spi5 {
0818 status = "okay";
0819
0820 tpm@0 {
0821 compatible = "google,cr50";
0822 reg = <0>;
0823 pinctrl-names = "default";
0824 pinctrl-0 = <&h1_ap_int_odl>;
0825 spi-max-frequency = <800000>;
0826 interrupt-parent = <&tlmm>;
0827 interrupts = <129 IRQ_TYPE_EDGE_RISING>;
0828 };
0829 };
0830
0831 &spi10 {
0832 status = "okay";
0833
0834 cros_ec: ec@0 {
0835 compatible = "google,cros-ec-spi";
0836 reg = <0>;
0837 interrupt-parent = <&tlmm>;
0838 interrupts = <122 IRQ_TYPE_LEVEL_LOW>;
0839 pinctrl-names = "default";
0840 pinctrl-0 = <&ec_ap_int_l>;
0841 spi-max-frequency = <3000000>;
0842
0843 cros_ec_pwm: pwm {
0844 compatible = "google,cros-ec-pwm";
0845 #pwm-cells = <1>;
0846 };
0847
0848 i2c_tunnel: i2c-tunnel {
0849 compatible = "google,cros-ec-i2c-tunnel";
0850 google,remote-bus = <0>;
0851 #address-cells = <1>;
0852 #size-cells = <0>;
0853 };
0854 };
0855 };
0856
0857 #include <arm/cros-ec-keyboard.dtsi>
0858 #include <arm/cros-ec-sbs.dtsi>
0859
0860 &uart6 {
0861 status = "okay";
0862
0863 bluetooth: wcn3990-bt {
0864 compatible = "qcom,wcn3990-bt";
0865 vddio-supply = <&src_pp1800_s4a>;
0866 vddxo-supply = <&pp1800_l7a_wcn3990>;
0867 vddrf-supply = <&src_pp1300_l17a>;
0868 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>;
0869 max-speed = <3200000>;
0870 };
0871 };
0872
0873 &uart9 {
0874 status = "okay";
0875 };
0876
0877 &ufs_mem_hc {
0878 status = "okay";
0879
0880 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
0881
0882 vcc-supply = <&src_pp2950_l20a>;
0883 vcc-max-microamp = <600000>;
0884 };
0885
0886 &ufs_mem_phy {
0887 status = "okay";
0888
0889 vdda-phy-supply = <&vdda_ufs1_core>;
0890 vdda-pll-supply = <&vdda_ufs1_1p2>;
0891 };
0892
0893 &usb_1 {
0894 status = "okay";
0895
0896 /* We'll use this as USB 2.0 only */
0897 qcom,select-utmi-as-pipe-clk;
0898 };
0899
0900 &usb_1_dwc3 {
0901 /*
0902 * The hardware design intends this port to be hooked up in peripheral
0903 * mode, so we'll hardcode it here. Some details:
0904 * - SDM845 expects only a single Type C connector so it has only one
0905 * native Type C port but cheza has two Type C connectors.
0906 * - The only source of DP is the single native Type C port.
0907 * - On cheza we want to be able to hook DP up to _either_ of the
0908 * two Type C connectors and want to be able to achieve 4 lanes of DP.
0909 * - When you configure a Type C port for 4 lanes of DP you lose USB3.
0910 * - In order to make everything work, the native Type C port is always
0911 * configured as 4-lanes DP so it's always available.
0912 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then
0913 * sent to the two Type C connectors.
0914 * - The extra USB2 lines from the native Type C port are always
0915 * setup as "peripheral" so that we can mux them over to one connector
0916 * or the other if someone needs the connector configured as a gadget
0917 * (but they only get USB2 speeds).
0918 *
0919 * All the hardware muxes would allow us to hook things up in different
0920 * ways to some potential benefit for static configurations (you could
0921 * achieve extra USB2 bandwidth by using two different ports for the
0922 * two connectors or possibly even get USB3 peripheral mode), but in
0923 * each case you end up forcing to disconnect/reconnect an in-use
0924 * USB session in some cases depending on what you hotplug into the
0925 * other connector. Thus hardcoding this as peripheral makes sense.
0926 */
0927 dr_mode = "peripheral";
0928
0929 /*
0930 * We always need the high speed pins as 4-lanes DP in case someone
0931 * hotplugs a DP peripheral. Thus limit this port to a max of high
0932 * speed.
0933 */
0934 maximum-speed = "high-speed";
0935
0936 /*
0937 * We don't need the usb3-phy since we run in highspeed mode always, so
0938 * re-define these properties removing the superspeed USB PHY reference.
0939 */
0940 phys = <&usb_1_hsphy>;
0941 phy-names = "usb2-phy";
0942 };
0943
0944 &usb_1_hsphy {
0945 status = "okay";
0946
0947 vdd-supply = <&vdda_usb1_ss_core>;
0948 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
0949 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
0950
0951 qcom,imp-res-offset-value = <8>;
0952 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
0953 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
0954 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
0955 };
0956
0957 &usb_2 {
0958 status = "okay";
0959 };
0960
0961 &usb_2_dwc3 {
0962 /* We have this hooked up to a hub and we always use in host mode */
0963 dr_mode = "host";
0964 };
0965
0966 &usb_2_hsphy {
0967 status = "okay";
0968
0969 vdd-supply = <&vdda_usb2_ss_core>;
0970 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
0971 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
0972
0973 qcom,imp-res-offset-value = <8>;
0974 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
0975 };
0976
0977 &usb_2_qmpphy {
0978 status = "okay";
0979
0980 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
0981 vdda-pll-supply = <&vdda_usb2_ss_core>;
0982 };
0983
0984 &wifi {
0985 status = "okay";
0986
0987 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >;
0988 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>;
0989 vdd-1.3-rfa-supply = <&src_pp1300_l17a>;
0990 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>;
0991 };
0992
0993 /* PINCTRL - additions to nodes defined in sdm845.dtsi */
0994
0995 &qspi_cs0 {
0996 pinconf {
0997 pins = "gpio90";
0998 bias-disable;
0999 };
1000 };
1001
1002 &qspi_clk {
1003 pinconf {
1004 pins = "gpio95";
1005 bias-disable;
1006 };
1007 };
1008
1009 &qspi_data01 {
1010 pinconf {
1011 pins = "gpio91", "gpio92";
1012
1013 /* High-Z when no transfers; nice to park the lines */
1014 bias-pull-up;
1015 };
1016 };
1017
1018 &qup_i2c3_default {
1019 pinconf {
1020 pins = "gpio41", "gpio42";
1021 drive-strength = <2>;
1022
1023 /* Has external pullup */
1024 bias-disable;
1025 };
1026 };
1027
1028 &qup_i2c11_default {
1029 pinconf {
1030 pins = "gpio31", "gpio32";
1031 drive-strength = <2>;
1032
1033 /* Has external pullup */
1034 bias-disable;
1035 };
1036 };
1037
1038 &qup_i2c12_default {
1039 pinconf {
1040 pins = "gpio49", "gpio50";
1041 drive-strength = <2>;
1042
1043 /* Has external pullup */
1044 bias-disable;
1045 };
1046 };
1047
1048 &qup_i2c14_default {
1049 pinconf {
1050 pins = "gpio33", "gpio34";
1051 drive-strength = <2>;
1052
1053 /* Has external pullup */
1054 bias-disable;
1055 };
1056 };
1057
1058 &qup_spi0_default {
1059 pinconf {
1060 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1061 drive-strength = <2>;
1062 bias-disable;
1063 };
1064 };
1065
1066 &qup_spi5_default {
1067 pinconf {
1068 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1069 drive-strength = <2>;
1070 bias-disable;
1071 };
1072 };
1073
1074 &qup_spi10_default {
1075 pinconf {
1076 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1077 drive-strength = <2>;
1078 bias-disable;
1079 };
1080 };
1081
1082 &qup_uart6_default {
1083 /* Change pinmux to all 4 pins since CTS and RTS are connected */
1084 pinmux {
1085 pins = "gpio45", "gpio46",
1086 "gpio47", "gpio48";
1087 };
1088
1089 pinconf-cts {
1090 /*
1091 * Configure a pull-down on 45 (CTS) to match the pull of
1092 * the Bluetooth module.
1093 */
1094 pins = "gpio45";
1095 bias-pull-down;
1096 };
1097
1098 pinconf-rts-tx {
1099 /* We'll drive 46 (RTS) and 47 (TX), so no pull */
1100 pins = "gpio46", "gpio47";
1101 drive-strength = <2>;
1102 bias-disable;
1103 };
1104
1105 pinconf-rx {
1106 /*
1107 * Configure a pull-up on 48 (RX). This is needed to avoid
1108 * garbage data when the TX pin of the Bluetooth module is
1109 * in tri-state (module powered off or not driving the
1110 * signal yet).
1111 */
1112 pins = "gpio48";
1113 bias-pull-up;
1114 };
1115 };
1116
1117 &qup_uart9_default {
1118 pinconf-tx {
1119 pins = "gpio4";
1120 drive-strength = <2>;
1121 bias-disable;
1122 };
1123
1124 pinconf-rx {
1125 pins = "gpio5";
1126 drive-strength = <2>;
1127 bias-pull-up;
1128 };
1129 };
1130
1131 /* PINCTRL - board-specific pinctrl */
1132 &pm8005_gpio {
1133 gpio-line-names = "",
1134 "",
1135 "SLB",
1136 "";
1137 };
1138
1139 &pm8998_adc {
1140 adc-chan@4d {
1141 reg = <ADC5_AMUX_THM1_100K_PU>;
1142 label = "sdm_temp";
1143 };
1144
1145 adc-chan@4e {
1146 reg = <ADC5_AMUX_THM2_100K_PU>;
1147 label = "quiet_temp";
1148 };
1149
1150 adc-chan@4f {
1151 reg = <ADC5_AMUX_THM3_100K_PU>;
1152 label = "lte_temp_1";
1153 };
1154
1155 adc-chan@50 {
1156 reg = <ADC5_AMUX_THM4_100K_PU>;
1157 label = "lte_temp_2";
1158 };
1159
1160 adc-chan@51 {
1161 reg = <ADC5_AMUX_THM5_100K_PU>;
1162 label = "charger_temp";
1163 };
1164 };
1165
1166 &pm8998_gpio {
1167 gpio-line-names = "",
1168 "",
1169 "SW_CTRL",
1170 "",
1171 "",
1172 "",
1173 "",
1174 "",
1175 "",
1176 "",
1177 "",
1178 "",
1179 "",
1180 "",
1181 "",
1182 "",
1183 "",
1184 "",
1185 "",
1186 "",
1187 "",
1188 "CFG_OPT1",
1189 "WCSS_PWR_REQ",
1190 "",
1191 "CFG_OPT2",
1192 "SLB";
1193 };
1194
1195 &tlmm {
1196 /*
1197 * pinctrl settings for pins that have no real owners.
1198 */
1199 pinctrl-names = "default", "sleep";
1200 pinctrl-0 = <&bios_flash_wp_r_l>,
1201 <&ap_suspend_l_deassert>;
1202
1203 pinctrl-1 = <&bios_flash_wp_r_l>,
1204 <&ap_suspend_l_assert>;
1205
1206 /*
1207 * Hogs prevent usermode from changing the value. A GPIO can be both
1208 * here and in the pinctrl section.
1209 */
1210 ap-suspend-l-hog {
1211 gpio-hog;
1212 gpios = <126 GPIO_ACTIVE_LOW>;
1213 output-low;
1214 };
1215
1216 ap_edp_bklten: ap-edp-bklten {
1217 pinmux {
1218 pins = "gpio37";
1219 function = "gpio";
1220 };
1221
1222 pinconf {
1223 pins = "gpio37";
1224 drive-strength = <2>;
1225 bias-disable;
1226 };
1227 };
1228
1229 bios_flash_wp_r_l: bios-flash-wp-r-l {
1230 pinmux {
1231 pins = "gpio128";
1232 function = "gpio";
1233 input-enable;
1234 };
1235
1236 pinconf {
1237 pins = "gpio128";
1238 bias-disable;
1239 };
1240 };
1241
1242 ec_ap_int_l: ec-ap-int-l {
1243 pinmux {
1244 pins = "gpio122";
1245 function = "gpio";
1246 input-enable;
1247 };
1248
1249 pinconf {
1250 pins = "gpio122";
1251 bias-pull-up;
1252 };
1253 };
1254
1255 edp_brij_en: edp-brij-en {
1256 pinmux {
1257 pins = "gpio102";
1258 function = "gpio";
1259 };
1260
1261 pinconf {
1262 pins = "gpio102";
1263 drive-strength = <2>;
1264 bias-disable;
1265 };
1266 };
1267
1268 edp_brij_irq: edp-brij-irq {
1269 pinmux {
1270 pins = "gpio10";
1271 function = "gpio";
1272 };
1273
1274 pinconf {
1275 pins = "gpio10";
1276 drive-strength = <2>;
1277 bias-pull-down;
1278 };
1279 };
1280
1281 en_pp3300_dx_edp: en-pp3300-dx-edp {
1282 pinmux {
1283 pins = "gpio43";
1284 function = "gpio";
1285 };
1286
1287 pinconf {
1288 pins = "gpio43";
1289 drive-strength = <2>;
1290 bias-disable;
1291 };
1292 };
1293
1294 h1_ap_int_odl: h1-ap-int-odl {
1295 pinmux {
1296 pins = "gpio129";
1297 function = "gpio";
1298 input-enable;
1299 };
1300
1301 pinconf {
1302 pins = "gpio129";
1303 bias-pull-up;
1304 };
1305 };
1306
1307 pen_eject_odl: pen-eject-odl {
1308 pinmux {
1309 pins = "gpio119";
1310 function = "gpio";
1311 bias-pull-up;
1312 };
1313 };
1314
1315 pen_irq_l: pen-irq-l {
1316 pinmux {
1317 pins = "gpio24";
1318 function = "gpio";
1319 };
1320
1321 pinconf {
1322 pins = "gpio24";
1323
1324 /* Has external pullup */
1325 bias-disable;
1326 };
1327 };
1328
1329 pen_pdct_l: pen-pdct-l {
1330 pinmux {
1331 pins = "gpio63";
1332 function = "gpio";
1333 };
1334
1335 pinconf {
1336 pins = "gpio63";
1337
1338 /* Has external pullup */
1339 bias-disable;
1340 };
1341 };
1342
1343 pen_rst_l: pen-rst-l {
1344 pinmux {
1345 pins = "gpio23";
1346 function = "gpio";
1347 };
1348
1349 pinconf {
1350 pins = "gpio23";
1351 bias-disable;
1352 drive-strength = <2>;
1353
1354 /*
1355 * The pen driver doesn't currently support
1356 * driving this reset line. By specifying
1357 * output-high here we're relying on the fact
1358 * that this pin has a default pulldown at boot
1359 * (which makes sure the pen was in reset if it
1360 * was powered) and then we set it high here to
1361 * take it out of reset. Better would be if the
1362 * pen driver could control this and we could
1363 * remove "output-high" here.
1364 */
1365 output-high;
1366 };
1367 };
1368
1369 sdc2_clk: sdc2-clk {
1370 pinconf {
1371 pins = "sdc2_clk";
1372 bias-disable;
1373
1374 /*
1375 * It seems that mmc_test reports errors if drive
1376 * strength is not 16.
1377 */
1378 drive-strength = <16>;
1379 };
1380 };
1381
1382 sdc2_cmd: sdc2-cmd {
1383 pinconf {
1384 pins = "sdc2_cmd";
1385 bias-pull-up;
1386 drive-strength = <16>;
1387 };
1388 };
1389
1390 sdc2_data: sdc2-data {
1391 pinconf {
1392 pins = "sdc2_data";
1393 bias-pull-up;
1394 drive-strength = <16>;
1395 };
1396 };
1397
1398 sd_cd_odl: sd-cd-odl {
1399 pinmux {
1400 pins = "gpio44";
1401 function = "gpio";
1402 };
1403
1404 pinconf {
1405 pins = "gpio44";
1406 bias-pull-up;
1407 };
1408 };
1409
1410 ts_int_l: ts-int-l {
1411 pinmux {
1412 pins = "gpio125";
1413 function = "gpio";
1414 };
1415
1416 pinconf {
1417 pins = "gpio125";
1418 bias-pull-up;
1419 };
1420 };
1421
1422 ts_reset_l: ts-reset-l {
1423 pinmux {
1424 pins = "gpio118";
1425 function = "gpio";
1426 };
1427
1428 pinconf {
1429 pins = "gpio118";
1430 bias-disable;
1431 drive-strength = <2>;
1432 };
1433 };
1434
1435 ap_suspend_l_assert: ap_suspend_l_assert {
1436 config {
1437 pins = "gpio126";
1438 function = "gpio";
1439 bias-no-pull;
1440 drive-strength = <2>;
1441 output-low;
1442 };
1443 };
1444
1445 ap_suspend_l_deassert: ap_suspend_l_deassert {
1446 config {
1447 pins = "gpio126";
1448 function = "gpio";
1449 bias-no-pull;
1450 drive-strength = <2>;
1451 output-high;
1452 };
1453 };
1454 };
1455
1456 &venus {
1457 status = "okay";
1458
1459 video-firmware {
1460 iommus = <&apps_smmu 0x10b2 0x0>;
1461 };
1462 };
