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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Cheza board device tree source
0004 *
0005 * Copyright 2018 Google LLC.
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "sdm845-cheza.dtsi"
0011
0012 / {
0013 model = "Google Cheza (rev3+)";
0014 compatible = "google,cheza", "qcom,sdm845";
0015 };
0016
0017 /* PINCTRL - board-specific pinctrl */
0018
0019 &tlmm {
0020 gpio-line-names = "AP_SPI_FP_MISO",
0021 "AP_SPI_FP_MOSI",
0022 "AP_SPI_FP_CLK",
0023 "AP_SPI_FP_CS_L",
0024 "UART_AP_TX_DBG_RX",
0025 "UART_DBG_TX_AP_RX",
0026 "BRIJ_SUSPEND",
0027 "FP_RST_L",
0028 "FCAM_EN",
0029 "",
0030 "EDP_BRIJ_IRQ",
0031 "EC_IN_RW_ODL",
0032 "",
0033 "RCAM_MCLK",
0034 "FCAM_MCLK",
0035 "",
0036 "RCAM_EN",
0037 "CCI0_SDA",
0038 "CCI0_SCL",
0039 "CCI1_SDA",
0040 "CCI1_SCL",
0041 "FCAM_RST_L",
0042 "FPMCU_BOOT0",
0043 "PEN_RST_L",
0044 "PEN_IRQ_L",
0045 "FPMCU_SEL_OD",
0046 "RCAM_VSYNC",
0047 "ESIM_MISO",
0048 "ESIM_MOSI",
0049 "ESIM_CLK",
0050 "ESIM_CS_L",
0051 "AP_PEN_1V8_SDA",
0052 "AP_PEN_1V8_SCL",
0053 "AP_TS_I2C_SDA",
0054 "AP_TS_I2C_SCL",
0055 "RCAM_RST_L",
0056 "",
0057 "AP_EDP_BKLTEN",
0058 "AP_BRD_ID0",
0059 "BOOT_CONFIG_4",
0060 "AMP_IRQ_L",
0061 "EDP_BRIJ_I2C_SDA",
0062 "EDP_BRIJ_I2C_SCL",
0063 "EN_PP3300_DX_EDP",
0064 "SD_CD_ODL",
0065 "BT_UART_RTS",
0066 "BT_UART_CTS",
0067 "BT_UART_RXD",
0068 "BT_UART_TXD",
0069 "AMP_I2C_SDA",
0070 "AMP_I2C_SCL",
0071 "AP_BRD_ID2",
0072 "",
0073 "AP_EC_SPI_CLK",
0074 "AP_EC_SPI_CS_L",
0075 "AP_EC_SPI_MISO",
0076 "AP_EC_SPI_MOSI",
0077 "FORCED_USB_BOOT",
0078 "AMP_BCLK",
0079 "AMP_LRCLK",
0080 "AMP_DOUT",
0081 "AMP_DIN",
0082 "AP_BRD_ID1",
0083 "PEN_PDCT_L",
0084 "HP_MCLK",
0085 "HP_BCLK",
0086 "HP_LRCLK",
0087 "HP_DOUT",
0088 "HP_DIN",
0089 "",
0090 "",
0091 "",
0092 "",
0093 "BT_SLIMBUS_DATA",
0094 "BT_SLIMBUS_CLK",
0095 "AMP_RESET_L",
0096 "",
0097 "FCAM_VSYNC",
0098 "",
0099 "AP_SKU_ID0",
0100 "EC_WOV_BCLK",
0101 "EC_WOV_LRCLK",
0102 "EC_WOV_DOUT",
0103 "",
0104 "",
0105 "AP_H1_SPI_MISO",
0106 "AP_H1_SPI_MOSI",
0107 "AP_H1_SPI_CLK",
0108 "AP_H1_SPI_CS_L",
0109 "",
0110 "AP_SPI_CS0_L",
0111 "AP_SPI_MOSI",
0112 "AP_SPI_MISO",
0113 "",
0114 "",
0115 "AP_SPI_CLK",
0116 "",
0117 "RFFE6_CLK",
0118 "RFFE6_DATA",
0119 "BOOT_CONFIG_1",
0120 "BOOT_CONFIG_2",
0121 "BOOT_CONFIG_0",
0122 "EDP_BRIJ_EN",
0123 "",
0124 "USB_HS_TX_EN",
0125 "UIM2_DATA",
0126 "UIM2_CLK",
0127 "UIM2_RST",
0128 "UIM2_PRESENT",
0129 "UIM1_DATA",
0130 "UIM1_CLK",
0131 "UIM1_RST",
0132 "",
0133 "AP_SKU_ID1",
0134 "SDM_GRFC_8",
0135 "SDM_GRFC_9",
0136 "AP_RST_REQ",
0137 "HP_IRQ",
0138 "TS_RESET_L",
0139 "PEN_EJECT_ODL",
0140 "HUB_RST_L",
0141 "FP_TO_AP_IRQ",
0142 "AP_EC_INT_L",
0143 "",
0144 "",
0145 "TS_INT_L",
0146 "AP_SUSPEND_L",
0147 "SDM_GRFC_3",
0148 /*
0149 * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
0150 * call it BIOS_FLASH_WP_R_L.
0151 */
0152 "AP_FLASH_WP_L",
0153 "H1_AP_INT_ODL",
0154 "QLINK_REQ",
0155 "QLINK_EN",
0156 "SDM_GRFC_2",
0157 "BOOT_CONFIG_3",
0158 "WMSS_RESET_L",
0159 "SDM_GRFC_0",
0160 "SDM_GRFC_1",
0161 "RFFE3_DATA",
0162 "RFFE3_CLK",
0163 "RFFE4_DATA",
0164 "RFFE4_CLK",
0165 "RFFE5_DATA",
0166 "RFFE5_CLK",
0167 "GNSS_EN",
0168 "WCI2_LTE_COEX_RXD",
0169 "WCI2_LTE_COEX_TXD",
0170 "AP_RAM_ID0",
0171 "AP_RAM_ID1",
0172 "RFFE1_DATA",
0173 "RFFE1_CLK";
0174 };
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