0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Cheza board device tree source
0004 *
0005 * Copyright 2018 Google LLC.
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "sdm845-cheza.dtsi"
0011
0012 / {
0013 model = "Google Cheza (rev2)";
0014 compatible = "google,cheza-rev2", "qcom,sdm845";
0015
0016 /*
0017 * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
0018 */
0019
0020 /*
0021 * NOTE: Technically pp3500_a is not the exact same signal as
0022 * pp3500_a_vbob (there's a load switch between them and the EC can
0023 * control pp3500_a via "en_pp3300_a"), but from the AP's point of
0024 * view they are the same.
0025 */
0026 pp3500_a:
0027 pp3500_a_vbob: pp3500-a-vbob-regulator {
0028 compatible = "regulator-fixed";
0029 regulator-name = "vreg_bob";
0030
0031 /*
0032 * Comes on automatically when pp5000_ldo comes on, which
0033 * comes on automatically when ppvar_sys comes on
0034 */
0035 regulator-always-on;
0036 regulator-boot-on;
0037 regulator-min-microvolt = <3500000>;
0038 regulator-max-microvolt = <3500000>;
0039
0040 vin-supply = <&ppvar_sys>;
0041 };
0042
0043 pp3300_dx_edp: pp3300-dx-edp-regulator {
0044 /* Yes, it's really 3.5 despite the name of the signal */
0045 regulator-min-microvolt = <3500000>;
0046 regulator-max-microvolt = <3500000>;
0047
0048 vin-supply = <&pp3500_a>;
0049 };
0050 };
0051
0052 /* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
0053
0054 /*
0055 * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
0056 * that limits them to 3.0, and trying to run at 3.3V with that old firmware
0057 * prevents the system from booting.
0058 */
0059 &src_pp3000_l19a {
0060 regulator-min-microvolt = <3008000>;
0061 regulator-max-microvolt = <3008000>;
0062 };
0063
0064 &src_pp3300_l22a {
0065 /delete-property/regulator-boot-on;
0066 /delete-property/regulator-always-on;
0067 };
0068
0069 &src_pp3300_l28a {
0070 regulator-min-microvolt = <3008000>;
0071 regulator-max-microvolt = <3008000>;
0072 };
0073
0074 &src_vreg_bob {
0075 regulator-min-microvolt = <3500000>;
0076 regulator-max-microvolt = <3500000>;
0077 vin-supply = <&pp3500_a_vbob>;
0078 };
0079
0080 /*
0081 * NON-REGULATOR OVERRIDES
0082 * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
0083 */
0084
0085 /* PINCTRL - board-specific pinctrl */
0086
0087 &tlmm {
0088 gpio-line-names = "AP_SPI_FP_MISO",
0089 "AP_SPI_FP_MOSI",
0090 "AP_SPI_FP_CLK",
0091 "AP_SPI_FP_CS_L",
0092 "UART_AP_TX_DBG_RX",
0093 "UART_DBG_TX_AP_RX",
0094 "BRIJ_SUSPEND",
0095 "FP_RST_L",
0096 "FCAM_EN",
0097 "",
0098 "EDP_BRIJ_IRQ",
0099 "EC_IN_RW_ODL",
0100 "",
0101 "RCAM_MCLK",
0102 "FCAM_MCLK",
0103 "",
0104 "RCAM_EN",
0105 "CCI0_SDA",
0106 "CCI0_SCL",
0107 "CCI1_SDA",
0108 "CCI1_SCL",
0109 "FCAM_RST_L",
0110 "FPMCU_BOOT0",
0111 "PEN_RST_L",
0112 "PEN_IRQ_L",
0113 "FPMCU_SEL_OD",
0114 "RCAM_VSYNC",
0115 "ESIM_MISO",
0116 "ESIM_MOSI",
0117 "ESIM_CLK",
0118 "ESIM_CS_L",
0119 "AP_PEN_1V8_SDA",
0120 "AP_PEN_1V8_SCL",
0121 "AP_TS_I2C_SDA",
0122 "AP_TS_I2C_SCL",
0123 "RCAM_RST_L",
0124 "",
0125 "AP_EDP_BKLTEN",
0126 "AP_BRD_ID1",
0127 "BOOT_CONFIG_4",
0128 "AMP_IRQ_L",
0129 "EDP_BRIJ_I2C_SDA",
0130 "EDP_BRIJ_I2C_SCL",
0131 "EN_PP3300_DX_EDP",
0132 "SD_CD_ODL",
0133 "BT_UART_RTS",
0134 "BT_UART_CTS",
0135 "BT_UART_RXD",
0136 "BT_UART_TXD",
0137 "AMP_I2C_SDA",
0138 "AMP_I2C_SCL",
0139 "AP_BRD_ID3",
0140 "",
0141 "AP_EC_SPI_CLK",
0142 "AP_EC_SPI_CS_L",
0143 "AP_EC_SPI_MISO",
0144 "AP_EC_SPI_MOSI",
0145 "FORCED_USB_BOOT",
0146 "AMP_BCLK",
0147 "AMP_LRCLK",
0148 "AMP_DOUT",
0149 "AMP_DIN",
0150 "AP_BRD_ID2",
0151 "PEN_PDCT_L",
0152 "HP_MCLK",
0153 "HP_BCLK",
0154 "HP_LRCLK",
0155 "HP_DOUT",
0156 "HP_DIN",
0157 "",
0158 "",
0159 "",
0160 "",
0161 "BT_SLIMBUS_DATA",
0162 "BT_SLIMBUS_CLK",
0163 "AMP_RESET_L",
0164 "",
0165 "FCAM_VSYNC",
0166 "",
0167 "AP_SKU_ID1",
0168 "EC_WOV_BCLK",
0169 "EC_WOV_LRCLK",
0170 "EC_WOV_DOUT",
0171 "",
0172 "",
0173 "AP_H1_SPI_MISO",
0174 "AP_H1_SPI_MOSI",
0175 "AP_H1_SPI_CLK",
0176 "AP_H1_SPI_CS_L",
0177 "",
0178 "AP_SPI_CS0_L",
0179 "AP_SPI_MOSI",
0180 "AP_SPI_MISO",
0181 "",
0182 "",
0183 "AP_SPI_CLK",
0184 "",
0185 "RFFE6_CLK",
0186 "RFFE6_DATA",
0187 "BOOT_CONFIG_1",
0188 "BOOT_CONFIG_2",
0189 "BOOT_CONFIG_0",
0190 "EDP_BRIJ_EN",
0191 "",
0192 "USB_HS_TX_EN",
0193 "UIM2_DATA",
0194 "UIM2_CLK",
0195 "UIM2_RST",
0196 "UIM2_PRESENT",
0197 "UIM1_DATA",
0198 "UIM1_CLK",
0199 "UIM1_RST",
0200 "",
0201 "AP_SKU_ID2",
0202 "SDM_GRFC_8",
0203 "SDM_GRFC_9",
0204 "AP_RST_REQ",
0205 "HP_IRQ",
0206 "TS_RESET_L",
0207 "PEN_EJECT_ODL",
0208 "HUB_RST_L",
0209 "FP_TO_AP_IRQ",
0210 "AP_EC_INT_L",
0211 "",
0212 "",
0213 "TS_INT_L",
0214 "AP_SUSPEND_L",
0215 "SDM_GRFC_3",
0216 "",
0217 "H1_AP_INT_ODL",
0218 "QLINK_REQ",
0219 "QLINK_EN",
0220 "SDM_GRFC_2",
0221 "BOOT_CONFIG_3",
0222 "WMSS_RESET_L",
0223 "SDM_GRFC_0",
0224 "SDM_GRFC_1",
0225 "RFFE3_DATA",
0226 "RFFE3_CLK",
0227 "RFFE4_DATA",
0228 "RFFE4_CLK",
0229 "RFFE5_DATA",
0230 "RFFE5_CLK",
0231 "GNSS_EN",
0232 "WCI2_LTE_COEX_RXD",
0233 "WCI2_LTE_COEX_TXD",
0234 "AP_RAM_ID1",
0235 "AP_RAM_ID2",
0236 "RFFE1_DATA",
0237 "RFFE1_CLK";
0238 };
