0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2018, Craig Tatlor.
0004 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
0005 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
0006 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
0007 * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
0008 */
0009
0010 #include "sdm630.dtsi"
0011
0012 &adreno_gpu {
0013 compatible = "qcom,adreno-512.0", "qcom,adreno";
0014 operating-points-v2 = <&gpu_sdm660_opp_table>;
0015
0016 gpu_sdm660_opp_table: opp-table {
0017 compatible = "operating-points-v2";
0018
0019 /*
0020 * 775MHz is only available on the highest speed bin
0021 * Though it cannot be used for now due to interconnect
0022 * framework not supporting multiple frequencies
0023 * at the same opp-level
0024
0025 opp-750000000 {
0026 opp-hz = /bits/ 64 <750000000>;
0027 opp-level = <RPM_SMD_LEVEL_TURBO>;
0028 opp-peak-kBps = <5412000>;
0029 opp-supported-hw = <0xCHECKME>;
0030 };
0031
0032 * These OPPs are correct, but we are lacking support for the
0033 * GPU regulator. Hence, disable them for now to prevent the
0034 * platform from hanging on high graphics loads.
0035
0036 opp-700000000 {
0037 opp-hz = /bits/ 64 <700000000>;
0038 opp-level = <RPM_SMD_LEVEL_TURBO>;
0039 opp-peak-kBps = <5184000>;
0040 opp-supported-hw = <0xFF>;
0041 };
0042
0043 opp-647000000 {
0044 opp-hz = /bits/ 64 <647000000>;
0045 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
0046 opp-peak-kBps = <4068000>;
0047 opp-supported-hw = <0xFF>;
0048 };
0049
0050 opp-588000000 {
0051 opp-hz = /bits/ 64 <588000000>;
0052 opp-level = <RPM_SMD_LEVEL_NOM>;
0053 opp-peak-kBps = <3072000>;
0054 opp-supported-hw = <0xFF>;
0055 };
0056
0057 opp-465000000 {
0058 opp-hz = /bits/ 64 <465000000>;
0059 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
0060 opp-peak-kBps = <2724000>;
0061 opp-supported-hw = <0xFF>;
0062 };
0063
0064 opp-370000000 {
0065 opp-hz = /bits/ 64 <370000000>;
0066 opp-level = <RPM_SMD_LEVEL_SVS>;
0067 opp-peak-kBps = <2188000>;
0068 opp-supported-hw = <0xFF>;
0069 };
0070 */
0071
0072 opp-266000000 {
0073 opp-hz = /bits/ 64 <266000000>;
0074 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
0075 opp-peak-kBps = <1648000>;
0076 opp-supported-hw = <0xFF>;
0077 };
0078
0079 opp-160000000 {
0080 opp-hz = /bits/ 64 <160000000>;
0081 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
0082 opp-peak-kBps = <1200000>;
0083 opp-supported-hw = <0xFF>;
0084 };
0085 };
0086 };
0087
0088 &CPU0 {
0089 compatible = "qcom,kryo260";
0090 capacity-dmips-mhz = <1024>;
0091 /delete-property/ operating-points-v2;
0092 };
0093
0094 &CPU1 {
0095 compatible = "qcom,kryo260";
0096 capacity-dmips-mhz = <1024>;
0097 /delete-property/ operating-points-v2;
0098 };
0099
0100 &CPU2 {
0101 compatible = "qcom,kryo260";
0102 capacity-dmips-mhz = <1024>;
0103 /delete-property/ operating-points-v2;
0104 };
0105
0106 &CPU3 {
0107 compatible = "qcom,kryo260";
0108 capacity-dmips-mhz = <1024>;
0109 /delete-property/ operating-points-v2;
0110 };
0111
0112 &CPU4 {
0113 compatible = "qcom,kryo260";
0114 capacity-dmips-mhz = <640>;
0115 /delete-property/ operating-points-v2;
0116 };
0117
0118 &CPU5 {
0119 compatible = "qcom,kryo260";
0120 capacity-dmips-mhz = <640>;
0121 /delete-property/ operating-points-v2;
0122 };
0123
0124 &CPU6 {
0125 compatible = "qcom,kryo260";
0126 capacity-dmips-mhz = <640>;
0127 /delete-property/ operating-points-v2;
0128 };
0129
0130 &CPU7 {
0131 compatible = "qcom,kryo260";
0132 capacity-dmips-mhz = <640>;
0133 /delete-property/ operating-points-v2;
0134 };
0135
0136 &gcc {
0137 compatible = "qcom,gcc-sdm660";
0138 };
0139
0140 &gpucc {
0141 compatible = "qcom,gpucc-sdm660";
0142 };
0143
0144 &mdp {
0145 ports {
0146 port@1 {
0147 reg = <1>;
0148 mdp5_intf2_out: endpoint {
0149 remote-endpoint = <&dsi1_in>;
0150 };
0151 };
0152 };
0153 };
0154
0155 &mdss {
0156 dsi1: dsi@c996000 {
0157 compatible = "qcom,mdss-dsi-ctrl";
0158 reg = <0x0c996000 0x400>;
0159 reg-names = "dsi_ctrl";
0160
0161 /* DSI1 shares the OPP table with DSI0 */
0162 operating-points-v2 = <&dsi_opp_table>;
0163 power-domains = <&rpmpd SDM660_VDDCX>;
0164
0165 interrupt-parent = <&mdss>;
0166 interrupts = <5>;
0167
0168 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
0169 <&mmcc PCLK1_CLK_SRC>;
0170 assigned-clock-parents = <&dsi1_phy 0>,
0171 <&dsi1_phy 1>;
0172
0173 clocks = <&mmcc MDSS_MDP_CLK>,
0174 <&mmcc MDSS_BYTE1_CLK>,
0175 <&mmcc MDSS_BYTE1_INTF_CLK>,
0176 <&mmcc MNOC_AHB_CLK>,
0177 <&mmcc MDSS_AHB_CLK>,
0178 <&mmcc MDSS_AXI_CLK>,
0179 <&mmcc MISC_AHB_CLK>,
0180 <&mmcc MDSS_PCLK1_CLK>,
0181 <&mmcc MDSS_ESC1_CLK>;
0182 clock-names = "mdp_core",
0183 "byte",
0184 "byte_intf",
0185 "mnoc",
0186 "iface",
0187 "bus",
0188 "core_mmss",
0189 "pixel",
0190 "core";
0191
0192 phys = <&dsi1_phy>;
0193 phy-names = "dsi";
0194
0195 status = "disabled";
0196
0197 ports {
0198 #address-cells = <1>;
0199 #size-cells = <0>;
0200
0201 port@0 {
0202 reg = <0>;
0203 dsi1_in: endpoint {
0204 remote-endpoint = <&mdp5_intf2_out>;
0205 };
0206 };
0207
0208 port@1 {
0209 reg = <1>;
0210 dsi1_out: endpoint {
0211 };
0212 };
0213 };
0214 };
0215
0216 dsi1_phy: dsi-phy@c996400 {
0217 compatible = "qcom,dsi-phy-14nm-660";
0218 reg = <0x0c996400 0x100>,
0219 <0x0c996500 0x300>,
0220 <0x0c996800 0x188>;
0221 reg-names = "dsi_phy",
0222 "dsi_phy_lane",
0223 "dsi_pll";
0224
0225 #clock-cells = <1>;
0226 #phy-cells = <0>;
0227
0228 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
0229 clock-names = "iface", "ref";
0230 status = "disabled";
0231 };
0232 };
0233
0234 &mmcc {
0235 compatible = "qcom,mmcc-sdm660";
0236 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
0237 <&sleep_clk>,
0238 <&gcc GCC_MMSS_GPLL0_CLK>,
0239 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
0240 <&dsi0_phy 1>,
0241 <&dsi0_phy 0>,
0242 <&dsi1_phy 1>,
0243 <&dsi1_phy 0>,
0244 <0>,
0245 <0>;
0246 };
0247
0248 &tlmm {
0249 compatible = "qcom,sdm660-pinctrl";
0250 };
0251
0252 &tsens {
0253 #qcom,sensors = <14>;
0254 };
