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0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
0004 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
0005 */
0006
0007 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
0008 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
0009 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
0010 #include <dt-bindings/clock/qcom,rpmcc.h>
0011 #include <dt-bindings/interconnect/qcom,sdm660.h>
0012 #include <dt-bindings/power/qcom-rpmpd.h>
0013 #include <dt-bindings/gpio/gpio.h>
0014 #include <dt-bindings/interrupt-controller/arm-gic.h>
0015 #include <dt-bindings/soc/qcom,apr.h>
0016
0017 / {
0018 interrupt-parent = <&intc>;
0019
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 aliases {
0024 mmc1 = &sdhc_1;
0025 mmc2 = &sdhc_2;
0026 };
0027
0028 chosen { };
0029
0030 clocks {
0031 xo_board: xo-board {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <19200000>;
0035 clock-output-names = "xo_board";
0036 };
0037
0038 sleep_clk: sleep-clk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 clock-frequency = <32764>;
0042 clock-output-names = "sleep_clk";
0043 };
0044 };
0045
0046 cpus {
0047 #address-cells = <2>;
0048 #size-cells = <0>;
0049
0050 CPU0: cpu@100 {
0051 device_type = "cpu";
0052 compatible = "arm,cortex-a53";
0053 reg = <0x0 0x100>;
0054 enable-method = "psci";
0055 cpu-idle-states = <&PERF_CPU_SLEEP_0
0056 &PERF_CPU_SLEEP_1
0057 &PERF_CLUSTER_SLEEP_0
0058 &PERF_CLUSTER_SLEEP_1
0059 &PERF_CLUSTER_SLEEP_2>;
0060 capacity-dmips-mhz = <1126>;
0061 #cooling-cells = <2>;
0062 next-level-cache = <&L2_1>;
0063 L2_1: l2-cache {
0064 compatible = "cache";
0065 cache-level = <2>;
0066 };
0067 };
0068
0069 CPU1: cpu@101 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a53";
0072 reg = <0x0 0x101>;
0073 enable-method = "psci";
0074 cpu-idle-states = <&PERF_CPU_SLEEP_0
0075 &PERF_CPU_SLEEP_1
0076 &PERF_CLUSTER_SLEEP_0
0077 &PERF_CLUSTER_SLEEP_1
0078 &PERF_CLUSTER_SLEEP_2>;
0079 capacity-dmips-mhz = <1126>;
0080 #cooling-cells = <2>;
0081 next-level-cache = <&L2_1>;
0082 };
0083
0084 CPU2: cpu@102 {
0085 device_type = "cpu";
0086 compatible = "arm,cortex-a53";
0087 reg = <0x0 0x102>;
0088 enable-method = "psci";
0089 cpu-idle-states = <&PERF_CPU_SLEEP_0
0090 &PERF_CPU_SLEEP_1
0091 &PERF_CLUSTER_SLEEP_0
0092 &PERF_CLUSTER_SLEEP_1
0093 &PERF_CLUSTER_SLEEP_2>;
0094 capacity-dmips-mhz = <1126>;
0095 #cooling-cells = <2>;
0096 next-level-cache = <&L2_1>;
0097 };
0098
0099 CPU3: cpu@103 {
0100 device_type = "cpu";
0101 compatible = "arm,cortex-a53";
0102 reg = <0x0 0x103>;
0103 enable-method = "psci";
0104 cpu-idle-states = <&PERF_CPU_SLEEP_0
0105 &PERF_CPU_SLEEP_1
0106 &PERF_CLUSTER_SLEEP_0
0107 &PERF_CLUSTER_SLEEP_1
0108 &PERF_CLUSTER_SLEEP_2>;
0109 capacity-dmips-mhz = <1126>;
0110 #cooling-cells = <2>;
0111 next-level-cache = <&L2_1>;
0112 };
0113
0114 CPU4: cpu@0 {
0115 device_type = "cpu";
0116 compatible = "arm,cortex-a53";
0117 reg = <0x0 0x0>;
0118 enable-method = "psci";
0119 cpu-idle-states = <&PWR_CPU_SLEEP_0
0120 &PWR_CPU_SLEEP_1
0121 &PWR_CLUSTER_SLEEP_0
0122 &PWR_CLUSTER_SLEEP_1
0123 &PWR_CLUSTER_SLEEP_2>;
0124 capacity-dmips-mhz = <1024>;
0125 #cooling-cells = <2>;
0126 next-level-cache = <&L2_0>;
0127 L2_0: l2-cache {
0128 compatible = "cache";
0129 cache-level = <2>;
0130 };
0131 };
0132
0133 CPU5: cpu@1 {
0134 device_type = "cpu";
0135 compatible = "arm,cortex-a53";
0136 reg = <0x0 0x1>;
0137 enable-method = "psci";
0138 cpu-idle-states = <&PWR_CPU_SLEEP_0
0139 &PWR_CPU_SLEEP_1
0140 &PWR_CLUSTER_SLEEP_0
0141 &PWR_CLUSTER_SLEEP_1
0142 &PWR_CLUSTER_SLEEP_2>;
0143 capacity-dmips-mhz = <1024>;
0144 #cooling-cells = <2>;
0145 next-level-cache = <&L2_0>;
0146 };
0147
0148 CPU6: cpu@2 {
0149 device_type = "cpu";
0150 compatible = "arm,cortex-a53";
0151 reg = <0x0 0x2>;
0152 enable-method = "psci";
0153 cpu-idle-states = <&PWR_CPU_SLEEP_0
0154 &PWR_CPU_SLEEP_1
0155 &PWR_CLUSTER_SLEEP_0
0156 &PWR_CLUSTER_SLEEP_1
0157 &PWR_CLUSTER_SLEEP_2>;
0158 capacity-dmips-mhz = <1024>;
0159 #cooling-cells = <2>;
0160 next-level-cache = <&L2_0>;
0161 };
0162
0163 CPU7: cpu@3 {
0164 device_type = "cpu";
0165 compatible = "arm,cortex-a53";
0166 reg = <0x0 0x3>;
0167 enable-method = "psci";
0168 cpu-idle-states = <&PWR_CPU_SLEEP_0
0169 &PWR_CPU_SLEEP_1
0170 &PWR_CLUSTER_SLEEP_0
0171 &PWR_CLUSTER_SLEEP_1
0172 &PWR_CLUSTER_SLEEP_2>;
0173 capacity-dmips-mhz = <1024>;
0174 #cooling-cells = <2>;
0175 next-level-cache = <&L2_0>;
0176 };
0177
0178 cpu-map {
0179 cluster0 {
0180 core0 {
0181 cpu = <&CPU4>;
0182 };
0183
0184 core1 {
0185 cpu = <&CPU5>;
0186 };
0187
0188 core2 {
0189 cpu = <&CPU6>;
0190 };
0191
0192 core3 {
0193 cpu = <&CPU7>;
0194 };
0195 };
0196
0197 cluster1 {
0198 core0 {
0199 cpu = <&CPU0>;
0200 };
0201
0202 core1 {
0203 cpu = <&CPU1>;
0204 };
0205
0206 core2 {
0207 cpu = <&CPU2>;
0208 };
0209
0210 core3 {
0211 cpu = <&CPU3>;
0212 };
0213 };
0214 };
0215
0216 idle-states {
0217 entry-method = "psci";
0218
0219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
0220 compatible = "arm,idle-state";
0221 idle-state-name = "pwr-retention";
0222 arm,psci-suspend-param = <0x40000002>;
0223 entry-latency-us = <338>;
0224 exit-latency-us = <423>;
0225 min-residency-us = <200>;
0226 };
0227
0228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
0229 compatible = "arm,idle-state";
0230 idle-state-name = "pwr-power-collapse";
0231 arm,psci-suspend-param = <0x40000003>;
0232 entry-latency-us = <515>;
0233 exit-latency-us = <1821>;
0234 min-residency-us = <1000>;
0235 local-timer-stop;
0236 };
0237
0238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
0239 compatible = "arm,idle-state";
0240 idle-state-name = "perf-retention";
0241 arm,psci-suspend-param = <0x40000002>;
0242 entry-latency-us = <154>;
0243 exit-latency-us = <87>;
0244 min-residency-us = <200>;
0245 };
0246
0247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
0248 compatible = "arm,idle-state";
0249 idle-state-name = "perf-power-collapse";
0250 arm,psci-suspend-param = <0x40000003>;
0251 entry-latency-us = <262>;
0252 exit-latency-us = <301>;
0253 min-residency-us = <1000>;
0254 local-timer-stop;
0255 };
0256
0257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
0258 compatible = "arm,idle-state";
0259 idle-state-name = "pwr-cluster-dynamic-retention";
0260 arm,psci-suspend-param = <0x400000F2>;
0261 entry-latency-us = <284>;
0262 exit-latency-us = <384>;
0263 min-residency-us = <9987>;
0264 local-timer-stop;
0265 };
0266
0267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
0268 compatible = "arm,idle-state";
0269 idle-state-name = "pwr-cluster-retention";
0270 arm,psci-suspend-param = <0x400000F3>;
0271 entry-latency-us = <338>;
0272 exit-latency-us = <423>;
0273 min-residency-us = <9987>;
0274 local-timer-stop;
0275 };
0276
0277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
0278 compatible = "arm,idle-state";
0279 idle-state-name = "pwr-cluster-retention";
0280 arm,psci-suspend-param = <0x400000F4>;
0281 entry-latency-us = <515>;
0282 exit-latency-us = <1821>;
0283 min-residency-us = <9987>;
0284 local-timer-stop;
0285 };
0286
0287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
0288 compatible = "arm,idle-state";
0289 idle-state-name = "perf-cluster-dynamic-retention";
0290 arm,psci-suspend-param = <0x400000F2>;
0291 entry-latency-us = <272>;
0292 exit-latency-us = <329>;
0293 min-residency-us = <9987>;
0294 local-timer-stop;
0295 };
0296
0297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
0298 compatible = "arm,idle-state";
0299 idle-state-name = "perf-cluster-retention";
0300 arm,psci-suspend-param = <0x400000F3>;
0301 entry-latency-us = <332>;
0302 exit-latency-us = <368>;
0303 min-residency-us = <9987>;
0304 local-timer-stop;
0305 };
0306
0307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
0308 compatible = "arm,idle-state";
0309 idle-state-name = "perf-cluster-retention";
0310 arm,psci-suspend-param = <0x400000F4>;
0311 entry-latency-us = <545>;
0312 exit-latency-us = <1609>;
0313 min-residency-us = <9987>;
0314 local-timer-stop;
0315 };
0316 };
0317 };
0318
0319 firmware {
0320 scm {
0321 compatible = "qcom,scm-msm8998", "qcom,scm";
0322 };
0323 };
0324
0325 memory@80000000 {
0326 device_type = "memory";
0327 /* We expect the bootloader to fill in the reg */
0328 reg = <0x0 0x80000000 0x0 0x0>;
0329 };
0330
0331 pmu {
0332 compatible = "arm,armv8-pmuv3";
0333 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
0334 };
0335
0336 psci {
0337 compatible = "arm,psci-1.0";
0338 method = "smc";
0339 };
0340
0341 reserved-memory {
0342 #address-cells = <2>;
0343 #size-cells = <2>;
0344 ranges;
0345
0346 wlan_msa_guard: wlan-msa-guard@85600000 {
0347 reg = <0x0 0x85600000 0x0 0x100000>;
0348 no-map;
0349 };
0350
0351 wlan_msa_mem: wlan-msa-mem@85700000 {
0352 reg = <0x0 0x85700000 0x0 0x100000>;
0353 no-map;
0354 };
0355
0356 qhee_code: qhee-code@85800000 {
0357 reg = <0x0 0x85800000 0x0 0x600000>;
0358 no-map;
0359 };
0360
0361 rmtfs_mem: memory@85e00000 {
0362 compatible = "qcom,rmtfs-mem";
0363 reg = <0x0 0x85e00000 0x0 0x200000>;
0364 no-map;
0365
0366 qcom,client-id = <1>;
0367 qcom,vmid = <15>;
0368 };
0369
0370 smem_region: smem-mem@86000000 {
0371 reg = <0 0x86000000 0 0x200000>;
0372 no-map;
0373 };
0374
0375 tz_mem: memory@86200000 {
0376 reg = <0x0 0x86200000 0x0 0x3300000>;
0377 no-map;
0378 };
0379
0380 mpss_region: mpss@8ac00000 {
0381 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
0382 no-map;
0383 };
0384
0385 adsp_region: adsp@92a00000 {
0386 reg = <0x0 0x92a00000 0x0 0x1e00000>;
0387 no-map;
0388 };
0389
0390 mba_region: mba@94800000 {
0391 reg = <0x0 0x94800000 0x0 0x200000>;
0392 no-map;
0393 };
0394
0395 buffer_mem: tzbuffer@94a00000 {
0396 reg = <0x0 0x94a00000 0x0 0x100000>;
0397 no-map;
0398 };
0399
0400 venus_region: venus@9f800000 {
0401 reg = <0x0 0x9f800000 0x0 0x800000>;
0402 no-map;
0403 };
0404
0405 adsp_mem: adsp-region@f6000000 {
0406 reg = <0x0 0xf6000000 0x0 0x800000>;
0407 no-map;
0408 };
0409
0410 qseecom_mem: qseecom-region@f6800000 {
0411 reg = <0x0 0xf6800000 0x0 0x1400000>;
0412 no-map;
0413 };
0414
0415 zap_shader_region: gpu@fed00000 {
0416 compatible = "shared-dma-pool";
0417 reg = <0x0 0xfed00000 0x0 0xa00000>;
0418 no-map;
0419 };
0420 };
0421
0422 rpm-glink {
0423 compatible = "qcom,glink-rpm";
0424
0425 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0426 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0427 mboxes = <&apcs_glb 0>;
0428
0429 rpm_requests: rpm-requests {
0430 compatible = "qcom,rpm-sdm660";
0431 qcom,glink-channels = "rpm_requests";
0432
0433 rpmcc: clock-controller {
0434 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
0435 #clock-cells = <1>;
0436 };
0437
0438 rpmpd: power-controller {
0439 compatible = "qcom,sdm660-rpmpd";
0440 #power-domain-cells = <1>;
0441 operating-points-v2 = <&rpmpd_opp_table>;
0442
0443 rpmpd_opp_table: opp-table {
0444 compatible = "operating-points-v2";
0445
0446 rpmpd_opp_ret: opp1 {
0447 opp-level = <RPM_SMD_LEVEL_RETENTION>;
0448 };
0449
0450 rpmpd_opp_ret_plus: opp2 {
0451 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
0452 };
0453
0454 rpmpd_opp_min_svs: opp3 {
0455 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
0456 };
0457
0458 rpmpd_opp_low_svs: opp4 {
0459 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
0460 };
0461
0462 rpmpd_opp_svs: opp5 {
0463 opp-level = <RPM_SMD_LEVEL_SVS>;
0464 };
0465
0466 rpmpd_opp_svs_plus: opp6 {
0467 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
0468 };
0469
0470 rpmpd_opp_nom: opp7 {
0471 opp-level = <RPM_SMD_LEVEL_NOM>;
0472 };
0473
0474 rpmpd_opp_nom_plus: opp8 {
0475 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
0476 };
0477
0478 rpmpd_opp_turbo: opp9 {
0479 opp-level = <RPM_SMD_LEVEL_TURBO>;
0480 };
0481 };
0482 };
0483 };
0484 };
0485
0486 smem: smem {
0487 compatible = "qcom,smem";
0488 memory-region = <&smem_region>;
0489 hwlocks = <&tcsr_mutex 3>;
0490 };
0491
0492 smp2p-adsp {
0493 compatible = "qcom,smp2p";
0494 qcom,smem = <443>, <429>;
0495 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
0496 mboxes = <&apcs_glb 10>;
0497 qcom,local-pid = <0>;
0498 qcom,remote-pid = <2>;
0499
0500 adsp_smp2p_out: master-kernel {
0501 qcom,entry-name = "master-kernel";
0502 #qcom,smem-state-cells = <1>;
0503 };
0504
0505 adsp_smp2p_in: slave-kernel {
0506 qcom,entry-name = "slave-kernel";
0507 interrupt-controller;
0508 #interrupt-cells = <2>;
0509 };
0510 };
0511
0512 smp2p-mpss {
0513 compatible = "qcom,smp2p";
0514 qcom,smem = <435>, <428>;
0515 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
0516 mboxes = <&apcs_glb 14>;
0517 qcom,local-pid = <0>;
0518 qcom,remote-pid = <1>;
0519
0520 modem_smp2p_out: master-kernel {
0521 qcom,entry-name = "master-kernel";
0522 #qcom,smem-state-cells = <1>;
0523 };
0524
0525 modem_smp2p_in: slave-kernel {
0526 qcom,entry-name = "slave-kernel";
0527 interrupt-controller;
0528 #interrupt-cells = <2>;
0529 };
0530 };
0531
0532 soc {
0533 #address-cells = <1>;
0534 #size-cells = <1>;
0535 ranges = <0 0 0 0xffffffff>;
0536 compatible = "simple-bus";
0537
0538 gcc: clock-controller@100000 {
0539 compatible = "qcom,gcc-sdm630";
0540 #clock-cells = <1>;
0541 #reset-cells = <1>;
0542 #power-domain-cells = <1>;
0543 reg = <0x00100000 0x94000>;
0544
0545 clock-names = "xo", "sleep_clk";
0546 clocks = <&xo_board>,
0547 <&sleep_clk>;
0548 };
0549
0550 rpm_msg_ram: sram@778000 {
0551 compatible = "qcom,rpm-msg-ram";
0552 reg = <0x00778000 0x7000>;
0553 };
0554
0555 qfprom: qfprom@780000 {
0556 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
0557 reg = <0x00780000 0x621c>;
0558 #address-cells = <1>;
0559 #size-cells = <1>;
0560
0561 qusb2_hstx_trim: hstx-trim@240 {
0562 reg = <0x243 0x1>;
0563 bits = <1 3>;
0564 };
0565
0566 gpu_speed_bin: gpu-speed-bin@41a0 {
0567 reg = <0x41a2 0x1>;
0568 bits = <5 7>;
0569 };
0570 };
0571
0572 rng: rng@793000 {
0573 compatible = "qcom,prng-ee";
0574 reg = <0x00793000 0x1000>;
0575 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0576 clock-names = "core";
0577 };
0578
0579 bimc: interconnect@1008000 {
0580 compatible = "qcom,sdm660-bimc";
0581 reg = <0x01008000 0x78000>;
0582 #interconnect-cells = <1>;
0583 clock-names = "bus", "bus_a";
0584 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
0585 <&rpmcc RPM_SMD_BIMC_A_CLK>;
0586 };
0587
0588 restart@10ac000 {
0589 compatible = "qcom,pshold";
0590 reg = <0x010ac000 0x4>;
0591 };
0592
0593 cnoc: interconnect@1500000 {
0594 compatible = "qcom,sdm660-cnoc";
0595 reg = <0x01500000 0x10000>;
0596 #interconnect-cells = <1>;
0597 clock-names = "bus", "bus_a";
0598 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
0599 <&rpmcc RPM_SMD_CNOC_A_CLK>;
0600 };
0601
0602 snoc: interconnect@1626000 {
0603 compatible = "qcom,sdm660-snoc";
0604 reg = <0x01626000 0x7090>;
0605 #interconnect-cells = <1>;
0606 clock-names = "bus", "bus_a";
0607 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
0608 <&rpmcc RPM_SMD_SNOC_A_CLK>;
0609 };
0610
0611 anoc2_smmu: iommu@16c0000 {
0612 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
0613 reg = <0x016c0000 0x40000>;
0614
0615 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
0616 assigned-clock-rates = <1000>;
0617 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
0618 clock-names = "bus";
0619 #global-interrupts = <2>;
0620 #iommu-cells = <1>;
0621
0622 interrupts =
0623 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
0624 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
0625
0626 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
0627 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
0628 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
0629 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
0630 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
0631 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
0632 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
0633 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
0634 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
0635 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
0636 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
0637 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
0638 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
0639 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
0640 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
0641 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
0642 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
0643 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
0644 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
0645 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
0646 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
0647 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
0648 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
0649 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
0650 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
0651 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
0652 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
0653 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
0654 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
0655
0656 status = "disabled";
0657 };
0658
0659 a2noc: interconnect@1704000 {
0660 compatible = "qcom,sdm660-a2noc";
0661 reg = <0x01704000 0xc100>;
0662 #interconnect-cells = <1>;
0663 clock-names = "bus",
0664 "bus_a",
0665 "ipa",
0666 "ufs_axi",
0667 "aggre2_ufs_axi",
0668 "aggre2_usb3_axi",
0669 "cfg_noc_usb2_axi";
0670 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
0671 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
0672 <&rpmcc RPM_SMD_IPA_CLK>,
0673 <&gcc GCC_UFS_AXI_CLK>,
0674 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
0675 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
0676 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
0677 };
0678
0679 mnoc: interconnect@1745000 {
0680 compatible = "qcom,sdm660-mnoc";
0681 reg = <0x01745000 0xA010>;
0682 #interconnect-cells = <1>;
0683 clock-names = "bus", "bus_a", "iface";
0684 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
0685 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
0686 <&mmcc AHB_CLK_SRC>;
0687 };
0688
0689 tsens: thermal-sensor@10ae000 {
0690 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
0691 reg = <0x010ae000 0x1000>, /* TM */
0692 <0x010ad000 0x1000>; /* SROT */
0693 #qcom,sensors = <12>;
0694 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0695 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
0696 interrupt-names = "uplow", "critical";
0697 #thermal-sensor-cells = <1>;
0698 };
0699
0700 tcsr_mutex_regs: syscon@1f40000 {
0701 compatible = "syscon";
0702 reg = <0x01f40000 0x40000>;
0703 };
0704
0705 tlmm: pinctrl@3100000 {
0706 compatible = "qcom,sdm630-pinctrl";
0707 reg = <0x03100000 0x400000>,
0708 <0x03500000 0x400000>,
0709 <0x03900000 0x400000>;
0710 reg-names = "south", "center", "north";
0711 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0712 gpio-controller;
0713 gpio-ranges = <&tlmm 0 0 114>;
0714 #gpio-cells = <2>;
0715 interrupt-controller;
0716 #interrupt-cells = <2>;
0717
0718 blsp1_uart1_default: blsp1-uart1-default {
0719 pins = "gpio0", "gpio1", "gpio2", "gpio3";
0720 drive-strength = <2>;
0721 bias-disable;
0722 };
0723
0724 blsp1_uart1_sleep: blsp1-uart1-sleep {
0725 pins = "gpio0", "gpio1", "gpio2", "gpio3";
0726 drive-strength = <2>;
0727 bias-disable;
0728 };
0729
0730 blsp1_uart2_default: blsp1-uart2-default {
0731 pins = "gpio4", "gpio5";
0732 drive-strength = <2>;
0733 bias-disable;
0734 };
0735
0736 blsp2_uart1_default: blsp2-uart1-active {
0737 tx-rts {
0738 pins = "gpio16", "gpio19";
0739 function = "blsp_uart5";
0740 drive-strength = <2>;
0741 bias-disable;
0742 };
0743
0744 rx {
0745 /*
0746 * Avoid garbage data while BT module
0747 * is powered off or not driving signal
0748 */
0749 pins = "gpio17";
0750 function = "blsp_uart5";
0751 drive-strength = <2>;
0752 bias-pull-up;
0753 };
0754
0755 cts {
0756 /* Match the pull of the BT module */
0757 pins = "gpio18";
0758 function = "blsp_uart5";
0759 drive-strength = <2>;
0760 bias-pull-down;
0761 };
0762 };
0763
0764 blsp2_uart1_sleep: blsp2-uart1-sleep {
0765 tx {
0766 pins = "gpio16";
0767 function = "gpio";
0768 drive-strength = <2>;
0769 bias-pull-up;
0770 };
0771
0772 rx-cts-rts {
0773 pins = "gpio17", "gpio18", "gpio19";
0774 function = "gpio";
0775 drive-strength = <2>;
0776 bias-no-pull;
0777 };
0778 };
0779
0780 i2c1_default: i2c1-default {
0781 pins = "gpio2", "gpio3";
0782 function = "blsp_i2c1";
0783 drive-strength = <2>;
0784 bias-disable;
0785 };
0786
0787 i2c1_sleep: i2c1-sleep {
0788 pins = "gpio2", "gpio3";
0789 function = "blsp_i2c1";
0790 drive-strength = <2>;
0791 bias-pull-up;
0792 };
0793
0794 i2c2_default: i2c2-default {
0795 pins = "gpio6", "gpio7";
0796 function = "blsp_i2c2";
0797 drive-strength = <2>;
0798 bias-disable;
0799 };
0800
0801 i2c2_sleep: i2c2-sleep {
0802 pins = "gpio6", "gpio7";
0803 function = "blsp_i2c2";
0804 drive-strength = <2>;
0805 bias-pull-up;
0806 };
0807
0808 i2c3_default: i2c3-default {
0809 pins = "gpio10", "gpio11";
0810 function = "blsp_i2c3";
0811 drive-strength = <2>;
0812 bias-disable;
0813 };
0814
0815 i2c3_sleep: i2c3-sleep {
0816 pins = "gpio10", "gpio11";
0817 function = "blsp_i2c3";
0818 drive-strength = <2>;
0819 bias-pull-up;
0820 };
0821
0822 i2c4_default: i2c4-default {
0823 pins = "gpio14", "gpio15";
0824 function = "blsp_i2c4";
0825 drive-strength = <2>;
0826 bias-disable;
0827 };
0828
0829 i2c4_sleep: i2c4-sleep {
0830 pins = "gpio14", "gpio15";
0831 function = "blsp_i2c4";
0832 drive-strength = <2>;
0833 bias-pull-up;
0834 };
0835
0836 i2c5_default: i2c5-default {
0837 pins = "gpio18", "gpio19";
0838 function = "blsp_i2c5";
0839 drive-strength = <2>;
0840 bias-disable;
0841 };
0842
0843 i2c5_sleep: i2c5-sleep {
0844 pins = "gpio18", "gpio19";
0845 function = "blsp_i2c5";
0846 drive-strength = <2>;
0847 bias-pull-up;
0848 };
0849
0850 i2c6_default: i2c6-default {
0851 pins = "gpio22", "gpio23";
0852 function = "blsp_i2c6";
0853 drive-strength = <2>;
0854 bias-disable;
0855 };
0856
0857 i2c6_sleep: i2c6-sleep {
0858 pins = "gpio22", "gpio23";
0859 function = "blsp_i2c6";
0860 drive-strength = <2>;
0861 bias-pull-up;
0862 };
0863
0864 i2c7_default: i2c7-default {
0865 pins = "gpio26", "gpio27";
0866 function = "blsp_i2c7";
0867 drive-strength = <2>;
0868 bias-disable;
0869 };
0870
0871 i2c7_sleep: i2c7-sleep {
0872 pins = "gpio26", "gpio27";
0873 function = "blsp_i2c7";
0874 drive-strength = <2>;
0875 bias-pull-up;
0876 };
0877
0878 i2c8_default: i2c8-default {
0879 pins = "gpio30", "gpio31";
0880 function = "blsp_i2c8";
0881 drive-strength = <2>;
0882 bias-disable;
0883 };
0884
0885 i2c8_sleep: i2c8-sleep {
0886 pins = "gpio30", "gpio31";
0887 function = "blsp_i2c8";
0888 drive-strength = <2>;
0889 bias-pull-up;
0890 };
0891
0892 cci0_default: cci0_default {
0893 pinmux {
0894 pins = "gpio36","gpio37";
0895 function = "cci_i2c";
0896 };
0897
0898 pinconf {
0899 pins = "gpio36","gpio37";
0900 bias-pull-up;
0901 drive-strength = <2>;
0902 };
0903 };
0904
0905 cci1_default: cci1_default {
0906 pinmux {
0907 pins = "gpio38","gpio39";
0908 function = "cci_i2c";
0909 };
0910
0911 pinconf {
0912 pins = "gpio38","gpio39";
0913 bias-pull-up;
0914 drive-strength = <2>;
0915 };
0916 };
0917
0918 sdc1_state_on: sdc1-on {
0919 clk {
0920 pins = "sdc1_clk";
0921 bias-disable;
0922 drive-strength = <16>;
0923 };
0924
0925 cmd {
0926 pins = "sdc1_cmd";
0927 bias-pull-up;
0928 drive-strength = <10>;
0929 };
0930
0931 data {
0932 pins = "sdc1_data";
0933 bias-pull-up;
0934 drive-strength = <10>;
0935 };
0936
0937 rclk {
0938 pins = "sdc1_rclk";
0939 bias-pull-down;
0940 };
0941 };
0942
0943 sdc1_state_off: sdc1-off {
0944 clk {
0945 pins = "sdc1_clk";
0946 bias-disable;
0947 drive-strength = <2>;
0948 };
0949
0950 cmd {
0951 pins = "sdc1_cmd";
0952 bias-pull-up;
0953 drive-strength = <2>;
0954 };
0955
0956 data {
0957 pins = "sdc1_data";
0958 bias-pull-up;
0959 drive-strength = <2>;
0960 };
0961
0962 rclk {
0963 pins = "sdc1_rclk";
0964 bias-pull-down;
0965 };
0966 };
0967
0968 sdc2_state_on: sdc2-on {
0969 clk {
0970 pins = "sdc2_clk";
0971 bias-disable;
0972 drive-strength = <16>;
0973 };
0974
0975 cmd {
0976 pins = "sdc2_cmd";
0977 bias-pull-up;
0978 drive-strength = <10>;
0979 };
0980
0981 data {
0982 pins = "sdc2_data";
0983 bias-pull-up;
0984 drive-strength = <10>;
0985 };
0986 };
0987
0988 sdc2_state_off: sdc2-off {
0989 clk {
0990 pins = "sdc2_clk";
0991 bias-disable;
0992 drive-strength = <2>;
0993 };
0994
0995 cmd {
0996 pins = "sdc2_cmd";
0997 bias-pull-up;
0998 drive-strength = <2>;
0999 };
1000
1001 data {
1002 pins = "sdc2_data";
1003 bias-pull-up;
1004 drive-strength = <2>;
1005 };
1006 };
1007 };
1008
1009 adreno_gpu: gpu@5000000 {
1010 compatible = "qcom,adreno-508.0", "qcom,adreno";
1011
1012 reg = <0x05000000 0x40000>;
1013 reg-names = "kgsl_3d0_reg_memory";
1014
1015 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1016
1017 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1018 <&gpucc GPUCC_RBBMTIMER_CLK>,
1019 <&gcc GCC_BIMC_GFX_CLK>,
1020 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1021 <&gpucc GPUCC_RBCPR_CLK>,
1022 <&gpucc GPUCC_GFX3D_CLK>;
1023
1024 clock-names = "iface",
1025 "rbbmtimer",
1026 "mem",
1027 "mem_iface",
1028 "rbcpr",
1029 "core";
1030
1031 power-domains = <&rpmpd SDM660_VDDMX>;
1032 iommus = <&kgsl_smmu 0>;
1033
1034 nvmem-cells = <&gpu_speed_bin>;
1035 nvmem-cell-names = "speed_bin";
1036
1037 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1038 interconnect-names = "gfx-mem";
1039
1040 operating-points-v2 = <&gpu_sdm630_opp_table>;
1041
1042 status = "disabled";
1043
1044 gpu_sdm630_opp_table: opp-table {
1045 compatible = "operating-points-v2";
1046 opp-775000000 {
1047 opp-hz = /bits/ 64 <775000000>;
1048 opp-level = <RPM_SMD_LEVEL_TURBO>;
1049 opp-peak-kBps = <5412000>;
1050 opp-supported-hw = <0xA2>;
1051 };
1052 opp-647000000 {
1053 opp-hz = /bits/ 64 <647000000>;
1054 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1055 opp-peak-kBps = <4068000>;
1056 opp-supported-hw = <0xFF>;
1057 };
1058 opp-588000000 {
1059 opp-hz = /bits/ 64 <588000000>;
1060 opp-level = <RPM_SMD_LEVEL_NOM>;
1061 opp-peak-kBps = <3072000>;
1062 opp-supported-hw = <0xFF>;
1063 };
1064 opp-465000000 {
1065 opp-hz = /bits/ 64 <465000000>;
1066 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1067 opp-peak-kBps = <2724000>;
1068 opp-supported-hw = <0xFF>;
1069 };
1070 opp-370000000 {
1071 opp-hz = /bits/ 64 <370000000>;
1072 opp-level = <RPM_SMD_LEVEL_SVS>;
1073 opp-peak-kBps = <2188000>;
1074 opp-supported-hw = <0xFF>;
1075 };
1076 opp-240000000 {
1077 opp-hz = /bits/ 64 <240000000>;
1078 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1079 opp-peak-kBps = <1648000>;
1080 opp-supported-hw = <0xFF>;
1081 };
1082 opp-160000000 {
1083 opp-hz = /bits/ 64 <160000000>;
1084 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1085 opp-peak-kBps = <1200000>;
1086 opp-supported-hw = <0xFF>;
1087 };
1088 };
1089 };
1090
1091 kgsl_smmu: iommu@5040000 {
1092 compatible = "qcom,sdm630-smmu-v2",
1093 "qcom,adreno-smmu", "qcom,smmu-v2";
1094 reg = <0x05040000 0x10000>;
1095
1096 /*
1097 * GX GDSC parent is CX. We need to bring up CX for SMMU
1098 * but we need both up for Adreno. On the other hand, we
1099 * need to manage the GX rpmpd domain in the adreno driver.
1100 * Enable CX/GX GDSCs here so that we can manage just the GX
1101 * RPM Power Domain in the Adreno driver.
1102 */
1103 power-domains = <&gpucc GPU_GX_GDSC>;
1104 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1105 <&gcc GCC_BIMC_GFX_CLK>,
1106 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1107 clock-names = "iface", "mem", "mem_iface";
1108 #global-interrupts = <2>;
1109 #iommu-cells = <1>;
1110
1111 interrupts =
1112 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1114
1115 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1118 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1119 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1120 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1121 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1123
1124 status = "disabled";
1125 };
1126
1127 gpucc: clock-controller@5065000 {
1128 compatible = "qcom,gpucc-sdm630";
1129 #clock-cells = <1>;
1130 #reset-cells = <1>;
1131 #power-domain-cells = <1>;
1132 reg = <0x05065000 0x9038>;
1133
1134 clocks = <&xo_board>,
1135 <&gcc GCC_GPU_GPLL0_CLK>,
1136 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1137 clock-names = "xo",
1138 "gcc_gpu_gpll0_clk",
1139 "gcc_gpu_gpll0_div_clk";
1140 status = "disabled";
1141 };
1142
1143 lpass_smmu: iommu@5100000 {
1144 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1145 reg = <0x05100000 0x40000>;
1146 #iommu-cells = <1>;
1147
1148 #global-interrupts = <2>;
1149 interrupts =
1150 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1152
1153 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1170
1171 status = "disabled";
1172 };
1173
1174 sram@290000 {
1175 compatible = "qcom,rpm-stats";
1176 reg = <0x00290000 0x10000>;
1177 };
1178
1179 spmi_bus: spmi@800f000 {
1180 compatible = "qcom,spmi-pmic-arb";
1181 reg = <0x0800f000 0x1000>,
1182 <0x08400000 0x1000000>,
1183 <0x09400000 0x1000000>,
1184 <0x0a400000 0x220000>,
1185 <0x0800a000 0x3000>;
1186 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1187 interrupt-names = "periph_irq";
1188 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1189 qcom,ee = <0>;
1190 qcom,channel = <0>;
1191 #address-cells = <2>;
1192 #size-cells = <0>;
1193 interrupt-controller;
1194 #interrupt-cells = <4>;
1195 cell-index = <0>;
1196 };
1197
1198 usb3: usb@a8f8800 {
1199 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1200 reg = <0x0a8f8800 0x400>;
1201 status = "disabled";
1202 #address-cells = <1>;
1203 #size-cells = <1>;
1204 ranges;
1205
1206 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1207 <&gcc GCC_USB30_MASTER_CLK>,
1208 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1209 <&gcc GCC_USB30_SLEEP_CLK>,
1210 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1211 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1212 clock-names = "cfg_noc",
1213 "core",
1214 "iface",
1215 "sleep",
1216 "mock_utmi",
1217 "bus";
1218
1219 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1220 <&gcc GCC_USB30_MASTER_CLK>,
1221 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1222 assigned-clock-rates = <19200000>, <120000000>,
1223 <19200000>;
1224
1225 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1228
1229 power-domains = <&gcc USB_30_GDSC>;
1230 qcom,select-utmi-as-pipe-clk;
1231
1232 resets = <&gcc GCC_USB_30_BCR>;
1233
1234 usb3_dwc3: usb@a800000 {
1235 compatible = "snps,dwc3";
1236 reg = <0x0a800000 0xc8d0>;
1237 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1238 snps,dis_u2_susphy_quirk;
1239 snps,dis_enblslpm_quirk;
1240
1241 /*
1242 * SDM630 technically supports USB3 but I
1243 * haven't seen any devices making use of it.
1244 */
1245 maximum-speed = "high-speed";
1246 phys = <&qusb2phy0>;
1247 phy-names = "usb2-phy";
1248 snps,hird-threshold = /bits/ 8 <0>;
1249 };
1250 };
1251
1252 qusb2phy0: phy@c012000 {
1253 compatible = "qcom,sdm660-qusb2-phy";
1254 reg = <0x0c012000 0x180>;
1255 #phy-cells = <0>;
1256
1257 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1258 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1259 clock-names = "cfg_ahb", "ref";
1260
1261 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1262 nvmem-cells = <&qusb2_hstx_trim>;
1263 status = "disabled";
1264 };
1265
1266 qusb2phy1: phy@c014000 {
1267 compatible = "qcom,sdm660-qusb2-phy";
1268 reg = <0x0c014000 0x180>;
1269 #phy-cells = <0>;
1270
1271 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1272 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1273 clock-names = "cfg_ahb", "ref";
1274
1275 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1276 nvmem-cells = <&qusb2_hstx_trim>;
1277 status = "disabled";
1278 };
1279
1280 sdhc_2: mmc@c084000 {
1281 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1282 reg = <0x0c084000 0x1000>;
1283 reg-names = "hc";
1284
1285 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1287 interrupt-names = "hc_irq", "pwr_irq";
1288
1289 bus-width = <4>;
1290
1291 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1292 <&gcc GCC_SDCC2_APPS_CLK>,
1293 <&xo_board>;
1294 clock-names = "iface", "core", "xo";
1295
1296
1297 interconnects = <&a2noc 3 &a2noc 10>,
1298 <&gnoc 0 &cnoc 28>;
1299 interconnect-names = "sdhc-ddr","cpu-sdhc";
1300 operating-points-v2 = <&sdhc2_opp_table>;
1301
1302 pinctrl-names = "default", "sleep";
1303 pinctrl-0 = <&sdc2_state_on>;
1304 pinctrl-1 = <&sdc2_state_off>;
1305 power-domains = <&rpmpd SDM660_VDDCX>;
1306
1307 status = "disabled";
1308
1309 sdhc2_opp_table: opp-table {
1310 compatible = "operating-points-v2";
1311
1312 opp-50000000 {
1313 opp-hz = /bits/ 64 <50000000>;
1314 required-opps = <&rpmpd_opp_low_svs>;
1315 opp-peak-kBps = <200000 140000>;
1316 opp-avg-kBps = <130718 133320>;
1317 };
1318 opp-100000000 {
1319 opp-hz = /bits/ 64 <100000000>;
1320 required-opps = <&rpmpd_opp_svs>;
1321 opp-peak-kBps = <250000 160000>;
1322 opp-avg-kBps = <196078 150000>;
1323 };
1324 opp-200000000 {
1325 opp-hz = /bits/ 64 <200000000>;
1326 required-opps = <&rpmpd_opp_nom>;
1327 opp-peak-kBps = <4096000 4096000>;
1328 opp-avg-kBps = <1338562 1338562>;
1329 };
1330 };
1331 };
1332
1333 sdhc_1: mmc@c0c4000 {
1334 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1335 reg = <0x0c0c4000 0x1000>,
1336 <0x0c0c5000 0x1000>,
1337 <0x0c0c8000 0x8000>;
1338 reg-names = "hc", "cqhci", "ice";
1339
1340 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1342 interrupt-names = "hc_irq", "pwr_irq";
1343
1344 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1345 <&gcc GCC_SDCC1_APPS_CLK>,
1346 <&xo_board>,
1347 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1348 clock-names = "iface", "core", "xo", "ice";
1349
1350 interconnects = <&a2noc 2 &a2noc 10>,
1351 <&gnoc 0 &cnoc 27>;
1352 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1353 operating-points-v2 = <&sdhc1_opp_table>;
1354 pinctrl-names = "default", "sleep";
1355 pinctrl-0 = <&sdc1_state_on>;
1356 pinctrl-1 = <&sdc1_state_off>;
1357 power-domains = <&rpmpd SDM660_VDDCX>;
1358
1359 bus-width = <8>;
1360 non-removable;
1361
1362 status = "disabled";
1363
1364 sdhc1_opp_table: opp-table {
1365 compatible = "operating-points-v2";
1366
1367 opp-50000000 {
1368 opp-hz = /bits/ 64 <50000000>;
1369 required-opps = <&rpmpd_opp_low_svs>;
1370 opp-peak-kBps = <200000 140000>;
1371 opp-avg-kBps = <130718 133320>;
1372 };
1373 opp-100000000 {
1374 opp-hz = /bits/ 64 <100000000>;
1375 required-opps = <&rpmpd_opp_svs>;
1376 opp-peak-kBps = <250000 160000>;
1377 opp-avg-kBps = <196078 150000>;
1378 };
1379 opp-384000000 {
1380 opp-hz = /bits/ 64 <384000000>;
1381 required-opps = <&rpmpd_opp_nom>;
1382 opp-peak-kBps = <4096000 4096000>;
1383 opp-avg-kBps = <1338562 1338562>;
1384 };
1385 };
1386 };
1387
1388 usb2: usb@c2f8800 {
1389 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1390 reg = <0x0c2f8800 0x400>;
1391 status = "disabled";
1392 #address-cells = <1>;
1393 #size-cells = <1>;
1394 ranges;
1395
1396 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1397 <&gcc GCC_USB20_MASTER_CLK>,
1398 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1399 <&gcc GCC_USB20_SLEEP_CLK>;
1400 clock-names = "cfg_noc", "core",
1401 "mock_utmi", "sleep";
1402
1403 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1404 <&gcc GCC_USB20_MASTER_CLK>;
1405 assigned-clock-rates = <19200000>, <60000000>;
1406
1407 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1408 interrupt-names = "hs_phy_irq";
1409
1410 qcom,select-utmi-as-pipe-clk;
1411
1412 resets = <&gcc GCC_USB_20_BCR>;
1413
1414 usb2_dwc3: usb@c200000 {
1415 compatible = "snps,dwc3";
1416 reg = <0x0c200000 0xc8d0>;
1417 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1418 snps,dis_u2_susphy_quirk;
1419 snps,dis_enblslpm_quirk;
1420
1421 /* This is the HS-only host */
1422 maximum-speed = "high-speed";
1423 phys = <&qusb2phy1>;
1424 phy-names = "usb2-phy";
1425 snps,hird-threshold = /bits/ 8 <0>;
1426 };
1427 };
1428
1429 mmcc: clock-controller@c8c0000 {
1430 compatible = "qcom,mmcc-sdm630";
1431 reg = <0x0c8c0000 0x40000>;
1432 #clock-cells = <1>;
1433 #reset-cells = <1>;
1434 #power-domain-cells = <1>;
1435 clock-names = "xo",
1436 "sleep_clk",
1437 "gpll0",
1438 "gpll0_div",
1439 "dsi0pll",
1440 "dsi0pllbyte",
1441 "dsi1pll",
1442 "dsi1pllbyte",
1443 "dp_link_2x_clk_divsel_five",
1444 "dp_vco_divided_clk_src_mux";
1445 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1446 <&sleep_clk>,
1447 <&gcc GCC_MMSS_GPLL0_CLK>,
1448 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1449 <&dsi0_phy 1>,
1450 <&dsi0_phy 0>,
1451 <0>,
1452 <0>,
1453 <0>,
1454 <0>;
1455 };
1456
1457 dsi_opp_table: opp-table-dsi {
1458 compatible = "operating-points-v2";
1459
1460 opp-131250000 {
1461 opp-hz = /bits/ 64 <131250000>;
1462 required-opps = <&rpmpd_opp_svs>;
1463 };
1464
1465 opp-210000000 {
1466 opp-hz = /bits/ 64 <210000000>;
1467 required-opps = <&rpmpd_opp_svs_plus>;
1468 };
1469
1470 opp-262500000 {
1471 opp-hz = /bits/ 64 <262500000>;
1472 required-opps = <&rpmpd_opp_nom>;
1473 };
1474 };
1475
1476 mdss: mdss@c900000 {
1477 compatible = "qcom,mdss";
1478 reg = <0x0c900000 0x1000>,
1479 <0x0c9b0000 0x1040>;
1480 reg-names = "mdss_phys", "vbif_phys";
1481
1482 power-domains = <&mmcc MDSS_GDSC>;
1483
1484 clocks = <&mmcc MDSS_AHB_CLK>,
1485 <&mmcc MDSS_AXI_CLK>,
1486 <&mmcc MDSS_VSYNC_CLK>,
1487 <&mmcc MDSS_MDP_CLK>;
1488 clock-names = "iface",
1489 "bus",
1490 "vsync",
1491 "core";
1492
1493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1494
1495 interrupt-controller;
1496 #interrupt-cells = <1>;
1497
1498 #address-cells = <1>;
1499 #size-cells = <1>;
1500 ranges;
1501 status = "disabled";
1502
1503 mdp: mdp@c901000 {
1504 compatible = "qcom,mdp5";
1505 reg = <0x0c901000 0x89000>;
1506 reg-names = "mdp_phys";
1507
1508 interrupt-parent = <&mdss>;
1509 interrupts = <0>;
1510
1511 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1512 <&mmcc MDSS_VSYNC_CLK>;
1513 assigned-clock-rates = <300000000>,
1514 <19200000>;
1515 clocks = <&mmcc MDSS_AHB_CLK>,
1516 <&mmcc MDSS_AXI_CLK>,
1517 <&mmcc MDSS_MDP_CLK>,
1518 <&mmcc MDSS_VSYNC_CLK>;
1519 clock-names = "iface",
1520 "bus",
1521 "core",
1522 "vsync";
1523
1524 interconnects = <&mnoc 2 &bimc 5>,
1525 <&mnoc 3 &bimc 5>,
1526 <&gnoc 0 &mnoc 17>;
1527 interconnect-names = "mdp0-mem",
1528 "mdp1-mem",
1529 "rotator-mem";
1530 iommus = <&mmss_smmu 0>;
1531 operating-points-v2 = <&mdp_opp_table>;
1532 power-domains = <&rpmpd SDM660_VDDCX>;
1533
1534 ports {
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1537
1538 port@0 {
1539 reg = <0>;
1540 mdp5_intf1_out: endpoint {
1541 remote-endpoint = <&dsi0_in>;
1542 };
1543 };
1544 };
1545
1546 mdp_opp_table: opp-table {
1547 compatible = "operating-points-v2";
1548
1549 opp-150000000 {
1550 opp-hz = /bits/ 64 <150000000>;
1551 opp-peak-kBps = <320000 320000 76800>;
1552 required-opps = <&rpmpd_opp_low_svs>;
1553 };
1554 opp-275000000 {
1555 opp-hz = /bits/ 64 <275000000>;
1556 opp-peak-kBps = <6400000 6400000 160000>;
1557 required-opps = <&rpmpd_opp_svs>;
1558 };
1559 opp-300000000 {
1560 opp-hz = /bits/ 64 <300000000>;
1561 opp-peak-kBps = <6400000 6400000 190000>;
1562 required-opps = <&rpmpd_opp_svs_plus>;
1563 };
1564 opp-330000000 {
1565 opp-hz = /bits/ 64 <330000000>;
1566 opp-peak-kBps = <6400000 6400000 240000>;
1567 required-opps = <&rpmpd_opp_nom>;
1568 };
1569 opp-412500000 {
1570 opp-hz = /bits/ 64 <412500000>;
1571 opp-peak-kBps = <6400000 6400000 320000>;
1572 required-opps = <&rpmpd_opp_turbo>;
1573 };
1574 };
1575 };
1576
1577 dsi0: dsi@c994000 {
1578 compatible = "qcom,mdss-dsi-ctrl";
1579 reg = <0x0c994000 0x400>;
1580 reg-names = "dsi_ctrl";
1581
1582 operating-points-v2 = <&dsi_opp_table>;
1583 power-domains = <&rpmpd SDM660_VDDCX>;
1584
1585 interrupt-parent = <&mdss>;
1586 interrupts = <4>;
1587
1588 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1589 <&mmcc PCLK0_CLK_SRC>;
1590 assigned-clock-parents = <&dsi0_phy 0>,
1591 <&dsi0_phy 1>;
1592
1593 clocks = <&mmcc MDSS_MDP_CLK>,
1594 <&mmcc MDSS_BYTE0_CLK>,
1595 <&mmcc MDSS_BYTE0_INTF_CLK>,
1596 <&mmcc MNOC_AHB_CLK>,
1597 <&mmcc MDSS_AHB_CLK>,
1598 <&mmcc MDSS_AXI_CLK>,
1599 <&mmcc MISC_AHB_CLK>,
1600 <&mmcc MDSS_PCLK0_CLK>,
1601 <&mmcc MDSS_ESC0_CLK>;
1602 clock-names = "mdp_core",
1603 "byte",
1604 "byte_intf",
1605 "mnoc",
1606 "iface",
1607 "bus",
1608 "core_mmss",
1609 "pixel",
1610 "core";
1611
1612 phys = <&dsi0_phy>;
1613 phy-names = "dsi";
1614
1615 status = "disabled";
1616
1617 ports {
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1620
1621 port@0 {
1622 reg = <0>;
1623 dsi0_in: endpoint {
1624 remote-endpoint = <&mdp5_intf1_out>;
1625 };
1626 };
1627
1628 port@1 {
1629 reg = <1>;
1630 dsi0_out: endpoint {
1631 };
1632 };
1633 };
1634 };
1635
1636 dsi0_phy: dsi-phy@c994400 {
1637 compatible = "qcom,dsi-phy-14nm-660";
1638 reg = <0x0c994400 0x100>,
1639 <0x0c994500 0x300>,
1640 <0x0c994800 0x188>;
1641 reg-names = "dsi_phy",
1642 "dsi_phy_lane",
1643 "dsi_pll";
1644
1645 #clock-cells = <1>;
1646 #phy-cells = <0>;
1647
1648 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1649 clock-names = "iface", "ref";
1650 status = "disabled";
1651 };
1652 };
1653
1654 blsp1_dma: dma-controller@c144000 {
1655 compatible = "qcom,bam-v1.7.0";
1656 reg = <0x0c144000 0x1f000>;
1657 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1658 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1659 clock-names = "bam_clk";
1660 #dma-cells = <1>;
1661 qcom,ee = <0>;
1662 qcom,controlled-remotely;
1663 num-channels = <18>;
1664 qcom,num-ees = <4>;
1665 };
1666
1667 blsp1_uart1: serial@c16f000 {
1668 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1669 reg = <0x0c16f000 0x200>;
1670 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1671 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1672 <&gcc GCC_BLSP1_AHB_CLK>;
1673 clock-names = "core", "iface";
1674 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1675 dma-names = "tx", "rx";
1676 pinctrl-names = "default", "sleep";
1677 pinctrl-0 = <&blsp1_uart1_default>;
1678 pinctrl-1 = <&blsp1_uart1_sleep>;
1679 status = "disabled";
1680 };
1681
1682 blsp1_uart2: serial@c170000 {
1683 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1684 reg = <0x0c170000 0x1000>;
1685 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1686 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1687 <&gcc GCC_BLSP1_AHB_CLK>;
1688 clock-names = "core", "iface";
1689 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1690 dma-names = "tx", "rx";
1691 pinctrl-names = "default";
1692 pinctrl-0 = <&blsp1_uart2_default>;
1693 status = "disabled";
1694 };
1695
1696 blsp_i2c1: i2c@c175000 {
1697 compatible = "qcom,i2c-qup-v2.2.1";
1698 reg = <0x0c175000 0x600>;
1699 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1700
1701 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1702 <&gcc GCC_BLSP1_AHB_CLK>;
1703 clock-names = "core", "iface";
1704 clock-frequency = <400000>;
1705 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1706 dma-names = "tx", "rx";
1707
1708 pinctrl-names = "default", "sleep";
1709 pinctrl-0 = <&i2c1_default>;
1710 pinctrl-1 = <&i2c1_sleep>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1713 status = "disabled";
1714 };
1715
1716 blsp_i2c2: i2c@c176000 {
1717 compatible = "qcom,i2c-qup-v2.2.1";
1718 reg = <0x0c176000 0x600>;
1719 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1720
1721 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1722 <&gcc GCC_BLSP1_AHB_CLK>;
1723 clock-names = "core", "iface";
1724 clock-frequency = <400000>;
1725 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1726 dma-names = "tx", "rx";
1727
1728 pinctrl-names = "default", "sleep";
1729 pinctrl-0 = <&i2c2_default>;
1730 pinctrl-1 = <&i2c2_sleep>;
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1733 status = "disabled";
1734 };
1735
1736 blsp_i2c3: i2c@c177000 {
1737 compatible = "qcom,i2c-qup-v2.2.1";
1738 reg = <0x0c177000 0x600>;
1739 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1740
1741 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1742 <&gcc GCC_BLSP1_AHB_CLK>;
1743 clock-names = "core", "iface";
1744 clock-frequency = <400000>;
1745 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1746 dma-names = "tx", "rx";
1747
1748 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&i2c3_default>;
1750 pinctrl-1 = <&i2c3_sleep>;
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1753 status = "disabled";
1754 };
1755
1756 blsp_i2c4: i2c@c178000 {
1757 compatible = "qcom,i2c-qup-v2.2.1";
1758 reg = <0x0c178000 0x600>;
1759 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1760
1761 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1762 <&gcc GCC_BLSP1_AHB_CLK>;
1763 clock-names = "core", "iface";
1764 clock-frequency = <400000>;
1765 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1766 dma-names = "tx", "rx";
1767
1768 pinctrl-names = "default", "sleep";
1769 pinctrl-0 = <&i2c4_default>;
1770 pinctrl-1 = <&i2c4_sleep>;
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1773 status = "disabled";
1774 };
1775
1776 blsp2_dma: dma-controller@c184000 {
1777 compatible = "qcom,bam-v1.7.0";
1778 reg = <0x0c184000 0x1f000>;
1779 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1780 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1781 clock-names = "bam_clk";
1782 #dma-cells = <1>;
1783 qcom,ee = <0>;
1784 qcom,controlled-remotely;
1785 num-channels = <18>;
1786 qcom,num-ees = <4>;
1787 };
1788
1789 blsp2_uart1: serial@c1af000 {
1790 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1791 reg = <0x0c1af000 0x200>;
1792 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1793 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1794 <&gcc GCC_BLSP2_AHB_CLK>;
1795 clock-names = "core", "iface";
1796 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1797 dma-names = "tx", "rx";
1798 pinctrl-names = "default", "sleep";
1799 pinctrl-0 = <&blsp2_uart1_default>;
1800 pinctrl-1 = <&blsp2_uart1_sleep>;
1801 status = "disabled";
1802 };
1803
1804 blsp_i2c5: i2c@c1b5000 {
1805 compatible = "qcom,i2c-qup-v2.2.1";
1806 reg = <0x0c1b5000 0x600>;
1807 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1808
1809 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1810 <&gcc GCC_BLSP2_AHB_CLK>;
1811 clock-names = "core", "iface";
1812 clock-frequency = <400000>;
1813 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1814 dma-names = "tx", "rx";
1815
1816 pinctrl-names = "default", "sleep";
1817 pinctrl-0 = <&i2c5_default>;
1818 pinctrl-1 = <&i2c5_sleep>;
1819 #address-cells = <1>;
1820 #size-cells = <0>;
1821 status = "disabled";
1822 };
1823
1824 blsp_i2c6: i2c@c1b6000 {
1825 compatible = "qcom,i2c-qup-v2.2.1";
1826 reg = <0x0c1b6000 0x600>;
1827 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1828
1829 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1830 <&gcc GCC_BLSP2_AHB_CLK>;
1831 clock-names = "core", "iface";
1832 clock-frequency = <400000>;
1833 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1834 dma-names = "tx", "rx";
1835
1836 pinctrl-names = "default", "sleep";
1837 pinctrl-0 = <&i2c6_default>;
1838 pinctrl-1 = <&i2c6_sleep>;
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1841 status = "disabled";
1842 };
1843
1844 blsp_i2c7: i2c@c1b7000 {
1845 compatible = "qcom,i2c-qup-v2.2.1";
1846 reg = <0x0c1b7000 0x600>;
1847 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1848
1849 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1850 <&gcc GCC_BLSP2_AHB_CLK>;
1851 clock-names = "core", "iface";
1852 clock-frequency = <400000>;
1853 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1854 dma-names = "tx", "rx";
1855
1856 pinctrl-names = "default", "sleep";
1857 pinctrl-0 = <&i2c7_default>;
1858 pinctrl-1 = <&i2c7_sleep>;
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1861 status = "disabled";
1862 };
1863
1864 blsp_i2c8: i2c@c1b8000 {
1865 compatible = "qcom,i2c-qup-v2.2.1";
1866 reg = <0x0c1b8000 0x600>;
1867 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1868
1869 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1870 <&gcc GCC_BLSP2_AHB_CLK>;
1871 clock-names = "core", "iface";
1872 clock-frequency = <400000>;
1873 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1874 dma-names = "tx", "rx";
1875
1876 pinctrl-names = "default", "sleep";
1877 pinctrl-0 = <&i2c8_default>;
1878 pinctrl-1 = <&i2c8_sleep>;
1879 #address-cells = <1>;
1880 #size-cells = <0>;
1881 status = "disabled";
1882 };
1883
1884 sram@146bf000 {
1885 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1886 reg = <0x146bf000 0x1000>;
1887
1888 #address-cells = <1>;
1889 #size-cells = <1>;
1890
1891 ranges = <0 0x146bf000 0x1000>;
1892
1893 pil-reloc@94c {
1894 compatible = "qcom,pil-reloc-info";
1895 reg = <0x94c 0xc8>;
1896 };
1897 };
1898
1899 camss: camss@ca00000 {
1900 compatible = "qcom,sdm660-camss";
1901 reg = <0x0ca00020 0x10>,
1902 <0x0ca30000 0x100>,
1903 <0x0ca30400 0x100>,
1904 <0x0ca30800 0x100>,
1905 <0x0ca30c00 0x100>,
1906 <0x0c824000 0x1000>,
1907 <0x0ca00120 0x4>,
1908 <0x0c825000 0x1000>,
1909 <0x0ca00124 0x4>,
1910 <0x0c826000 0x1000>,
1911 <0x0ca00128 0x4>,
1912 <0x0ca31000 0x500>,
1913 <0x0ca10000 0x1000>,
1914 <0x0ca14000 0x1000>;
1915 reg-names = "csi_clk_mux",
1916 "csid0",
1917 "csid1",
1918 "csid2",
1919 "csid3",
1920 "csiphy0",
1921 "csiphy0_clk_mux",
1922 "csiphy1",
1923 "csiphy1_clk_mux",
1924 "csiphy2",
1925 "csiphy2_clk_mux",
1926 "ispif",
1927 "vfe0",
1928 "vfe1";
1929 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1930 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1931 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1932 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1933 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1934 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1935 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1936 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1937 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1938 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1939 interrupt-names = "csid0",
1940 "csid1",
1941 "csid2",
1942 "csid3",
1943 "csiphy0",
1944 "csiphy1",
1945 "csiphy2",
1946 "ispif",
1947 "vfe0",
1948 "vfe1";
1949 clocks = <&mmcc CAMSS_AHB_CLK>,
1950 <&mmcc CAMSS_CPHY_CSID0_CLK>,
1951 <&mmcc CAMSS_CPHY_CSID1_CLK>,
1952 <&mmcc CAMSS_CPHY_CSID2_CLK>,
1953 <&mmcc CAMSS_CPHY_CSID3_CLK>,
1954 <&mmcc CAMSS_CSI0_AHB_CLK>,
1955 <&mmcc CAMSS_CSI0_CLK>,
1956 <&mmcc CAMSS_CPHY_CSID0_CLK>,
1957 <&mmcc CAMSS_CSI0PIX_CLK>,
1958 <&mmcc CAMSS_CSI0RDI_CLK>,
1959 <&mmcc CAMSS_CSI1_AHB_CLK>,
1960 <&mmcc CAMSS_CSI1_CLK>,
1961 <&mmcc CAMSS_CPHY_CSID1_CLK>,
1962 <&mmcc CAMSS_CSI1PIX_CLK>,
1963 <&mmcc CAMSS_CSI1RDI_CLK>,
1964 <&mmcc CAMSS_CSI2_AHB_CLK>,
1965 <&mmcc CAMSS_CSI2_CLK>,
1966 <&mmcc CAMSS_CPHY_CSID2_CLK>,
1967 <&mmcc CAMSS_CSI2PIX_CLK>,
1968 <&mmcc CAMSS_CSI2RDI_CLK>,
1969 <&mmcc CAMSS_CSI3_AHB_CLK>,
1970 <&mmcc CAMSS_CSI3_CLK>,
1971 <&mmcc CAMSS_CPHY_CSID3_CLK>,
1972 <&mmcc CAMSS_CSI3PIX_CLK>,
1973 <&mmcc CAMSS_CSI3RDI_CLK>,
1974 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1975 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1976 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1977 <&mmcc CSIPHY_AHB2CRIF_CLK>,
1978 <&mmcc CAMSS_CSI_VFE0_CLK>,
1979 <&mmcc CAMSS_CSI_VFE1_CLK>,
1980 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1981 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
1982 <&mmcc CAMSS_TOP_AHB_CLK>,
1983 <&mmcc CAMSS_VFE0_AHB_CLK>,
1984 <&mmcc CAMSS_VFE0_CLK>,
1985 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1986 <&mmcc CAMSS_VFE1_AHB_CLK>,
1987 <&mmcc CAMSS_VFE1_CLK>,
1988 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1989 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
1990 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
1991 clock-names = "ahb",
1992 "cphy_csid0",
1993 "cphy_csid1",
1994 "cphy_csid2",
1995 "cphy_csid3",
1996 "csi0_ahb",
1997 "csi0",
1998 "csi0_phy",
1999 "csi0_pix",
2000 "csi0_rdi",
2001 "csi1_ahb",
2002 "csi1",
2003 "csi1_phy",
2004 "csi1_pix",
2005 "csi1_rdi",
2006 "csi2_ahb",
2007 "csi2",
2008 "csi2_phy",
2009 "csi2_pix",
2010 "csi2_rdi",
2011 "csi3_ahb",
2012 "csi3",
2013 "csi3_phy",
2014 "csi3_pix",
2015 "csi3_rdi",
2016 "csiphy0_timer",
2017 "csiphy1_timer",
2018 "csiphy2_timer",
2019 "csiphy_ahb2crif",
2020 "csi_vfe0",
2021 "csi_vfe1",
2022 "ispif_ahb",
2023 "throttle_axi",
2024 "top_ahb",
2025 "vfe0_ahb",
2026 "vfe0",
2027 "vfe0_stream",
2028 "vfe1_ahb",
2029 "vfe1",
2030 "vfe1_stream",
2031 "vfe_ahb",
2032 "vfe_axi";
2033 interconnects = <&mnoc 5 &bimc 5>;
2034 interconnect-names = "vfe-mem";
2035 iommus = <&mmss_smmu 0xc00>,
2036 <&mmss_smmu 0xc01>,
2037 <&mmss_smmu 0xc02>,
2038 <&mmss_smmu 0xc03>;
2039 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2040 <&mmcc CAMSS_VFE1_GDSC>;
2041 status = "disabled";
2042
2043 ports {
2044 #address-cells = <1>;
2045 #size-cells = <0>;
2046 };
2047 };
2048
2049 cci: cci@ca0c000 {
2050 compatible = "qcom,msm8996-cci";
2051 #address-cells = <1>;
2052 #size-cells = <0>;
2053 reg = <0x0ca0c000 0x1000>;
2054 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2055
2056 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2057 <&mmcc CAMSS_CCI_CLK>;
2058 assigned-clock-rates = <80800000>, <37500000>;
2059 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2060 <&mmcc CAMSS_CCI_AHB_CLK>,
2061 <&mmcc CAMSS_CCI_CLK>,
2062 <&mmcc CAMSS_AHB_CLK>;
2063 clock-names = "camss_top_ahb",
2064 "cci_ahb",
2065 "cci",
2066 "camss_ahb";
2067
2068 pinctrl-names = "default";
2069 pinctrl-0 = <&cci0_default &cci1_default>;
2070 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2071 status = "disabled";
2072
2073 cci_i2c0: i2c-bus@0 {
2074 reg = <0>;
2075 clock-frequency = <400000>;
2076 #address-cells = <1>;
2077 #size-cells = <0>;
2078 };
2079
2080 cci_i2c1: i2c-bus@1 {
2081 reg = <1>;
2082 clock-frequency = <400000>;
2083 #address-cells = <1>;
2084 #size-cells = <0>;
2085 };
2086 };
2087
2088 venus: video-codec@cc00000 {
2089 compatible = "qcom,sdm660-venus";
2090 reg = <0x0cc00000 0xff000>;
2091 clocks = <&mmcc VIDEO_CORE_CLK>,
2092 <&mmcc VIDEO_AHB_CLK>,
2093 <&mmcc VIDEO_AXI_CLK>,
2094 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2095 clock-names = "core", "iface", "bus", "bus_throttle";
2096 interconnects = <&gnoc 0 &mnoc 13>,
2097 <&mnoc 4 &bimc 5>;
2098 interconnect-names = "cpu-cfg", "video-mem";
2099 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2100 iommus = <&mmss_smmu 0x400>,
2101 <&mmss_smmu 0x401>,
2102 <&mmss_smmu 0x40a>,
2103 <&mmss_smmu 0x407>,
2104 <&mmss_smmu 0x40e>,
2105 <&mmss_smmu 0x40f>,
2106 <&mmss_smmu 0x408>,
2107 <&mmss_smmu 0x409>,
2108 <&mmss_smmu 0x40b>,
2109 <&mmss_smmu 0x40c>,
2110 <&mmss_smmu 0x40d>,
2111 <&mmss_smmu 0x410>,
2112 <&mmss_smmu 0x421>,
2113 <&mmss_smmu 0x428>,
2114 <&mmss_smmu 0x429>,
2115 <&mmss_smmu 0x42b>,
2116 <&mmss_smmu 0x42c>,
2117 <&mmss_smmu 0x42d>,
2118 <&mmss_smmu 0x411>,
2119 <&mmss_smmu 0x431>;
2120 memory-region = <&venus_region>;
2121 power-domains = <&mmcc VENUS_GDSC>;
2122 status = "disabled";
2123
2124 video-decoder {
2125 compatible = "venus-decoder";
2126 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2127 clock-names = "vcodec0_core";
2128 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2129 };
2130
2131 video-encoder {
2132 compatible = "venus-encoder";
2133 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2134 clock-names = "vcodec0_core";
2135 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2136 };
2137 };
2138
2139 mmss_smmu: iommu@cd00000 {
2140 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2141 reg = <0x0cd00000 0x40000>;
2142
2143 clocks = <&mmcc MNOC_AHB_CLK>,
2144 <&mmcc BIMC_SMMU_AHB_CLK>,
2145 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2146 <&mmcc BIMC_SMMU_AXI_CLK>;
2147 clock-names = "iface-mm", "iface-smmu",
2148 "bus-mm", "bus-smmu";
2149 #global-interrupts = <2>;
2150 #iommu-cells = <1>;
2151
2152 interrupts =
2153 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2155
2156 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2157 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2160 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2161 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2162 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2163 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2164 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2165 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2166 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2167 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2168 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2169 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2170 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2171 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2172 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2173 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2174 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2175 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2176 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2177 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2178 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2179 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2180
2181 status = "disabled";
2182 };
2183
2184 adsp_pil: remoteproc@15700000 {
2185 compatible = "qcom,sdm660-adsp-pas";
2186 reg = <0x15700000 0x4040>;
2187
2188 interrupts-extended =
2189 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2190 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2191 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2192 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2193 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2194 interrupt-names = "wdog", "fatal", "ready",
2195 "handover", "stop-ack";
2196
2197 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2198 clock-names = "xo";
2199
2200 memory-region = <&adsp_region>;
2201 power-domains = <&rpmpd SDM660_VDDCX>;
2202 power-domain-names = "cx";
2203
2204 qcom,smem-states = <&adsp_smp2p_out 0>;
2205 qcom,smem-state-names = "stop";
2206
2207 glink-edge {
2208 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2209
2210 label = "lpass";
2211 mboxes = <&apcs_glb 9>;
2212 qcom,remote-pid = <2>;
2213
2214 apr {
2215 compatible = "qcom,apr-v2";
2216 qcom,glink-channels = "apr_audio_svc";
2217 qcom,domain = <APR_DOMAIN_ADSP>;
2218 #address-cells = <1>;
2219 #size-cells = <0>;
2220
2221 q6core {
2222 reg = <APR_SVC_ADSP_CORE>;
2223 compatible = "qcom,q6core";
2224 };
2225
2226 q6afe: apr-service@4 {
2227 compatible = "qcom,q6afe";
2228 reg = <APR_SVC_AFE>;
2229 q6afedai: dais {
2230 compatible = "qcom,q6afe-dais";
2231 #address-cells = <1>;
2232 #size-cells = <0>;
2233 #sound-dai-cells = <1>;
2234 };
2235 };
2236
2237 q6asm: apr-service@7 {
2238 compatible = "qcom,q6asm";
2239 reg = <APR_SVC_ASM>;
2240 q6asmdai: dais {
2241 compatible = "qcom,q6asm-dais";
2242 #address-cells = <1>;
2243 #size-cells = <0>;
2244 #sound-dai-cells = <1>;
2245 iommus = <&lpass_smmu 1>;
2246 };
2247 };
2248
2249 q6adm: apr-service@8 {
2250 compatible = "qcom,q6adm";
2251 reg = <APR_SVC_ADM>;
2252 q6routing: routing {
2253 compatible = "qcom,q6adm-routing";
2254 #sound-dai-cells = <0>;
2255 };
2256 };
2257 };
2258 };
2259 };
2260
2261 gnoc: interconnect@17900000 {
2262 compatible = "qcom,sdm660-gnoc";
2263 reg = <0x17900000 0xe000>;
2264 #interconnect-cells = <1>;
2265 /*
2266 * This one apparently features no clocks,
2267 * so let's not mess with the driver needlessly
2268 */
2269 clock-names = "bus", "bus_a";
2270 clocks = <&xo_board>, <&xo_board>;
2271 };
2272
2273 apcs_glb: mailbox@17911000 {
2274 compatible = "qcom,sdm660-apcs-hmss-global";
2275 reg = <0x17911000 0x1000>;
2276
2277 #mbox-cells = <1>;
2278 };
2279
2280 timer@17920000 {
2281 #address-cells = <1>;
2282 #size-cells = <1>;
2283 ranges;
2284 compatible = "arm,armv7-timer-mem";
2285 reg = <0x17920000 0x1000>;
2286 clock-frequency = <19200000>;
2287
2288 frame@17921000 {
2289 frame-number = <0>;
2290 interrupts = <0 8 0x4>,
2291 <0 7 0x4>;
2292 reg = <0x17921000 0x1000>,
2293 <0x17922000 0x1000>;
2294 };
2295
2296 frame@17923000 {
2297 frame-number = <1>;
2298 interrupts = <0 9 0x4>;
2299 reg = <0x17923000 0x1000>;
2300 status = "disabled";
2301 };
2302
2303 frame@17924000 {
2304 frame-number = <2>;
2305 interrupts = <0 10 0x4>;
2306 reg = <0x17924000 0x1000>;
2307 status = "disabled";
2308 };
2309
2310 frame@17925000 {
2311 frame-number = <3>;
2312 interrupts = <0 11 0x4>;
2313 reg = <0x17925000 0x1000>;
2314 status = "disabled";
2315 };
2316
2317 frame@17926000 {
2318 frame-number = <4>;
2319 interrupts = <0 12 0x4>;
2320 reg = <0x17926000 0x1000>;
2321 status = "disabled";
2322 };
2323
2324 frame@17927000 {
2325 frame-number = <5>;
2326 interrupts = <0 13 0x4>;
2327 reg = <0x17927000 0x1000>;
2328 status = "disabled";
2329 };
2330
2331 frame@17928000 {
2332 frame-number = <6>;
2333 interrupts = <0 14 0x4>;
2334 reg = <0x17928000 0x1000>;
2335 status = "disabled";
2336 };
2337 };
2338
2339 intc: interrupt-controller@17a00000 {
2340 compatible = "arm,gic-v3";
2341 reg = <0x17a00000 0x10000>, /* GICD */
2342 <0x17b00000 0x100000>; /* GICR * 8 */
2343 #interrupt-cells = <3>;
2344 #address-cells = <1>;
2345 #size-cells = <1>;
2346 ranges;
2347 interrupt-controller;
2348 #redistributor-regions = <1>;
2349 redistributor-stride = <0x0 0x20000>;
2350 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2351 };
2352 };
2353
2354 tcsr_mutex: hwlock {
2355 compatible = "qcom,tcsr-mutex";
2356 syscon = <&tcsr_mutex_regs 0 0x1000>;
2357 #hwlock-cells = <1>;
2358 };
2359
2360 sound: sound {
2361 };
2362
2363 thermal-zones {
2364 aoss-thermal {
2365 polling-delay-passive = <250>;
2366 polling-delay = <1000>;
2367
2368 thermal-sensors = <&tsens 0>;
2369
2370 trips {
2371 aoss_alert0: trip-point0 {
2372 temperature = <105000>;
2373 hysteresis = <1000>;
2374 type = "hot";
2375 };
2376 };
2377 };
2378
2379 cpuss0-thermal {
2380 polling-delay-passive = <250>;
2381 polling-delay = <1000>;
2382
2383 thermal-sensors = <&tsens 1>;
2384
2385 trips {
2386 cpuss0_alert0: trip-point0 {
2387 temperature = <125000>;
2388 hysteresis = <1000>;
2389 type = "hot";
2390 };
2391 };
2392 };
2393
2394 cpuss1-thermal {
2395 polling-delay-passive = <250>;
2396 polling-delay = <1000>;
2397
2398 thermal-sensors = <&tsens 2>;
2399
2400 trips {
2401 cpuss1_alert0: trip-point0 {
2402 temperature = <125000>;
2403 hysteresis = <1000>;
2404 type = "hot";
2405 };
2406 };
2407 };
2408
2409 cpu0-thermal {
2410 polling-delay-passive = <250>;
2411 polling-delay = <1000>;
2412
2413 thermal-sensors = <&tsens 3>;
2414
2415 trips {
2416 cpu0_alert0: trip-point0 {
2417 temperature = <70000>;
2418 hysteresis = <1000>;
2419 type = "passive";
2420 };
2421
2422 cpu0_crit: cpu_crit {
2423 temperature = <110000>;
2424 hysteresis = <1000>;
2425 type = "critical";
2426 };
2427 };
2428 };
2429
2430 cpu1-thermal {
2431 polling-delay-passive = <250>;
2432 polling-delay = <1000>;
2433
2434 thermal-sensors = <&tsens 4>;
2435
2436 trips {
2437 cpu1_alert0: trip-point0 {
2438 temperature = <70000>;
2439 hysteresis = <1000>;
2440 type = "passive";
2441 };
2442
2443 cpu1_crit: cpu_crit {
2444 temperature = <110000>;
2445 hysteresis = <1000>;
2446 type = "critical";
2447 };
2448 };
2449 };
2450
2451 cpu2-thermal {
2452 polling-delay-passive = <250>;
2453 polling-delay = <1000>;
2454
2455 thermal-sensors = <&tsens 5>;
2456
2457 trips {
2458 cpu2_alert0: trip-point0 {
2459 temperature = <70000>;
2460 hysteresis = <1000>;
2461 type = "passive";
2462 };
2463
2464 cpu2_crit: cpu_crit {
2465 temperature = <110000>;
2466 hysteresis = <1000>;
2467 type = "critical";
2468 };
2469 };
2470 };
2471
2472 cpu3-thermal {
2473 polling-delay-passive = <250>;
2474 polling-delay = <1000>;
2475
2476 thermal-sensors = <&tsens 6>;
2477
2478 trips {
2479 cpu3_alert0: trip-point0 {
2480 temperature = <70000>;
2481 hysteresis = <1000>;
2482 type = "passive";
2483 };
2484
2485 cpu3_crit: cpu_crit {
2486 temperature = <110000>;
2487 hysteresis = <1000>;
2488 type = "critical";
2489 };
2490 };
2491 };
2492
2493 /*
2494 * According to what downstream DTS says,
2495 * the entire power efficient cluster has
2496 * only a single thermal sensor.
2497 */
2498
2499 pwr-cluster-thermal {
2500 polling-delay-passive = <250>;
2501 polling-delay = <1000>;
2502
2503 thermal-sensors = <&tsens 7>;
2504
2505 trips {
2506 pwr_cluster_alert0: trip-point0 {
2507 temperature = <70000>;
2508 hysteresis = <1000>;
2509 type = "passive";
2510 };
2511
2512 pwr_cluster_crit: cpu_crit {
2513 temperature = <110000>;
2514 hysteresis = <1000>;
2515 type = "critical";
2516 };
2517 };
2518 };
2519
2520 gpu-thermal {
2521 polling-delay-passive = <250>;
2522 polling-delay = <1000>;
2523
2524 thermal-sensors = <&tsens 8>;
2525
2526 trips {
2527 gpu_alert0: trip-point0 {
2528 temperature = <90000>;
2529 hysteresis = <1000>;
2530 type = "hot";
2531 };
2532 };
2533 };
2534 };
2535
2536 timer {
2537 compatible = "arm,armv8-timer";
2538 interrupts = <GIC_PPI 1 0xf08>,
2539 <GIC_PPI 2 0xf08>,
2540 <GIC_PPI 3 0xf08>,
2541 <GIC_PPI 0 0xf08>;
2542 };
2543 };
2544
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