0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * sc7280 CRD 3+ board device tree source
0004 *
0005 * Copyright 2022 Google LLC.
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "sc7280-herobrine.dtsi"
0011 #include "sc7280-herobrine-audio-wcd9385.dtsi"
0012
0013 / {
0014 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
0015 compatible = "google,hoglin", "qcom,sc7280";
0016
0017 /* FIXED REGULATORS */
0018
0019 /*
0020 * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL.
0021 * However, on CRD there's an extra regulator in the way. Since this
0022 * is expected to be uncommon, we'll leave the "vreg_edp_bl" label
0023 * in the baseboard herobrine.dtsi point at "ppvar_sys" and then
0024 * make a "_crd" specific version here.
0025 */
0026 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
0027 compatible = "regulator-fixed";
0028 regulator-name = "vreg_edp_bl_crd";
0029
0030 gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
0031 enable-active-high;
0032 pinctrl-names = "default";
0033 pinctrl-0 = <&edp_bl_reg_en>;
0034
0035 vin-supply = <&ppvar_sys>;
0036 };
0037 };
0038
0039 /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
0040
0041 &apps_rsc {
0042 pmg1110-regulators {
0043 compatible = "qcom,pmg1110-rpmh-regulators";
0044 qcom,pmic-id = "k";
0045
0046 vreg_s1k_1p0: smps1 {
0047 regulator-min-microvolt = <1010000>;
0048 regulator-max-microvolt = <1170000>;
0049 };
0050 };
0051 };
0052
0053 ap_tp_i2c: &i2c0 {
0054 status = "okay";
0055 clock-frequency = <400000>;
0056
0057 trackpad: trackpad@15 {
0058 compatible = "hid-over-i2c";
0059 reg = <0x15>;
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&tp_int_odl>;
0062
0063 interrupt-parent = <&tlmm>;
0064 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
0065
0066 post-power-on-delay-ms = <20>;
0067 hid-descr-addr = <0x0001>;
0068 vdd-supply = <&pp3300_z1>;
0069
0070 wakeup-source;
0071 };
0072 };
0073
0074 &ap_sar_sensor_i2c {
0075 status = "okay";
0076 };
0077
0078 &ap_sar_sensor0 {
0079 status = "okay";
0080 };
0081
0082 &ap_sar_sensor1 {
0083 status = "okay";
0084 };
0085
0086 ap_ts_pen_1v8: &i2c13 {
0087 status = "okay";
0088 clock-frequency = <400000>;
0089
0090 ap_ts: touchscreen@5c {
0091 compatible = "hid-over-i2c";
0092 reg = <0x5c>;
0093 pinctrl-names = "default";
0094 pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
0095
0096 interrupt-parent = <&tlmm>;
0097 interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
0098
0099 post-power-on-delay-ms = <500>;
0100 hid-descr-addr = <0x0000>;
0101
0102 vdd-supply = <&pp3300_left_in_mlb>;
0103 };
0104 };
0105
0106 &mdss_edp {
0107 status = "okay";
0108 };
0109
0110 &mdss_edp_phy {
0111 status = "okay";
0112 };
0113
0114 /* For nvme */
0115 &pcie1 {
0116 status = "okay";
0117 };
0118
0119 /* For nvme */
0120 &pcie1_phy {
0121 status = "okay";
0122 };
0123
0124 &pm8350c_pwm_backlight {
0125 power-supply = <&vreg_edp_bl_crd>;
0126 };
0127
0128 /* For eMMC */
0129 &sdhc_1 {
0130 status = "okay";
0131 };
0132
0133 /* For SD Card */
0134 &sdhc_2 {
0135 status = "okay";
0136 };
0137
0138 /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
0139
0140 /*
0141 * This pin goes to the display panel but then doesn't actually do anything
0142 * on the panel itself (it doesn't connect to the touchscreen controller).
0143 * We'll set a pullup here just to park the line.
0144 */
0145 &ts_rst_conn {
0146 bias-pull-up;
0147 };
0148
0149 /* PINCTRL - BOARD-SPECIFIC */
0150
0151 /*
0152 * Methodology for gpio-line-names:
0153 * - If a pin goes to CRD board and is named it gets that name.
0154 * - If a pin goes to CRD board and is not named, it gets no name.
0155 * - If a pin is totally internal to Qcard then it gets Qcard name.
0156 * - If a pin is not hooked up on Qcard, it gets no name.
0157 */
0158
0159 &pm8350c_gpios {
0160 gpio-line-names = "FLASH_STROBE_1", /* 1 */
0161 "AP_SUSPEND",
0162 "PM8008_1_RST_N",
0163 "",
0164 "",
0165 "EDP_BL_REG_EN",
0166 "PMIC_EDP_BL_EN",
0167 "PMIC_EDP_BL_PWM",
0168 "";
0169
0170 edp_bl_reg_en: edp-bl-reg-en {
0171 pins = "gpio6";
0172 function = "normal";
0173 bias-disable;
0174 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
0175 };
0176 };
0177
0178 &tlmm {
0179 gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
0180 "AP_TP_I2C_SCL",
0181 "PCIE1_RESET_N",
0182 "PCIE1_WAKE_N",
0183 "APPS_I2C_SDA",
0184 "APPS_I2C_SCL",
0185 "",
0186 "TPAD_INT_N",
0187 "",
0188 "",
0189
0190 "GNSS_L1_EN", /* 10 */
0191 "GNSS_L5_EN",
0192 "QSPI_DATA_0",
0193 "QSPI_DATA_1",
0194 "QSPI_CLK",
0195 "QSPI_CS_N_1",
0196 /*
0197 * AP_FLASH_WP is crossystem ABI. Schematics call it
0198 * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the
0199 * signal is active high).
0200 */
0201 "AP_FLASH_WP",
0202 "",
0203 "AP_EC_INT_N",
0204 "",
0205
0206 "CAM0_RST_N", /* 20 */
0207 "CAM1_RST_N",
0208 "SM_DBG_UART_TX",
0209 "SM_DBG_UART_RX",
0210 "",
0211 "PM8008_IRQ_1",
0212 "HOST2WLAN_SOL",
0213 "WLAN2HOST_SOL",
0214 "MOS_BT_UART_CTS",
0215 "MOS_BT_UART_RFR",
0216
0217 "MOS_BT_UART_TX", /* 30 */
0218 "MOS_BT_UART_RX",
0219 "",
0220 "HUB_RST",
0221 "",
0222 "",
0223 "",
0224 "",
0225 "",
0226 "",
0227
0228 "EC_SPI_MISO_GPIO40", /* 40 */
0229 "EC_SPI_MOSI_GPIO41",
0230 "EC_SPI_CLK_GPIO42",
0231 "EC_SPI_CS_GPIO43",
0232 "",
0233 "EARLY_EUD_EN",
0234 "",
0235 "DP_HOT_PLUG_DETECT",
0236 "AP_BRD_ID_0",
0237 "AP_BRD_ID_1",
0238
0239 "AP_BRD_ID_2", /* 50 */
0240 "NVME_PWR_REG_EN",
0241 "TS_I2C_SDA_CONN",
0242 "TS_I2C_CLK_CONN",
0243 "TS_RST_CONN",
0244 "TS_INT_CONN",
0245 "AP_I2C_TPM_SDA",
0246 "AP_I2C_TPM_SCL",
0247 "",
0248 "",
0249
0250 "EDP_HOT_PLUG_DET_N", /* 60 */
0251 "",
0252 "",
0253 "AMP_EN",
0254 "CAM0_MCLK_GPIO_64",
0255 "CAM1_MCLK_GPIO_65",
0256 "",
0257 "",
0258 "",
0259 "CCI_I2C_SDA0",
0260
0261 "CCI_I2C_SCL0", /* 70 */
0262 "",
0263 "",
0264 "",
0265 "",
0266 "",
0267 "",
0268 "",
0269 "",
0270 "PCIE1_CLK_REQ_N",
0271
0272 "EN_PP3300_DX_EDP", /* 80 */
0273 "US_EURO_HS_SEL",
0274 "FORCED_USB_BOOT",
0275 "WCD_RESET_N",
0276 "MOS_WLAN_EN",
0277 "MOS_BT_EN",
0278 "MOS_SW_CTRL",
0279 "MOS_PCIE0_RST",
0280 "MOS_PCIE0_CLKREQ_N",
0281 "MOS_PCIE0_WAKE_N",
0282
0283 "MOS_LAA_AS_EN", /* 90 */
0284 "SD_CARD_DET_CONN",
0285 "",
0286 "",
0287 "MOS_BT_WLAN_SLIMBUS_CLK",
0288 "MOS_BT_WLAN_SLIMBUS_DAT0",
0289 "",
0290 "",
0291 "",
0292 "",
0293
0294 "", /* 100 */
0295 "",
0296 "",
0297 "",
0298 "H1_AP_INT_N",
0299 "",
0300 "AMP_BCLK",
0301 "AMP_DIN",
0302 "AMP_LRCLK",
0303 "UIM1_DATA_GPIO_109",
0304
0305 "UIM1_CLK_GPIO_110", /* 110 */
0306 "UIM1_RESET_GPIO_111",
0307 "",
0308 "UIM1_DATA",
0309 "UIM1_CLK",
0310 "UIM1_RESET",
0311 "UIM1_PRESENT",
0312 "SDM_RFFE0_CLK",
0313 "SDM_RFFE0_DATA",
0314 "",
0315
0316 "SDM_RFFE1_DATA", /* 120 */
0317 "SC_GPIO_121",
0318 "FASTBOOT_SEL_1",
0319 "SC_GPIO_123",
0320 "FASTBOOT_SEL_2",
0321 "SM_RFFE4_CLK_GRFC_8",
0322 "SM_RFFE4_DATA_GRFC_9",
0323 "WLAN_COEX_UART1_RX",
0324 "WLAN_COEX_UART1_TX",
0325 "",
0326
0327 "", /* 130 */
0328 "",
0329 "",
0330 "SDR_QLINK_REQ",
0331 "SDR_QLINK_EN",
0332 "QLINK0_WMSS_RESET_N",
0333 "SMR526_QLINK1_REQ",
0334 "SMR526_QLINK1_EN",
0335 "SMR526_QLINK1_WMSS_RESET_N",
0336 "",
0337
0338 "SAR1_INT_N", /* 140 */
0339 "SAR0_INT_N",
0340 "",
0341 "",
0342 "WCD_SWR_TX_CLK",
0343 "WCD_SWR_TX_DATA0",
0344 "WCD_SWR_TX_DATA1",
0345 "WCD_SWR_RX_CLK",
0346 "WCD_SWR_RX_DATA0",
0347 "WCD_SWR_RX_DATA1",
0348
0349 "DMIC01_CLK", /* 150 */
0350 "DMIC01_DATA",
0351 "DMIC23_CLK",
0352 "DMIC23_DATA",
0353 "",
0354 "",
0355 "EC_IN_RW_N",
0356 "EN_PP3300_HUB",
0357 "WCD_SWR_TX_DATA2",
0358 "",
0359
0360 "", /* 160 */
0361 "",
0362 "",
0363 "",
0364 "",
0365 "",
0366 "",
0367 "",
0368 "",
0369 "",
0370
0371 "", /* 170 */
0372 "MOS_BLE_UART_TX",
0373 "MOS_BLE_UART_RX",
0374 "",
0375 "",
0376 "";
0377 };
