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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003  * sc7280 fragment for devices with Chrome bootloader
0004  *
0005  * This file mainly tries to abstract out the memory protections put into
0006  * place by the Chrome bootloader which are different than what's put into
0007  * place by Qualcomm's typical bootloader. It also has a smattering of other
0008  * things that will hold true for any conceivable Chrome design
0009  *
0010  * Copyright 2022 Google LLC.
0011  */
0012 
0013 /*
0014  * Reserved memory changes
0015  *
0016  * Delete all unused memory nodes and define the peripheral memory regions
0017  * required by the setup for Chrome boards.
0018  */
0019 
0020 /delete-node/ &hyp_mem;
0021 /delete-node/ &xbl_mem;
0022 /delete-node/ &reserved_xbl_uefi_log;
0023 /delete-node/ &sec_apps_mem;
0024 
0025 / {
0026         reserved-memory {
0027                 adsp_mem: memory@86700000 {
0028                         reg = <0x0 0x86700000 0x0 0x2800000>;
0029                         no-map;
0030                 };
0031 
0032                 camera_mem: memory@8ad00000 {
0033                         reg = <0x0 0x8ad00000 0x0 0x500000>;
0034                         no-map;
0035                 };
0036 
0037                 venus_mem: memory@8b200000 {
0038                         reg = <0x0 0x8b200000 0x0 0x500000>;
0039                         no-map;
0040                 };
0041 
0042                 mpss_mem: memory@8b800000 {
0043                         reg = <0x0 0x8b800000 0x0 0xf600000>;
0044                         no-map;
0045                 };
0046 
0047                 wpss_mem: memory@9ae00000 {
0048                         reg = <0x0 0x9ae00000 0x0 0x1900000>;
0049                         no-map;
0050                 };
0051 
0052                 mba_mem: memory@9c700000 {
0053                         reg = <0x0 0x9c700000 0x0 0x200000>;
0054                         no-map;
0055                 };
0056         };
0057 };
0058 
0059 /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
0060 &pmk8350_pon {
0061         status = "disabled";
0062 };
0063 
0064 /*
0065  * Chrome designs always boot from SPI flash hooked up to the qspi.
0066  *
0067  * It's expected that all boards will support "dual SPI" at 37.5 MHz.
0068  * If some boards need a different speed or have a package that allows
0069  * Quad SPI together with WP then those boards can easily override.
0070  */
0071 &qspi {
0072         status = "okay";
0073         pinctrl-names = "default";
0074         pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
0075 
0076         spi_flash: flash@0 {
0077                 compatible = "jedec,spi-nor";
0078                 reg = <0>;
0079 
0080                 spi-max-frequency = <37500000>;
0081                 spi-tx-bus-width = <2>;
0082                 spi-rx-bus-width = <2>;
0083         };
0084 };
0085 
0086 /* Modem setup is different on Chrome setups than typical Qualcomm setup */
0087 &remoteproc_mpss {
0088         status = "okay";
0089         compatible = "qcom,sc7280-mss-pil";
0090         iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
0091         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
0092         memory-region = <&mba_mem>, <&mpss_mem>;
0093         firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn",
0094                         "qcom/sc7280-herobrine/modem/qdsp6sw.mbn";
0095 };
0096 
0097 &remoteproc_wpss {
0098         status = "okay";
0099         firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
0100 };
0101 
0102 /* Increase the size from 2.5MB to 8MB */
0103 &rmtfs_mem {
0104         reg = <0x0 0x9c900000 0x0 0x800000>;
0105 };
0106 
0107 &wifi {
0108         status = "okay";
0109 
0110         wifi-firmware {
0111                 iommus = <&apps_smmu 0x1c02 0x1>;
0112         };
0113 };