0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018, Linaro Limited
0003
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
0006 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
0007 #include <dt-bindings/clock/qcom,rpmcc.h>
0008 #include <dt-bindings/power/qcom-rpmpd.h>
0009 #include <dt-bindings/thermal/thermal.h>
0010
0011 / {
0012 interrupt-parent = <&intc>;
0013
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 chosen { };
0018
0019 clocks {
0020 xo_board: xo-board {
0021 compatible = "fixed-clock";
0022 #clock-cells = <0>;
0023 clock-frequency = <19200000>;
0024 };
0025
0026 sleep_clk: sleep-clk {
0027 compatible = "fixed-clock";
0028 #clock-cells = <0>;
0029 clock-frequency = <32768>;
0030 };
0031 };
0032
0033 cpus {
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036
0037 CPU0: cpu@100 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a53";
0040 reg = <0x100>;
0041 enable-method = "psci";
0042 cpu-idle-states = <&CPU_SLEEP_0>;
0043 next-level-cache = <&L2_0>;
0044 #cooling-cells = <2>;
0045 clocks = <&apcs_glb>;
0046 operating-points-v2 = <&cpu_opp_table>;
0047 power-domains = <&cpr>;
0048 power-domain-names = "cpr";
0049 };
0050
0051 CPU1: cpu@101 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a53";
0054 reg = <0x101>;
0055 enable-method = "psci";
0056 cpu-idle-states = <&CPU_SLEEP_0>;
0057 next-level-cache = <&L2_0>;
0058 #cooling-cells = <2>;
0059 clocks = <&apcs_glb>;
0060 operating-points-v2 = <&cpu_opp_table>;
0061 power-domains = <&cpr>;
0062 power-domain-names = "cpr";
0063 };
0064
0065 CPU2: cpu@102 {
0066 device_type = "cpu";
0067 compatible = "arm,cortex-a53";
0068 reg = <0x102>;
0069 enable-method = "psci";
0070 cpu-idle-states = <&CPU_SLEEP_0>;
0071 next-level-cache = <&L2_0>;
0072 #cooling-cells = <2>;
0073 clocks = <&apcs_glb>;
0074 operating-points-v2 = <&cpu_opp_table>;
0075 power-domains = <&cpr>;
0076 power-domain-names = "cpr";
0077 };
0078
0079 CPU3: cpu@103 {
0080 device_type = "cpu";
0081 compatible = "arm,cortex-a53";
0082 reg = <0x103>;
0083 enable-method = "psci";
0084 cpu-idle-states = <&CPU_SLEEP_0>;
0085 next-level-cache = <&L2_0>;
0086 #cooling-cells = <2>;
0087 clocks = <&apcs_glb>;
0088 operating-points-v2 = <&cpu_opp_table>;
0089 power-domains = <&cpr>;
0090 power-domain-names = "cpr";
0091 };
0092
0093 L2_0: l2-cache {
0094 compatible = "cache";
0095 cache-level = <2>;
0096 };
0097
0098 idle-states {
0099 entry-method = "psci";
0100
0101 CPU_SLEEP_0: cpu-sleep-0 {
0102 compatible = "arm,idle-state";
0103 idle-state-name = "standalone-power-collapse";
0104 arm,psci-suspend-param = <0x40000003>;
0105 entry-latency-us = <125>;
0106 exit-latency-us = <180>;
0107 min-residency-us = <595>;
0108 local-timer-stop;
0109 };
0110 };
0111 };
0112
0113 cpu_opp_table: opp-table-cpu {
0114 compatible = "operating-points-v2-kryo-cpu";
0115 opp-shared;
0116
0117 opp-1094400000 {
0118 opp-hz = /bits/ 64 <1094400000>;
0119 required-opps = <&cpr_opp1>;
0120 };
0121 opp-1248000000 {
0122 opp-hz = /bits/ 64 <1248000000>;
0123 required-opps = <&cpr_opp2>;
0124 };
0125 opp-1401600000 {
0126 opp-hz = /bits/ 64 <1401600000>;
0127 required-opps = <&cpr_opp3>;
0128 };
0129 };
0130
0131 cpr_opp_table: opp-table-cpr {
0132 compatible = "operating-points-v2-qcom-level";
0133
0134 cpr_opp1: opp1 {
0135 opp-level = <1>;
0136 qcom,opp-fuse-level = <1>;
0137 };
0138 cpr_opp2: opp2 {
0139 opp-level = <2>;
0140 qcom,opp-fuse-level = <2>;
0141 };
0142 cpr_opp3: opp3 {
0143 opp-level = <3>;
0144 qcom,opp-fuse-level = <3>;
0145 };
0146 };
0147
0148 firmware {
0149 scm: scm {
0150 compatible = "qcom,scm-qcs404", "qcom,scm";
0151 #reset-cells = <1>;
0152 };
0153 };
0154
0155 memory@80000000 {
0156 device_type = "memory";
0157 /* We expect the bootloader to fill in the size */
0158 reg = <0 0x80000000 0 0>;
0159 };
0160
0161 psci {
0162 compatible = "arm,psci-1.0";
0163 method = "smc";
0164 };
0165
0166 reserved-memory {
0167 #address-cells = <2>;
0168 #size-cells = <2>;
0169 ranges;
0170
0171 tz_apps_mem: memory@85900000 {
0172 reg = <0 0x85900000 0 0x500000>;
0173 no-map;
0174 };
0175
0176 xbl_mem: memory@85e00000 {
0177 reg = <0 0x85e00000 0 0x100000>;
0178 no-map;
0179 };
0180
0181 smem_region: memory@85f00000 {
0182 reg = <0 0x85f00000 0 0x200000>;
0183 no-map;
0184 };
0185
0186 tz_mem: memory@86100000 {
0187 reg = <0 0x86100000 0 0x300000>;
0188 no-map;
0189 };
0190
0191 wlan_fw_mem: memory@86400000 {
0192 reg = <0 0x86400000 0 0x1100000>;
0193 no-map;
0194 };
0195
0196 adsp_fw_mem: memory@87500000 {
0197 reg = <0 0x87500000 0 0x1a00000>;
0198 no-map;
0199 };
0200
0201 cdsp_fw_mem: memory@88f00000 {
0202 reg = <0 0x88f00000 0 0x600000>;
0203 no-map;
0204 };
0205
0206 wlan_msa_mem: memory@89500000 {
0207 reg = <0 0x89500000 0 0x100000>;
0208 no-map;
0209 };
0210
0211 uefi_mem: memory@9f800000 {
0212 reg = <0 0x9f800000 0 0x800000>;
0213 no-map;
0214 };
0215 };
0216
0217 rpm-glink {
0218 compatible = "qcom,glink-rpm";
0219
0220 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0221 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0222 mboxes = <&apcs_glb 0>;
0223
0224 rpm_requests: glink-channel {
0225 compatible = "qcom,rpm-qcs404";
0226 qcom,glink-channels = "rpm_requests";
0227
0228 rpmcc: clock-controller {
0229 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
0230 #clock-cells = <1>;
0231 };
0232
0233 rpmpd: power-controller {
0234 compatible = "qcom,qcs404-rpmpd";
0235 #power-domain-cells = <1>;
0236 operating-points-v2 = <&rpmpd_opp_table>;
0237
0238 rpmpd_opp_table: opp-table {
0239 compatible = "operating-points-v2";
0240
0241 rpmpd_opp_ret: opp1 {
0242 opp-level = <16>;
0243 };
0244
0245 rpmpd_opp_ret_plus: opp2 {
0246 opp-level = <32>;
0247 };
0248
0249 rpmpd_opp_min_svs: opp3 {
0250 opp-level = <48>;
0251 };
0252
0253 rpmpd_opp_low_svs: opp4 {
0254 opp-level = <64>;
0255 };
0256
0257 rpmpd_opp_svs: opp5 {
0258 opp-level = <128>;
0259 };
0260
0261 rpmpd_opp_svs_plus: opp6 {
0262 opp-level = <192>;
0263 };
0264
0265 rpmpd_opp_nom: opp7 {
0266 opp-level = <256>;
0267 };
0268
0269 rpmpd_opp_nom_plus: opp8 {
0270 opp-level = <320>;
0271 };
0272
0273 rpmpd_opp_turbo: opp9 {
0274 opp-level = <384>;
0275 };
0276
0277 rpmpd_opp_turbo_no_cpr: opp10 {
0278 opp-level = <416>;
0279 };
0280
0281 rpmpd_opp_turbo_plus: opp11 {
0282 opp-level = <512>;
0283 };
0284 };
0285 };
0286 };
0287 };
0288
0289 smem {
0290 compatible = "qcom,smem";
0291
0292 memory-region = <&smem_region>;
0293 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0294
0295 hwlocks = <&tcsr_mutex 3>;
0296 };
0297
0298 tcsr_mutex: hwlock {
0299 compatible = "qcom,tcsr-mutex";
0300 syscon = <&tcsr_mutex_regs 0 0x1000>;
0301 #hwlock-cells = <1>;
0302 };
0303
0304 soc: soc@0 {
0305 #address-cells = <1>;
0306 #size-cells = <1>;
0307 ranges = <0 0 0 0xffffffff>;
0308 compatible = "simple-bus";
0309
0310 turingcc: clock-controller@800000 {
0311 compatible = "qcom,qcs404-turingcc";
0312 reg = <0x00800000 0x30000>;
0313 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
0314
0315 #clock-cells = <1>;
0316 #reset-cells = <1>;
0317
0318 status = "disabled";
0319 };
0320
0321 rpm_msg_ram: sram@60000 {
0322 compatible = "qcom,rpm-msg-ram";
0323 reg = <0x00060000 0x6000>;
0324 };
0325
0326 usb3_phy: phy@78000 {
0327 compatible = "qcom,usb-ss-28nm-phy";
0328 reg = <0x00078000 0x400>;
0329 #phy-cells = <0>;
0330 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
0331 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
0332 <&gcc GCC_USB3_PHY_PIPE_CLK>;
0333 clock-names = "ref", "ahb", "pipe";
0334 resets = <&gcc GCC_USB3_PHY_BCR>,
0335 <&gcc GCC_USB3PHY_PHY_BCR>;
0336 reset-names = "com", "phy";
0337 status = "disabled";
0338 };
0339
0340 usb2_phy_prim: phy@7a000 {
0341 compatible = "qcom,usb-hs-28nm-femtophy";
0342 reg = <0x0007a000 0x200>;
0343 #phy-cells = <0>;
0344 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
0345 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
0346 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
0347 clock-names = "ref", "ahb", "sleep";
0348 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
0349 <&gcc GCC_USB2A_PHY_BCR>;
0350 reset-names = "phy", "por";
0351 status = "disabled";
0352 };
0353
0354 usb2_phy_sec: phy@7c000 {
0355 compatible = "qcom,usb-hs-28nm-femtophy";
0356 reg = <0x0007c000 0x200>;
0357 #phy-cells = <0>;
0358 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
0359 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
0360 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
0361 clock-names = "ref", "ahb", "sleep";
0362 resets = <&gcc GCC_QUSB2_PHY_BCR>,
0363 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
0364 reset-names = "phy", "por";
0365 status = "disabled";
0366 };
0367
0368 qfprom: qfprom@a4000 {
0369 compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
0370 reg = <0x000a4000 0x1000>;
0371 #address-cells = <1>;
0372 #size-cells = <1>;
0373 tsens_caldata: caldata@d0 {
0374 reg = <0x1f8 0x14>;
0375 };
0376 cpr_efuse_speedbin: speedbin@13c {
0377 reg = <0x13c 0x4>;
0378 bits = <2 3>;
0379 };
0380 cpr_efuse_quot_offset1: qoffset1@231 {
0381 reg = <0x231 0x4>;
0382 bits = <4 7>;
0383 };
0384 cpr_efuse_quot_offset2: qoffset2@232 {
0385 reg = <0x232 0x4>;
0386 bits = <3 7>;
0387 };
0388 cpr_efuse_quot_offset3: qoffset3@233 {
0389 reg = <0x233 0x4>;
0390 bits = <2 7>;
0391 };
0392 cpr_efuse_init_voltage1: ivoltage1@229 {
0393 reg = <0x229 0x4>;
0394 bits = <4 6>;
0395 };
0396 cpr_efuse_init_voltage2: ivoltage2@22a {
0397 reg = <0x22a 0x4>;
0398 bits = <2 6>;
0399 };
0400 cpr_efuse_init_voltage3: ivoltage3@22b {
0401 reg = <0x22b 0x4>;
0402 bits = <0 6>;
0403 };
0404 cpr_efuse_quot1: quot1@22b {
0405 reg = <0x22b 0x4>;
0406 bits = <6 12>;
0407 };
0408 cpr_efuse_quot2: quot2@22d {
0409 reg = <0x22d 0x4>;
0410 bits = <2 12>;
0411 };
0412 cpr_efuse_quot3: quot3@230 {
0413 reg = <0x230 0x4>;
0414 bits = <0 12>;
0415 };
0416 cpr_efuse_ring1: ring1@228 {
0417 reg = <0x228 0x4>;
0418 bits = <0 3>;
0419 };
0420 cpr_efuse_ring2: ring2@228 {
0421 reg = <0x228 0x4>;
0422 bits = <4 3>;
0423 };
0424 cpr_efuse_ring3: ring3@229 {
0425 reg = <0x229 0x4>;
0426 bits = <0 3>;
0427 };
0428 cpr_efuse_revision: revision@218 {
0429 reg = <0x218 0x4>;
0430 bits = <3 3>;
0431 };
0432 };
0433
0434 rng: rng@e3000 {
0435 compatible = "qcom,prng-ee";
0436 reg = <0x000e3000 0x1000>;
0437 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0438 clock-names = "core";
0439 };
0440
0441 bimc: interconnect@400000 {
0442 reg = <0x00400000 0x80000>;
0443 compatible = "qcom,qcs404-bimc";
0444 #interconnect-cells = <1>;
0445 clock-names = "bus", "bus_a";
0446 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
0447 <&rpmcc RPM_SMD_BIMC_A_CLK>;
0448 };
0449
0450 tsens: thermal-sensor@4a9000 {
0451 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
0452 reg = <0x004a9000 0x1000>, /* TM */
0453 <0x004a8000 0x1000>; /* SROT */
0454 nvmem-cells = <&tsens_caldata>;
0455 nvmem-cell-names = "calib";
0456 #qcom,sensors = <10>;
0457 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0458 interrupt-names = "uplow";
0459 #thermal-sensor-cells = <1>;
0460 };
0461
0462 pcnoc: interconnect@500000 {
0463 reg = <0x00500000 0x15080>;
0464 compatible = "qcom,qcs404-pcnoc";
0465 #interconnect-cells = <1>;
0466 clock-names = "bus", "bus_a";
0467 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
0468 <&rpmcc RPM_SMD_PNOC_A_CLK>;
0469 };
0470
0471 snoc: interconnect@580000 {
0472 reg = <0x00580000 0x23080>;
0473 compatible = "qcom,qcs404-snoc";
0474 #interconnect-cells = <1>;
0475 clock-names = "bus", "bus_a";
0476 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
0477 <&rpmcc RPM_SMD_SNOC_A_CLK>;
0478 };
0479
0480 remoteproc_cdsp: remoteproc@b00000 {
0481 compatible = "qcom,qcs404-cdsp-pas";
0482 reg = <0x00b00000 0x4040>;
0483
0484 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
0485 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0486 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0487 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0488 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
0489 interrupt-names = "wdog", "fatal", "ready",
0490 "handover", "stop-ack";
0491
0492 clocks = <&xo_board>,
0493 <&gcc GCC_CDSP_CFG_AHB_CLK>,
0494 <&gcc GCC_CDSP_TBU_CLK>,
0495 <&gcc GCC_BIMC_CDSP_CLK>,
0496 <&turingcc TURING_WRAPPER_AON_CLK>,
0497 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
0498 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
0499 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
0500 clock-names = "xo",
0501 "sway",
0502 "tbu",
0503 "bimc",
0504 "ahb_aon",
0505 "q6ss_slave",
0506 "q6ss_master",
0507 "q6_axim";
0508
0509 resets = <&gcc GCC_CDSP_RESTART>;
0510 reset-names = "restart";
0511
0512 qcom,halt-regs = <&tcsr 0x19004>;
0513
0514 memory-region = <&cdsp_fw_mem>;
0515
0516 qcom,smem-states = <&cdsp_smp2p_out 0>;
0517 qcom,smem-state-names = "stop";
0518
0519 status = "disabled";
0520
0521 glink-edge {
0522 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
0523
0524 qcom,remote-pid = <5>;
0525 mboxes = <&apcs_glb 12>;
0526
0527 label = "cdsp";
0528 };
0529 };
0530
0531 usb3: usb@7678800 {
0532 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
0533 reg = <0x07678800 0x400>;
0534 #address-cells = <1>;
0535 #size-cells = <1>;
0536 ranges;
0537 clocks = <&gcc GCC_USB30_MASTER_CLK>,
0538 <&gcc GCC_SYS_NOC_USB3_CLK>,
0539 <&gcc GCC_USB30_SLEEP_CLK>,
0540 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
0541 clock-names = "core", "iface", "sleep", "mock_utmi";
0542 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
0543 <&gcc GCC_USB30_MASTER_CLK>;
0544 assigned-clock-rates = <19200000>, <200000000>;
0545 status = "disabled";
0546
0547 usb3_dwc3: usb@7580000 {
0548 compatible = "snps,dwc3";
0549 reg = <0x07580000 0xcd00>;
0550 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0551 phys = <&usb2_phy_prim>, <&usb3_phy>;
0552 phy-names = "usb2-phy", "usb3-phy";
0553 snps,has-lpm-erratum;
0554 snps,hird-threshold = /bits/ 8 <0x10>;
0555 snps,usb3_lpm_capable;
0556 dr_mode = "otg";
0557 };
0558 };
0559
0560 usb2: usb@79b8800 {
0561 compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
0562 reg = <0x079b8800 0x400>;
0563 #address-cells = <1>;
0564 #size-cells = <1>;
0565 ranges;
0566 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
0567 <&gcc GCC_PCNOC_USB2_CLK>,
0568 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
0569 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
0570 clock-names = "core", "iface", "sleep", "mock_utmi";
0571 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
0572 <&gcc GCC_USB_HS_SYSTEM_CLK>;
0573 assigned-clock-rates = <19200000>, <133333333>;
0574 status = "disabled";
0575
0576 usb@78c0000 {
0577 compatible = "snps,dwc3";
0578 reg = <0x078c0000 0xcc00>;
0579 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0580 phys = <&usb2_phy_sec>;
0581 phy-names = "usb2-phy";
0582 snps,has-lpm-erratum;
0583 snps,hird-threshold = /bits/ 8 <0x10>;
0584 snps,usb3_lpm_capable;
0585 dr_mode = "peripheral";
0586 };
0587 };
0588
0589 tlmm: pinctrl@1000000 {
0590 compatible = "qcom,qcs404-pinctrl";
0591 reg = <0x01000000 0x200000>,
0592 <0x01300000 0x200000>,
0593 <0x07b00000 0x200000>;
0594 reg-names = "south", "north", "east";
0595 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0596 gpio-ranges = <&tlmm 0 0 120>;
0597 gpio-controller;
0598 #gpio-cells = <2>;
0599 interrupt-controller;
0600 #interrupt-cells = <2>;
0601
0602 blsp1_i2c0_default: blsp1-i2c0-default {
0603 pins = "gpio32", "gpio33";
0604 function = "blsp_i2c0";
0605 };
0606
0607 blsp1_i2c1_default: blsp1-i2c1-default {
0608 pins = "gpio24", "gpio25";
0609 function = "blsp_i2c1";
0610 };
0611
0612 blsp1_i2c2_default: blsp1-i2c2-default {
0613 sda {
0614 pins = "gpio19";
0615 function = "blsp_i2c_sda_a2";
0616 };
0617
0618 scl {
0619 pins = "gpio20";
0620 function = "blsp_i2c_scl_a2";
0621 };
0622 };
0623
0624 blsp1_i2c3_default: blsp1-i2c3-default {
0625 pins = "gpio84", "gpio85";
0626 function = "blsp_i2c3";
0627 };
0628
0629 blsp1_i2c4_default: blsp1-i2c4-default {
0630 pins = "gpio117", "gpio118";
0631 function = "blsp_i2c4";
0632 };
0633
0634 blsp1_uart0_default: blsp1-uart0-default {
0635 pins = "gpio30", "gpio31", "gpio32", "gpio33";
0636 function = "blsp_uart0";
0637 };
0638
0639 blsp1_uart1_default: blsp1-uart1-default {
0640 pins = "gpio22", "gpio23";
0641 function = "blsp_uart1";
0642 };
0643
0644 blsp1_uart2_default: blsp1-uart2-default {
0645 rx {
0646 pins = "gpio18";
0647 function = "blsp_uart_rx_a2";
0648 };
0649
0650 tx {
0651 pins = "gpio17";
0652 function = "blsp_uart_tx_a2";
0653 };
0654 };
0655
0656 blsp1_uart3_default: blsp1-uart3-default {
0657 pins = "gpio82", "gpio83", "gpio84", "gpio85";
0658 function = "blsp_uart3";
0659 };
0660
0661 blsp2_i2c0_default: blsp2-i2c0-default {
0662 pins = "gpio28", "gpio29";
0663 function = "blsp_i2c5";
0664 };
0665
0666 blsp1_spi0_default: blsp1-spi0-default {
0667 pins = "gpio30", "gpio31", "gpio32", "gpio33";
0668 function = "blsp_spi0";
0669 };
0670
0671 blsp1_spi1_default: blsp1-spi1-default {
0672 mosi {
0673 pins = "gpio22";
0674 function = "blsp_spi_mosi_a1";
0675 };
0676
0677 miso {
0678 pins = "gpio23";
0679 function = "blsp_spi_miso_a1";
0680 };
0681
0682 cs_n {
0683 pins = "gpio24";
0684 function = "blsp_spi_cs_n_a1";
0685 };
0686
0687 clk {
0688 pins = "gpio25";
0689 function = "blsp_spi_clk_a1";
0690 };
0691 };
0692
0693 blsp1_spi2_default: blsp1-spi2-default {
0694 pins = "gpio17", "gpio18", "gpio19", "gpio20";
0695 function = "blsp_spi2";
0696 };
0697
0698 blsp1_spi3_default: blsp1-spi3-default {
0699 pins = "gpio82", "gpio83", "gpio84", "gpio85";
0700 function = "blsp_spi3";
0701 };
0702
0703 blsp1_spi4_default: blsp1-spi4-default {
0704 pins = "gpio37", "gpio38", "gpio117", "gpio118";
0705 function = "blsp_spi4";
0706 };
0707
0708 blsp2_spi0_default: blsp2-spi0-default {
0709 pins = "gpio26", "gpio27", "gpio28", "gpio29";
0710 function = "blsp_spi5";
0711 };
0712
0713 blsp2_uart0_default: blsp2-uart0-default {
0714 pins = "gpio26", "gpio27", "gpio28", "gpio29";
0715 function = "blsp_uart5";
0716 };
0717 };
0718
0719 gcc: clock-controller@1800000 {
0720 compatible = "qcom,gcc-qcs404";
0721 reg = <0x01800000 0x80000>;
0722 #clock-cells = <1>;
0723 #reset-cells = <1>;
0724
0725 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
0726 assigned-clock-rates = <19200000>;
0727 };
0728
0729 tcsr_mutex_regs: syscon@1905000 {
0730 compatible = "syscon";
0731 reg = <0x01905000 0x20000>;
0732 };
0733
0734 tcsr: syscon@1937000 {
0735 compatible = "syscon";
0736 reg = <0x01937000 0x25000>;
0737 };
0738
0739 sram@290000 {
0740 compatible = "qcom,rpm-stats";
0741 reg = <0x00290000 0x10000>;
0742 };
0743
0744 spmi_bus: spmi@200f000 {
0745 compatible = "qcom,spmi-pmic-arb";
0746 reg = <0x0200f000 0x001000>,
0747 <0x02400000 0x800000>,
0748 <0x02c00000 0x800000>,
0749 <0x03800000 0x200000>,
0750 <0x0200a000 0x002100>;
0751 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
0752 interrupt-names = "periph_irq";
0753 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0754 qcom,ee = <0>;
0755 qcom,channel = <0>;
0756 #address-cells = <2>;
0757 #size-cells = <0>;
0758 interrupt-controller;
0759 #interrupt-cells = <4>;
0760 };
0761
0762 remoteproc_wcss: remoteproc@7400000 {
0763 compatible = "qcom,qcs404-wcss-pas";
0764 reg = <0x07400000 0x4040>;
0765
0766 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
0767 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0768 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0769 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0770 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
0771 interrupt-names = "wdog", "fatal", "ready",
0772 "handover", "stop-ack";
0773
0774 clocks = <&xo_board>;
0775 clock-names = "xo";
0776
0777 memory-region = <&wlan_fw_mem>;
0778
0779 qcom,smem-states = <&wcss_smp2p_out 0>;
0780 qcom,smem-state-names = "stop";
0781
0782 status = "disabled";
0783
0784 glink-edge {
0785 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
0786
0787 qcom,remote-pid = <1>;
0788 mboxes = <&apcs_glb 16>;
0789
0790 label = "wcss";
0791 };
0792 };
0793
0794 pcie_phy: phy@7786000 {
0795 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
0796 reg = <0x07786000 0xb8>;
0797
0798 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
0799 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
0800 <&gcc 21>;
0801 reset-names = "phy", "pipe";
0802
0803 clock-output-names = "pcie_0_pipe_clk";
0804 #phy-cells = <0>;
0805
0806 status = "disabled";
0807 };
0808
0809 sdcc1: mmc@7804000 {
0810 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
0811 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
0812 reg-names = "hc", "cqhci";
0813
0814 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0815 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0816 interrupt-names = "hc_irq", "pwr_irq";
0817
0818 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0819 <&gcc GCC_SDCC1_APPS_CLK>,
0820 <&xo_board>;
0821 clock-names = "iface", "core", "xo";
0822
0823 status = "disabled";
0824 };
0825
0826 blsp1_dma: dma-controller@7884000 {
0827 compatible = "qcom,bam-v1.7.0";
0828 reg = <0x07884000 0x25000>;
0829 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
0830 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
0831 clock-names = "bam_clk";
0832 #dma-cells = <1>;
0833 qcom,ee = <0>;
0834 status = "okay";
0835 };
0836
0837 blsp1_uart0: serial@78af000 {
0838 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0839 reg = <0x078af000 0x200>;
0840 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0841 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0842 clock-names = "core", "iface";
0843 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
0844 dma-names = "tx", "rx";
0845 pinctrl-names = "default";
0846 pinctrl-0 = <&blsp1_uart0_default>;
0847 status = "disabled";
0848 };
0849
0850 blsp1_uart1: serial@78b0000 {
0851 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0852 reg = <0x078b0000 0x200>;
0853 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0854 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0855 clock-names = "core", "iface";
0856 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
0857 dma-names = "tx", "rx";
0858 pinctrl-names = "default";
0859 pinctrl-0 = <&blsp1_uart1_default>;
0860 status = "disabled";
0861 };
0862
0863 blsp1_uart2: serial@78b1000 {
0864 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0865 reg = <0x078b1000 0x200>;
0866 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0867 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0868 clock-names = "core", "iface";
0869 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
0870 dma-names = "tx", "rx";
0871 pinctrl-names = "default";
0872 pinctrl-0 = <&blsp1_uart2_default>;
0873 status = "okay";
0874 };
0875
0876 ethernet: ethernet@7a80000 {
0877 compatible = "qcom,qcs404-ethqos";
0878 reg = <0x07a80000 0x10000>,
0879 <0x07a96000 0x100>;
0880 reg-names = "stmmaceth", "rgmii";
0881 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
0882 clocks = <&gcc GCC_ETH_AXI_CLK>,
0883 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
0884 <&gcc GCC_ETH_PTP_CLK>,
0885 <&gcc GCC_ETH_RGMII_CLK>;
0886 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0887 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0888 interrupt-names = "macirq", "eth_lpi";
0889
0890 snps,tso;
0891 rx-fifo-depth = <4096>;
0892 tx-fifo-depth = <4096>;
0893
0894 status = "disabled";
0895 };
0896
0897 wifi: wifi@a000000 {
0898 compatible = "qcom,wcn3990-wifi";
0899 reg = <0xa000000 0x800000>;
0900 reg-names = "membase";
0901 memory-region = <&wlan_msa_mem>;
0902 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
0903 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
0904 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
0905 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
0906 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
0907 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
0908 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
0909 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
0910 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
0911 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
0912 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
0913 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
0914 status = "disabled";
0915 };
0916
0917 blsp1_uart3: serial@78b2000 {
0918 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0919 reg = <0x078b2000 0x200>;
0920 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0921 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0922 clock-names = "core", "iface";
0923 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
0924 dma-names = "tx", "rx";
0925 pinctrl-names = "default";
0926 pinctrl-0 = <&blsp1_uart3_default>;
0927 status = "disabled";
0928 };
0929
0930 blsp1_i2c0: i2c@78b5000 {
0931 compatible = "qcom,i2c-qup-v2.2.1";
0932 reg = <0x078b5000 0x600>;
0933 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0934 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
0935 <&gcc GCC_BLSP1_AHB_CLK>;
0936 clock-names = "core", "iface";
0937 pinctrl-names = "default";
0938 pinctrl-0 = <&blsp1_i2c0_default>;
0939 #address-cells = <1>;
0940 #size-cells = <0>;
0941 status = "disabled";
0942 };
0943
0944 blsp1_spi0: spi@78b5000 {
0945 compatible = "qcom,spi-qup-v2.2.1";
0946 reg = <0x078b5000 0x600>;
0947 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0948 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
0949 <&gcc GCC_BLSP1_AHB_CLK>;
0950 clock-names = "core", "iface";
0951 pinctrl-names = "default";
0952 pinctrl-0 = <&blsp1_spi0_default>;
0953 #address-cells = <1>;
0954 #size-cells = <0>;
0955 status = "disabled";
0956 };
0957
0958 blsp1_i2c1: i2c@78b6000 {
0959 compatible = "qcom,i2c-qup-v2.2.1";
0960 reg = <0x078b6000 0x600>;
0961 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0962 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
0963 <&gcc GCC_BLSP1_AHB_CLK>;
0964 clock-names = "core", "iface";
0965 pinctrl-names = "default";
0966 pinctrl-0 = <&blsp1_i2c1_default>;
0967 #address-cells = <1>;
0968 #size-cells = <0>;
0969 status = "disabled";
0970 };
0971
0972 blsp1_spi1: spi@78b6000 {
0973 compatible = "qcom,spi-qup-v2.2.1";
0974 reg = <0x078b6000 0x600>;
0975 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0976 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
0977 <&gcc GCC_BLSP1_AHB_CLK>;
0978 clock-names = "core", "iface";
0979 pinctrl-names = "default";
0980 pinctrl-0 = <&blsp1_spi1_default>;
0981 #address-cells = <1>;
0982 #size-cells = <0>;
0983 status = "disabled";
0984 };
0985
0986 blsp1_i2c2: i2c@78b7000 {
0987 compatible = "qcom,i2c-qup-v2.2.1";
0988 reg = <0x078b7000 0x600>;
0989 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0990 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
0991 <&gcc GCC_BLSP1_AHB_CLK>;
0992 clock-names = "core", "iface";
0993 pinctrl-names = "default";
0994 pinctrl-0 = <&blsp1_i2c2_default>;
0995 #address-cells = <1>;
0996 #size-cells = <0>;
0997 status = "disabled";
0998 };
0999
1000 blsp1_spi2: spi@78b7000 {
1001 compatible = "qcom,spi-qup-v2.2.1";
1002 reg = <0x078b7000 0x600>;
1003 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1005 <&gcc GCC_BLSP1_AHB_CLK>;
1006 clock-names = "core", "iface";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&blsp1_spi2_default>;
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 status = "disabled";
1012 };
1013
1014 blsp1_i2c3: i2c@78b8000 {
1015 compatible = "qcom,i2c-qup-v2.2.1";
1016 reg = <0x078b8000 0x600>;
1017 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1019 <&gcc GCC_BLSP1_AHB_CLK>;
1020 clock-names = "core", "iface";
1021 pinctrl-names = "default";
1022 pinctrl-0 = <&blsp1_i2c3_default>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 status = "disabled";
1026 };
1027
1028 blsp1_spi3: spi@78b8000 {
1029 compatible = "qcom,spi-qup-v2.2.1";
1030 reg = <0x078b8000 0x600>;
1031 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1033 <&gcc GCC_BLSP1_AHB_CLK>;
1034 clock-names = "core", "iface";
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&blsp1_spi3_default>;
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 status = "disabled";
1040 };
1041
1042 blsp1_i2c4: i2c@78b9000 {
1043 compatible = "qcom,i2c-qup-v2.2.1";
1044 reg = <0x078b9000 0x600>;
1045 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1047 <&gcc GCC_BLSP1_AHB_CLK>;
1048 clock-names = "core", "iface";
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&blsp1_i2c4_default>;
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1053 status = "disabled";
1054 };
1055
1056 blsp1_spi4: spi@78b9000 {
1057 compatible = "qcom,spi-qup-v2.2.1";
1058 reg = <0x078b9000 0x600>;
1059 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1061 <&gcc GCC_BLSP1_AHB_CLK>;
1062 clock-names = "core", "iface";
1063 pinctrl-names = "default";
1064 pinctrl-0 = <&blsp1_spi4_default>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1067 status = "disabled";
1068 };
1069
1070 blsp2_dma: dma-controller@7ac4000 {
1071 compatible = "qcom,bam-v1.7.0";
1072 reg = <0x07ac4000 0x17000>;
1073 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1075 clock-names = "bam_clk";
1076 #dma-cells = <1>;
1077 qcom,ee = <0>;
1078 status = "disabled";
1079 };
1080
1081 blsp2_uart0: serial@7aef000 {
1082 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1083 reg = <0x07aef000 0x200>;
1084 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1085 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1086 clock-names = "core", "iface";
1087 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1088 dma-names = "tx", "rx";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&blsp2_uart0_default>;
1091 status = "disabled";
1092 };
1093
1094 blsp2_i2c0: i2c@7af5000 {
1095 compatible = "qcom,i2c-qup-v2.2.1";
1096 reg = <0x07af5000 0x600>;
1097 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
1099 <&gcc GCC_BLSP2_AHB_CLK>;
1100 clock-names = "core", "iface";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&blsp2_i2c0_default>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 status = "disabled";
1106 };
1107
1108 blsp2_spi0: spi@7af5000 {
1109 compatible = "qcom,spi-qup-v2.2.1";
1110 reg = <0x07af5000 0x600>;
1111 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1112 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
1113 <&gcc GCC_BLSP2_AHB_CLK>;
1114 clock-names = "core", "iface";
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&blsp2_spi0_default>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 status = "disabled";
1120 };
1121
1122 sram@8600000 {
1123 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1124 reg = <0x08600000 0x1000>;
1125
1126 #address-cells = <1>;
1127 #size-cells = <1>;
1128
1129 ranges = <0 0x08600000 0x1000>;
1130
1131 pil-reloc@94c {
1132 compatible = "qcom,pil-reloc-info";
1133 reg = <0x94c 0xc8>;
1134 };
1135 };
1136
1137 intc: interrupt-controller@b000000 {
1138 compatible = "qcom,msm-qgic2";
1139 interrupt-controller;
1140 #interrupt-cells = <3>;
1141 reg = <0x0b000000 0x1000>,
1142 <0x0b002000 0x1000>;
1143 };
1144
1145 apcs_glb: mailbox@b011000 {
1146 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
1147 reg = <0x0b011000 0x1000>;
1148 #mbox-cells = <1>;
1149 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1150 clock-names = "pll", "aux";
1151 #clock-cells = <0>;
1152 };
1153
1154 apcs_hfpll: clock-controller@b016000 {
1155 compatible = "qcom,hfpll";
1156 reg = <0x0b016000 0x30>;
1157 #clock-cells = <0>;
1158 clock-output-names = "apcs_hfpll";
1159 clocks = <&xo_board>;
1160 clock-names = "xo";
1161 };
1162
1163 watchdog@b017000 {
1164 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1165 reg = <0x0b017000 0x1000>;
1166 clocks = <&sleep_clk>;
1167 };
1168
1169 cpr: power-controller@b018000 {
1170 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1171 reg = <0x0b018000 0x1000>;
1172 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1173 clocks = <&xo_board>;
1174 clock-names = "ref";
1175 vdd-apc-supply = <&pms405_s3>;
1176 #power-domain-cells = <0>;
1177 operating-points-v2 = <&cpr_opp_table>;
1178 acc-syscon = <&tcsr>;
1179
1180 nvmem-cells = <&cpr_efuse_quot_offset1>,
1181 <&cpr_efuse_quot_offset2>,
1182 <&cpr_efuse_quot_offset3>,
1183 <&cpr_efuse_init_voltage1>,
1184 <&cpr_efuse_init_voltage2>,
1185 <&cpr_efuse_init_voltage3>,
1186 <&cpr_efuse_quot1>,
1187 <&cpr_efuse_quot2>,
1188 <&cpr_efuse_quot3>,
1189 <&cpr_efuse_ring1>,
1190 <&cpr_efuse_ring2>,
1191 <&cpr_efuse_ring3>,
1192 <&cpr_efuse_revision>;
1193 nvmem-cell-names = "cpr_quotient_offset1",
1194 "cpr_quotient_offset2",
1195 "cpr_quotient_offset3",
1196 "cpr_init_voltage1",
1197 "cpr_init_voltage2",
1198 "cpr_init_voltage3",
1199 "cpr_quotient1",
1200 "cpr_quotient2",
1201 "cpr_quotient3",
1202 "cpr_ring_osc1",
1203 "cpr_ring_osc2",
1204 "cpr_ring_osc3",
1205 "cpr_fuse_revision";
1206 };
1207
1208 timer@b120000 {
1209 #address-cells = <1>;
1210 #size-cells = <1>;
1211 ranges;
1212 compatible = "arm,armv7-timer-mem";
1213 reg = <0x0b120000 0x1000>;
1214 clock-frequency = <19200000>;
1215
1216 frame@b121000 {
1217 frame-number = <0>;
1218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1220 reg = <0x0b121000 0x1000>,
1221 <0x0b122000 0x1000>;
1222 };
1223
1224 frame@b123000 {
1225 frame-number = <1>;
1226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1227 reg = <0x0b123000 0x1000>;
1228 status = "disabled";
1229 };
1230
1231 frame@b124000 {
1232 frame-number = <2>;
1233 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1234 reg = <0x0b124000 0x1000>;
1235 status = "disabled";
1236 };
1237
1238 frame@b125000 {
1239 frame-number = <3>;
1240 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1241 reg = <0x0b125000 0x1000>;
1242 status = "disabled";
1243 };
1244
1245 frame@b126000 {
1246 frame-number = <4>;
1247 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1248 reg = <0x0b126000 0x1000>;
1249 status = "disabled";
1250 };
1251
1252 frame@b127000 {
1253 frame-number = <5>;
1254 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1255 reg = <0xb127000 0x1000>;
1256 status = "disabled";
1257 };
1258
1259 frame@b128000 {
1260 frame-number = <6>;
1261 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1262 reg = <0x0b128000 0x1000>;
1263 status = "disabled";
1264 };
1265 };
1266
1267 remoteproc_adsp: remoteproc@c700000 {
1268 compatible = "qcom,qcs404-adsp-pas";
1269 reg = <0x0c700000 0x4040>;
1270
1271 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1272 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1273 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1274 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1275 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1276 interrupt-names = "wdog", "fatal", "ready",
1277 "handover", "stop-ack";
1278
1279 clocks = <&xo_board>;
1280 clock-names = "xo";
1281
1282 memory-region = <&adsp_fw_mem>;
1283
1284 qcom,smem-states = <&adsp_smp2p_out 0>;
1285 qcom,smem-state-names = "stop";
1286
1287 status = "disabled";
1288
1289 glink-edge {
1290 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
1291
1292 qcom,remote-pid = <2>;
1293 mboxes = <&apcs_glb 8>;
1294
1295 label = "adsp";
1296 };
1297 };
1298
1299 pcie: pci@10000000 {
1300 compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
1301 reg = <0x10000000 0xf1d>,
1302 <0x10000f20 0xa8>,
1303 <0x07780000 0x2000>,
1304 <0x10001000 0x2000>;
1305 reg-names = "dbi", "elbi", "parf", "config";
1306 device_type = "pci";
1307 linux,pci-domain = <0>;
1308 bus-range = <0x00 0xff>;
1309 num-lanes = <1>;
1310 #address-cells = <3>;
1311 #size-cells = <2>;
1312
1313 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
1314 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
1315
1316 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1317 interrupt-names = "msi";
1318 #interrupt-cells = <1>;
1319 interrupt-map-mask = <0 0 0 0x7>;
1320 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1321 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1322 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1323 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1324 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1325 <&gcc GCC_PCIE_0_AUX_CLK>,
1326 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1327 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1328 clock-names = "iface", "aux", "master_bus", "slave_bus";
1329
1330 resets = <&gcc 18>,
1331 <&gcc 17>,
1332 <&gcc 15>,
1333 <&gcc 19>,
1334 <&gcc GCC_PCIE_0_BCR>,
1335 <&gcc 16>;
1336 reset-names = "axi_m",
1337 "axi_s",
1338 "axi_m_sticky",
1339 "pipe_sticky",
1340 "pwr",
1341 "ahb";
1342
1343 phys = <&pcie_phy>;
1344 phy-names = "pciephy";
1345
1346 status = "disabled";
1347 };
1348 };
1349
1350 timer {
1351 compatible = "arm,armv8-timer";
1352 interrupts = <GIC_PPI 2 0xff08>,
1353 <GIC_PPI 3 0xff08>,
1354 <GIC_PPI 4 0xff08>,
1355 <GIC_PPI 1 0xff08>;
1356 };
1357
1358 smp2p-adsp {
1359 compatible = "qcom,smp2p";
1360 qcom,smem = <443>, <429>;
1361 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
1362 mboxes = <&apcs_glb 10>;
1363 qcom,local-pid = <0>;
1364 qcom,remote-pid = <2>;
1365
1366 adsp_smp2p_out: master-kernel {
1367 qcom,entry-name = "master-kernel";
1368 #qcom,smem-state-cells = <1>;
1369 };
1370
1371 adsp_smp2p_in: slave-kernel {
1372 qcom,entry-name = "slave-kernel";
1373 interrupt-controller;
1374 #interrupt-cells = <2>;
1375 };
1376 };
1377
1378 smp2p-cdsp {
1379 compatible = "qcom,smp2p";
1380 qcom,smem = <94>, <432>;
1381 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
1382 mboxes = <&apcs_glb 14>;
1383 qcom,local-pid = <0>;
1384 qcom,remote-pid = <5>;
1385
1386 cdsp_smp2p_out: master-kernel {
1387 qcom,entry-name = "master-kernel";
1388 #qcom,smem-state-cells = <1>;
1389 };
1390
1391 cdsp_smp2p_in: slave-kernel {
1392 qcom,entry-name = "slave-kernel";
1393 interrupt-controller;
1394 #interrupt-cells = <2>;
1395 };
1396 };
1397
1398 smp2p-wcss {
1399 compatible = "qcom,smp2p";
1400 qcom,smem = <435>, <428>;
1401 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1402 mboxes = <&apcs_glb 18>;
1403 qcom,local-pid = <0>;
1404 qcom,remote-pid = <1>;
1405
1406 wcss_smp2p_out: master-kernel {
1407 qcom,entry-name = "master-kernel";
1408 #qcom,smem-state-cells = <1>;
1409 };
1410
1411 wcss_smp2p_in: slave-kernel {
1412 qcom,entry-name = "slave-kernel";
1413 interrupt-controller;
1414 #interrupt-cells = <2>;
1415 };
1416 };
1417
1418 thermal-zones {
1419 aoss-thermal {
1420 polling-delay-passive = <250>;
1421 polling-delay = <1000>;
1422
1423 thermal-sensors = <&tsens 0>;
1424
1425 trips {
1426 aoss_alert0: trip-point0 {
1427 temperature = <105000>;
1428 hysteresis = <2000>;
1429 type = "hot";
1430 };
1431 };
1432 };
1433
1434 q6-hvx-thermal {
1435 polling-delay-passive = <250>;
1436 polling-delay = <1000>;
1437
1438 thermal-sensors = <&tsens 1>;
1439
1440 trips {
1441 q6_hvx_alert0: trip-point0 {
1442 temperature = <105000>;
1443 hysteresis = <2000>;
1444 type = "hot";
1445 };
1446 };
1447 };
1448
1449 lpass-thermal {
1450 polling-delay-passive = <250>;
1451 polling-delay = <1000>;
1452
1453 thermal-sensors = <&tsens 2>;
1454
1455 trips {
1456 lpass_alert0: trip-point0 {
1457 temperature = <105000>;
1458 hysteresis = <2000>;
1459 type = "hot";
1460 };
1461 };
1462 };
1463
1464 wlan-thermal {
1465 polling-delay-passive = <250>;
1466 polling-delay = <1000>;
1467
1468 thermal-sensors = <&tsens 3>;
1469
1470 trips {
1471 wlan_alert0: trip-point0 {
1472 temperature = <105000>;
1473 hysteresis = <2000>;
1474 type = "hot";
1475 };
1476 };
1477 };
1478
1479 cluster-thermal {
1480 polling-delay-passive = <250>;
1481 polling-delay = <1000>;
1482
1483 thermal-sensors = <&tsens 4>;
1484
1485 trips {
1486 cluster_alert0: trip-point0 {
1487 temperature = <95000>;
1488 hysteresis = <2000>;
1489 type = "hot";
1490 };
1491 cluster_alert1: trip-point1 {
1492 temperature = <105000>;
1493 hysteresis = <2000>;
1494 type = "passive";
1495 };
1496 cluster_crit: cluster_crit {
1497 temperature = <120000>;
1498 hysteresis = <2000>;
1499 type = "critical";
1500 };
1501 };
1502 cooling-maps {
1503 map0 {
1504 trip = <&cluster_alert1>;
1505 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1506 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1507 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1508 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1509 };
1510 };
1511 };
1512
1513 cpu0-thermal {
1514 polling-delay-passive = <250>;
1515 polling-delay = <1000>;
1516
1517 thermal-sensors = <&tsens 5>;
1518
1519 trips {
1520 cpu0_alert0: trip-point0 {
1521 temperature = <95000>;
1522 hysteresis = <2000>;
1523 type = "hot";
1524 };
1525 cpu0_alert1: trip-point1 {
1526 temperature = <105000>;
1527 hysteresis = <2000>;
1528 type = "passive";
1529 };
1530 cpu0_crit: cpu_crit {
1531 temperature = <120000>;
1532 hysteresis = <2000>;
1533 type = "critical";
1534 };
1535 };
1536 cooling-maps {
1537 map0 {
1538 trip = <&cpu0_alert1>;
1539 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1540 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1541 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1542 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1543 };
1544 };
1545 };
1546
1547 cpu1-thermal {
1548 polling-delay-passive = <250>;
1549 polling-delay = <1000>;
1550
1551 thermal-sensors = <&tsens 6>;
1552
1553 trips {
1554 cpu1_alert0: trip-point0 {
1555 temperature = <95000>;
1556 hysteresis = <2000>;
1557 type = "hot";
1558 };
1559 cpu1_alert1: trip-point1 {
1560 temperature = <105000>;
1561 hysteresis = <2000>;
1562 type = "passive";
1563 };
1564 cpu1_crit: cpu_crit {
1565 temperature = <120000>;
1566 hysteresis = <2000>;
1567 type = "critical";
1568 };
1569 };
1570 cooling-maps {
1571 map0 {
1572 trip = <&cpu1_alert1>;
1573 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1574 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1575 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1576 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1577 };
1578 };
1579 };
1580
1581 cpu2-thermal {
1582 polling-delay-passive = <250>;
1583 polling-delay = <1000>;
1584
1585 thermal-sensors = <&tsens 7>;
1586
1587 trips {
1588 cpu2_alert0: trip-point0 {
1589 temperature = <95000>;
1590 hysteresis = <2000>;
1591 type = "hot";
1592 };
1593 cpu2_alert1: trip-point1 {
1594 temperature = <105000>;
1595 hysteresis = <2000>;
1596 type = "passive";
1597 };
1598 cpu2_crit: cpu_crit {
1599 temperature = <120000>;
1600 hysteresis = <2000>;
1601 type = "critical";
1602 };
1603 };
1604 cooling-maps {
1605 map0 {
1606 trip = <&cpu2_alert1>;
1607 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1608 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1609 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1610 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1611 };
1612 };
1613 };
1614
1615 cpu3-thermal {
1616 polling-delay-passive = <250>;
1617 polling-delay = <1000>;
1618
1619 thermal-sensors = <&tsens 8>;
1620
1621 trips {
1622 cpu3_alert0: trip-point0 {
1623 temperature = <95000>;
1624 hysteresis = <2000>;
1625 type = "hot";
1626 };
1627 cpu3_alert1: trip-point1 {
1628 temperature = <105000>;
1629 hysteresis = <2000>;
1630 type = "passive";
1631 };
1632 cpu3_crit: cpu_crit {
1633 temperature = <120000>;
1634 hysteresis = <2000>;
1635 type = "critical";
1636 };
1637 };
1638 cooling-maps {
1639 map0 {
1640 trip = <&cpu3_alert1>;
1641 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1642 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1643 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1644 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1645 };
1646 };
1647 };
1648
1649 gpu-thermal {
1650 polling-delay-passive = <250>;
1651 polling-delay = <1000>;
1652
1653 thermal-sensors = <&tsens 9>;
1654
1655 trips {
1656 gpu_alert0: trip-point0 {
1657 temperature = <95000>;
1658 hysteresis = <2000>;
1659 type = "hot";
1660 };
1661 };
1662 };
1663 };
1664 };
