0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
0003 */
0004
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
0007 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
0008 #include <dt-bindings/clock/qcom,rpmcc.h>
0009 #include <dt-bindings/power/qcom-rpmpd.h>
0010
0011 / {
0012 interrupt-parent = <&intc>;
0013
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 aliases {
0018 mmc1 = &sdhc1;
0019 mmc2 = &sdhc2;
0020 };
0021
0022 chosen { };
0023
0024 clocks {
0025 xo_board: xo-board {
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <19200000>;
0029 clock-output-names = "xo_board";
0030 };
0031
0032 sleep_clk: sleep-clk {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 clock-frequency = <32768>;
0036 clock-output-names = "sleep_clk";
0037 };
0038 };
0039
0040 cpus {
0041 #address-cells = <2>;
0042 #size-cells = <0>;
0043
0044 CPU0: cpu@0 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a53";
0047 reg = <0x0 0x0>;
0048 enable-method = "psci";
0049 next-level-cache = <&L2_0>;
0050 L2_0: l2-cache {
0051 compatible = "cache";
0052 cache-level = <2>;
0053 };
0054 };
0055
0056 CPU1: cpu@1 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a53";
0059 reg = <0x0 0x1>;
0060 enable-method = "psci";
0061 next-level-cache = <&L2_0>;
0062 };
0063
0064 CPU2: cpu@2 {
0065 device_type = "cpu";
0066 compatible = "arm,cortex-a53";
0067 reg = <0x0 0x2>;
0068 enable-method = "psci";
0069 next-level-cache = <&L2_0>;
0070 };
0071
0072 CPU3: cpu@3 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a53";
0075 reg = <0x0 0x3>;
0076 enable-method = "psci";
0077 next-level-cache = <&L2_0>;
0078 };
0079
0080 CPU4: cpu@100 {
0081 device_type = "cpu";
0082 compatible = "arm,cortex-a57";
0083 reg = <0x0 0x100>;
0084 enable-method = "psci";
0085 next-level-cache = <&L2_1>;
0086 L2_1: l2-cache {
0087 compatible = "cache";
0088 cache-level = <2>;
0089 };
0090 };
0091
0092 CPU5: cpu@101 {
0093 device_type = "cpu";
0094 compatible = "arm,cortex-a57";
0095 reg = <0x0 0x101>;
0096 enable-method = "psci";
0097 next-level-cache = <&L2_1>;
0098 };
0099
0100 CPU6: cpu@102 {
0101 device_type = "cpu";
0102 compatible = "arm,cortex-a57";
0103 reg = <0x0 0x102>;
0104 enable-method = "psci";
0105 next-level-cache = <&L2_1>;
0106 };
0107
0108 CPU7: cpu@103 {
0109 device_type = "cpu";
0110 compatible = "arm,cortex-a57";
0111 reg = <0x0 0x103>;
0112 enable-method = "psci";
0113 next-level-cache = <&L2_1>;
0114 };
0115
0116 cpu-map {
0117 cluster0 {
0118 core0 {
0119 cpu = <&CPU0>;
0120 };
0121
0122 core1 {
0123 cpu = <&CPU1>;
0124 };
0125
0126 core2 {
0127 cpu = <&CPU2>;
0128 };
0129
0130 core3 {
0131 cpu = <&CPU3>;
0132 };
0133 };
0134
0135 cluster1 {
0136 core0 {
0137 cpu = <&CPU4>;
0138 };
0139
0140 core1 {
0141 cpu = <&CPU5>;
0142 };
0143
0144 cpu6_map: core2 {
0145 cpu = <&CPU6>;
0146 };
0147
0148 cpu7_map: core3 {
0149 cpu = <&CPU7>;
0150 };
0151 };
0152 };
0153 };
0154
0155 firmware {
0156 scm {
0157 compatible = "qcom,scm-msm8994", "qcom,scm";
0158 };
0159 };
0160
0161 memory@80000000 {
0162 device_type = "memory";
0163 /* We expect the bootloader to fill in the reg */
0164 reg = <0 0x80000000 0 0>;
0165 };
0166
0167 tcsr_mutex: hwlock {
0168 compatible = "qcom,tcsr-mutex";
0169 syscon = <&tcsr_mutex_regs 0 0x80>;
0170 #hwlock-cells = <1>;
0171 };
0172
0173 pmu {
0174 compatible = "arm,cortex-a53-pmu";
0175 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
0176 };
0177
0178 psci {
0179 compatible = "arm,psci-0.2";
0180 method = "hvc";
0181 };
0182
0183 reserved-memory {
0184 #address-cells = <2>;
0185 #size-cells = <2>;
0186 ranges;
0187
0188 dfps_data_mem: dfps_data_mem@3400000 {
0189 reg = <0 0x03400000 0 0x1000>;
0190 no-map;
0191 };
0192
0193 cont_splash_mem: memory@3401000 {
0194 reg = <0 0x03401000 0 0x2200000>;
0195 no-map;
0196 };
0197
0198 smem_mem: smem_region@6a00000 {
0199 reg = <0 0x06a00000 0 0x200000>;
0200 no-map;
0201 };
0202
0203 mpss_mem: memory@7000000 {
0204 reg = <0 0x07000000 0 0x5a00000>;
0205 no-map;
0206 };
0207
0208 peripheral_region: memory@ca00000 {
0209 reg = <0 0x0ca00000 0 0x1f00000>;
0210 no-map;
0211 };
0212
0213 rmtfs_mem: memory@c6400000 {
0214 compatible = "qcom,rmtfs-mem";
0215 reg = <0 0xc6400000 0 0x180000>;
0216 no-map;
0217
0218 qcom,client-id = <1>;
0219 };
0220
0221 mba_mem: memory@c6700000 {
0222 reg = <0 0xc6700000 0 0x100000>;
0223 no-map;
0224 };
0225
0226 audio_mem: memory@c7000000 {
0227 reg = <0 0xc7000000 0 0x800000>;
0228 no-map;
0229 };
0230
0231 adsp_mem: memory@c9400000 {
0232 reg = <0 0xc9400000 0 0x3f00000>;
0233 no-map;
0234 };
0235 };
0236
0237 smd {
0238 compatible = "qcom,smd";
0239 rpm {
0240 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0241 qcom,ipc = <&apcs 8 0>;
0242 qcom,smd-edge = <15>;
0243 qcom,remote-pid = <6>;
0244
0245 rpm_requests: rpm-requests {
0246 compatible = "qcom,rpm-msm8994";
0247 qcom,smd-channels = "rpm_requests";
0248
0249 rpmcc: rpmcc {
0250 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
0251 #clock-cells = <1>;
0252 };
0253
0254 rpmpd: power-controller {
0255 compatible = "qcom,msm8994-rpmpd";
0256 #power-domain-cells = <1>;
0257 operating-points-v2 = <&rpmpd_opp_table>;
0258
0259 rpmpd_opp_table: opp-table {
0260 compatible = "operating-points-v2";
0261
0262 rpmpd_opp_ret: opp1 {
0263 opp-level = <1>;
0264 };
0265 rpmpd_opp_svs_krait: opp2 {
0266 opp-level = <2>;
0267 };
0268 rpmpd_opp_svs_soc: opp3 {
0269 opp-level = <3>;
0270 };
0271 rpmpd_opp_nom: opp4 {
0272 opp-level = <4>;
0273 };
0274 rpmpd_opp_turbo: opp5 {
0275 opp-level = <5>;
0276 };
0277 rpmpd_opp_super_turbo: opp6 {
0278 opp-level = <6>;
0279 };
0280 };
0281 };
0282 };
0283 };
0284 };
0285
0286 smem {
0287 compatible = "qcom,smem";
0288 memory-region = <&smem_mem>;
0289 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0290 hwlocks = <&tcsr_mutex 3>;
0291 };
0292
0293 smp2p-lpass {
0294 compatible = "qcom,smp2p";
0295 qcom,smem = <443>, <429>;
0296
0297 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
0298
0299 qcom,ipc = <&apcs 8 10>;
0300
0301 qcom,local-pid = <0>;
0302 qcom,remote-pid = <2>;
0303
0304 adsp_smp2p_out: master-kernel {
0305 qcom,entry-name = "master-kernel";
0306 #qcom,smem-state-cells = <1>;
0307 };
0308
0309 adsp_smp2p_in: slave-kernel {
0310 qcom,entry-name = "slave-kernel";
0311
0312 interrupt-controller;
0313 #interrupt-cells = <2>;
0314 };
0315 };
0316
0317 smp2p-modem {
0318 compatible = "qcom,smp2p";
0319 qcom,smem = <435>, <428>;
0320
0321 interrupt-parent = <&intc>;
0322 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
0323
0324 qcom,ipc = <&apcs 8 14>;
0325
0326 qcom,local-pid = <0>;
0327 qcom,remote-pid = <1>;
0328
0329 modem_smp2p_out: master-kernel {
0330 qcom,entry-name = "master-kernel";
0331 #qcom,smem-state-cells = <1>;
0332 };
0333
0334 modem_smp2p_in: slave-kernel {
0335 qcom,entry-name = "slave-kernel";
0336
0337 interrupt-controller;
0338 #interrupt-cells = <2>;
0339 };
0340 };
0341
0342 soc: soc {
0343
0344 #address-cells = <1>;
0345 #size-cells = <1>;
0346 ranges = <0 0 0 0xffffffff>;
0347 compatible = "simple-bus";
0348
0349 intc: interrupt-controller@f9000000 {
0350 compatible = "qcom,msm-qgic2";
0351 interrupt-controller;
0352 #interrupt-cells = <3>;
0353 reg = <0xf9000000 0x1000>,
0354 <0xf9002000 0x1000>;
0355 };
0356
0357 apcs: mailbox@f900d000 {
0358 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
0359 reg = <0xf900d000 0x2000>;
0360 #mbox-cells = <1>;
0361 };
0362
0363 watchdog@f9017000 {
0364 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
0365 reg = <0xf9017000 0x1000>;
0366 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
0367 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
0368 clocks = <&sleep_clk>;
0369 timeout-sec = <10>;
0370 };
0371
0372 timer@f9020000 {
0373 #address-cells = <1>;
0374 #size-cells = <1>;
0375 ranges;
0376 compatible = "arm,armv7-timer-mem";
0377 reg = <0xf9020000 0x1000>;
0378
0379 frame@f9021000 {
0380 frame-number = <0>;
0381 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0382 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0383 reg = <0xf9021000 0x1000>,
0384 <0xf9022000 0x1000>;
0385 };
0386
0387 frame@f9023000 {
0388 frame-number = <1>;
0389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0390 reg = <0xf9023000 0x1000>;
0391 status = "disabled";
0392 };
0393
0394 frame@f9024000 {
0395 frame-number = <2>;
0396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0397 reg = <0xf9024000 0x1000>;
0398 status = "disabled";
0399 };
0400
0401 frame@f9025000 {
0402 frame-number = <3>;
0403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0404 reg = <0xf9025000 0x1000>;
0405 status = "disabled";
0406 };
0407
0408 frame@f9026000 {
0409 frame-number = <4>;
0410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0411 reg = <0xf9026000 0x1000>;
0412 status = "disabled";
0413 };
0414
0415 frame@f9027000 {
0416 frame-number = <5>;
0417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0418 reg = <0xf9027000 0x1000>;
0419 status = "disabled";
0420 };
0421
0422 frame@f9028000 {
0423 frame-number = <6>;
0424 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0425 reg = <0xf9028000 0x1000>;
0426 status = "disabled";
0427 };
0428 };
0429
0430 usb3: usb@f92f8800 {
0431 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
0432 reg = <0xf92f8800 0x400>;
0433 #address-cells = <1>;
0434 #size-cells = <1>;
0435 ranges;
0436
0437 clocks = <&gcc GCC_USB30_MASTER_CLK>,
0438 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
0439 <&gcc GCC_USB30_SLEEP_CLK>,
0440 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
0441 clock-names = "core",
0442 "iface",
0443 "sleep",
0444 "mock_utmi";
0445
0446 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
0447 <&gcc GCC_USB30_MASTER_CLK>;
0448 assigned-clock-rates = <19200000>, <120000000>;
0449
0450 power-domains = <&gcc USB30_GDSC>;
0451 qcom,select-utmi-as-pipe-clk;
0452
0453 usb@f9200000 {
0454 compatible = "snps,dwc3";
0455 reg = <0xf9200000 0xcc00>;
0456 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
0457 snps,dis_u2_susphy_quirk;
0458 snps,dis_enblslpm_quirk;
0459 maximum-speed = "high-speed";
0460 dr_mode = "peripheral";
0461 };
0462 };
0463
0464 sdhc1: mmc@f9824900 {
0465 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
0466 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
0467 reg-names = "hc_mem", "core_mem";
0468
0469 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0471 interrupt-names = "hc_irq", "pwr_irq";
0472
0473 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0474 <&gcc GCC_SDCC1_APPS_CLK>,
0475 <&xo_board>;
0476 clock-names = "iface", "core", "xo";
0477
0478 pinctrl-names = "default", "sleep";
0479 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
0480 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
0481
0482 bus-width = <8>;
0483 non-removable;
0484 status = "disabled";
0485 };
0486
0487 sdhc2: mmc@f98a4900 {
0488 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
0489 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
0490 reg-names = "hc_mem", "core_mem";
0491
0492 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0493 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0494 interrupt-names = "hc_irq", "pwr_irq";
0495
0496 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
0497 <&gcc GCC_SDCC2_APPS_CLK>,
0498 <&xo_board>;
0499 clock-names = "iface", "core", "xo";
0500
0501 pinctrl-names = "default", "sleep";
0502 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
0503 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
0504
0505 cd-gpios = <&tlmm 100 0>;
0506 bus-width = <4>;
0507 status = "disabled";
0508 };
0509
0510 blsp1_dma: dma-controller@f9904000 {
0511 compatible = "qcom,bam-v1.7.0";
0512 reg = <0xf9904000 0x19000>;
0513 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
0514 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
0515 clock-names = "bam_clk";
0516 #dma-cells = <1>;
0517 qcom,ee = <0>;
0518 qcom,controlled-remotely;
0519 num-channels = <24>;
0520 qcom,num-ees = <4>;
0521 };
0522
0523 blsp1_uart2: serial@f991e000 {
0524 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0525 reg = <0xf991e000 0x1000>;
0526 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0527 clock-names = "core", "iface";
0528 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
0529 <&gcc GCC_BLSP1_AHB_CLK>;
0530 pinctrl-names = "default", "sleep";
0531 pinctrl-0 = <&blsp1_uart2_default>;
0532 pinctrl-1 = <&blsp1_uart2_sleep>;
0533 status = "disabled";
0534 };
0535
0536 blsp1_i2c1: i2c@f9923000 {
0537 compatible = "qcom,i2c-qup-v2.2.1";
0538 reg = <0xf9923000 0x500>;
0539 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0540 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
0541 <&gcc GCC_BLSP1_AHB_CLK>;
0542 clock-names = "core", "iface";
0543 clock-frequency = <400000>;
0544 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
0545 dma-names = "tx", "rx";
0546 pinctrl-names = "default", "sleep";
0547 pinctrl-0 = <&i2c1_default>;
0548 pinctrl-1 = <&i2c1_sleep>;
0549 #address-cells = <1>;
0550 #size-cells = <0>;
0551 status = "disabled";
0552 };
0553
0554 blsp1_spi1: spi@f9923000 {
0555 compatible = "qcom,spi-qup-v2.2.1";
0556 reg = <0xf9923000 0x500>;
0557 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0558 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
0559 <&gcc GCC_BLSP1_AHB_CLK>;
0560 clock-names = "core", "iface";
0561 spi-max-frequency = <19200000>;
0562 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
0563 dma-names = "tx", "rx";
0564 pinctrl-names = "default", "sleep";
0565 pinctrl-0 = <&blsp1_spi1_default>;
0566 pinctrl-1 = <&blsp1_spi1_sleep>;
0567 #address-cells = <1>;
0568 #size-cells = <0>;
0569 status = "disabled";
0570 };
0571
0572 blsp1_i2c2: i2c@f9924000 {
0573 compatible = "qcom,i2c-qup-v2.2.1";
0574 reg = <0xf9924000 0x500>;
0575 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0576 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
0577 <&gcc GCC_BLSP1_AHB_CLK>;
0578 clock-names = "core", "iface";
0579 clock-frequency = <400000>;
0580 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
0581 dma-names = "tx", "rx";
0582 pinctrl-names = "default", "sleep";
0583 pinctrl-0 = <&i2c2_default>;
0584 pinctrl-1 = <&i2c2_sleep>;
0585 #address-cells = <1>;
0586 #size-cells = <0>;
0587 status = "disabled";
0588 };
0589
0590 /* I2C3 doesn't exist */
0591
0592 blsp1_i2c4: i2c@f9926000 {
0593 compatible = "qcom,i2c-qup-v2.2.1";
0594 reg = <0xf9926000 0x500>;
0595 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0596 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
0597 <&gcc GCC_BLSP1_AHB_CLK>;
0598 clock-names = "core", "iface";
0599 clock-frequency = <400000>;
0600 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
0601 dma-names = "tx", "rx";
0602 pinctrl-names = "default", "sleep";
0603 pinctrl-0 = <&i2c4_default>;
0604 pinctrl-1 = <&i2c4_sleep>;
0605 #address-cells = <1>;
0606 #size-cells = <0>;
0607 status = "disabled";
0608 };
0609
0610 blsp1_i2c5: i2c@f9927000 {
0611 compatible = "qcom,i2c-qup-v2.2.1";
0612 reg = <0xf9927000 0x500>;
0613 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0614 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
0615 <&gcc GCC_BLSP1_AHB_CLK>;
0616 clock-names = "core", "iface";
0617 clock-frequency = <400000>;
0618 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
0619 dma-names = "tx", "rx";
0620 pinctrl-names = "default", "sleep";
0621 pinctrl-0 = <&i2c5_default>;
0622 pinctrl-1 = <&i2c5_sleep>;
0623 #address-cells = <1>;
0624 #size-cells = <0>;
0625 status = "disabled";
0626 };
0627
0628 blsp1_i2c6: i2c@f9928000 {
0629 compatible = "qcom,i2c-qup-v2.2.1";
0630 reg = <0xf9928000 0x500>;
0631 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0632 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
0633 <&gcc GCC_BLSP1_AHB_CLK>;
0634 clock-names = "core", "iface";
0635 clock-frequency = <400000>;
0636 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
0637 dma-names = "tx", "rx";
0638 pinctrl-names = "default", "sleep";
0639 pinctrl-0 = <&i2c6_default>;
0640 pinctrl-1 = <&i2c6_sleep>;
0641 #address-cells = <1>;
0642 #size-cells = <0>;
0643 status = "disabled";
0644 };
0645
0646 blsp2_dma: dma-controller@f9944000 {
0647 compatible = "qcom,bam-v1.7.0";
0648 reg = <0xf9944000 0x19000>;
0649 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
0650 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
0651 clock-names = "bam_clk";
0652 #dma-cells = <1>;
0653 qcom,ee = <0>;
0654 qcom,controlled-remotely;
0655 num-channels = <24>;
0656 qcom,num-ees = <4>;
0657 };
0658
0659 blsp2_uart2: serial@f995e000 {
0660 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0661 reg = <0xf995e000 0x1000>;
0662 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0663 clock-names = "core", "iface";
0664 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
0665 <&gcc GCC_BLSP2_AHB_CLK>;
0666 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
0667 dma-names = "tx", "rx";
0668 pinctrl-names = "default", "sleep";
0669 pinctrl-0 = <&blsp2_uart2_default>;
0670 pinctrl-1 = <&blsp2_uart2_sleep>;
0671 status = "disabled";
0672 };
0673
0674 blsp2_i2c1: i2c@f9963000 {
0675 compatible = "qcom,i2c-qup-v2.2.1";
0676 reg = <0xf9963000 0x500>;
0677 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0678 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
0679 <&gcc GCC_BLSP2_AHB_CLK>;
0680 clock-names = "core", "iface";
0681 clock-frequency = <400000>;
0682 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
0683 dma-names = "tx", "rx";
0684 pinctrl-names = "default", "sleep";
0685 pinctrl-0 = <&i2c7_default>;
0686 pinctrl-1 = <&i2c7_sleep>;
0687 #address-cells = <1>;
0688 #size-cells = <0>;
0689 status = "disabled";
0690 };
0691
0692 blsp2_spi4: spi@f9966000 {
0693 compatible = "qcom,spi-qup-v2.2.1";
0694 reg = <0xf9966000 0x500>;
0695 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0696 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
0697 <&gcc GCC_BLSP2_AHB_CLK>;
0698 clock-names = "core", "iface";
0699 spi-max-frequency = <19200000>;
0700 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
0701 dma-names = "tx", "rx";
0702 pinctrl-names = "default", "sleep";
0703 pinctrl-0 = <&blsp2_spi10_default>;
0704 pinctrl-1 = <&blsp2_spi10_sleep>;
0705 #address-cells = <1>;
0706 #size-cells = <0>;
0707 status = "disabled";
0708 };
0709
0710 blsp2_i2c5: i2c@f9967000 {
0711 compatible = "qcom,i2c-qup-v2.2.1";
0712 reg = <0xf9967000 0x500>;
0713 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0714 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
0715 <&gcc GCC_BLSP2_AHB_CLK>;
0716 clock-names = "core", "iface";
0717 clock-frequency = <355000>;
0718 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
0719 dma-names = "tx", "rx";
0720 pinctrl-names = "default", "sleep";
0721 pinctrl-0 = <&i2c11_default>;
0722 pinctrl-1 = <&i2c11_sleep>;
0723 #address-cells = <1>;
0724 #size-cells = <0>;
0725 status = "disabled";
0726 };
0727
0728 gcc: clock-controller@fc400000 {
0729 compatible = "qcom,gcc-msm8994";
0730 #clock-cells = <1>;
0731 #reset-cells = <1>;
0732 #power-domain-cells = <1>;
0733 reg = <0xfc400000 0x2000>;
0734
0735 clock-names = "xo", "sleep";
0736 clocks = <&xo_board>, <&sleep_clk>;
0737 };
0738
0739 rpm_msg_ram: sram@fc428000 {
0740 compatible = "qcom,rpm-msg-ram";
0741 reg = <0xfc428000 0x4000>;
0742 };
0743
0744 restart@fc4ab000 {
0745 compatible = "qcom,pshold";
0746 reg = <0xfc4ab000 0x4>;
0747 };
0748
0749 spmi_bus: spmi@fc4c0000 {
0750 compatible = "qcom,spmi-pmic-arb";
0751 reg = <0xfc4cf000 0x1000>,
0752 <0xfc4cb000 0x1000>,
0753 <0xfc4ca000 0x1000>;
0754 reg-names = "core", "intr", "cnfg";
0755 interrupt-names = "periph_irq";
0756 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0757 qcom,ee = <0>;
0758 qcom,channel = <0>;
0759 #address-cells = <2>;
0760 #size-cells = <0>;
0761 interrupt-controller;
0762 #interrupt-cells = <4>;
0763 };
0764
0765 tcsr_mutex_regs: syscon@fd484000 {
0766 compatible = "syscon";
0767 reg = <0xfd484000 0x2000>;
0768 };
0769
0770 tlmm: pinctrl@fd510000 {
0771 compatible = "qcom,msm8994-pinctrl";
0772 reg = <0xfd510000 0x4000>;
0773 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0774 gpio-controller;
0775 gpio-ranges = <&tlmm 0 0 146>;
0776 #gpio-cells = <2>;
0777 interrupt-controller;
0778 #interrupt-cells = <2>;
0779
0780 blsp1_uart2_default: blsp1-uart2-default {
0781 function = "blsp_uart2";
0782 pins = "gpio4", "gpio5";
0783 drive-strength = <16>;
0784 bias-disable;
0785 };
0786
0787 blsp1_uart2_sleep: blsp1-uart2-sleep {
0788 function = "gpio";
0789 pins = "gpio4", "gpio5";
0790 drive-strength = <2>;
0791 bias-pull-down;
0792 };
0793
0794 blsp2_uart2_default: blsp2-uart2-default {
0795 function = "blsp_uart8";
0796 pins = "gpio45", "gpio46",
0797 "gpio47", "gpio48";
0798 drive-strength = <16>;
0799 bias-disable;
0800 };
0801
0802 blsp2_uart2_sleep: blsp2-uart2-sleep {
0803 function = "gpio";
0804 pins = "gpio45", "gpio46",
0805 "gpio47", "gpio48";
0806 drive-strength = <2>;
0807 bias-disable;
0808 };
0809
0810 i2c1_default: i2c1-default {
0811 function = "blsp_i2c1";
0812 pins = "gpio2", "gpio3";
0813 drive-strength = <2>;
0814 bias-disable;
0815 };
0816
0817 i2c1_sleep: i2c1-sleep {
0818 function = "gpio";
0819 pins = "gpio2", "gpio3";
0820 drive-strength = <2>;
0821 bias-disable;
0822 };
0823
0824 i2c2_default: i2c2-default {
0825 function = "blsp_i2c2";
0826 pins = "gpio6", "gpio7";
0827 drive-strength = <2>;
0828 bias-disable;
0829 };
0830
0831 i2c2_sleep: i2c2-sleep {
0832 function = "gpio";
0833 pins = "gpio6", "gpio7";
0834 drive-strength = <2>;
0835 bias-disable;
0836 };
0837
0838 i2c4_default: i2c4-default {
0839 function = "blsp_i2c4";
0840 pins = "gpio19", "gpio20";
0841 drive-strength = <2>;
0842 bias-disable;
0843 };
0844
0845 i2c4_sleep: i2c4-sleep {
0846 function = "gpio";
0847 pins = "gpio19", "gpio20";
0848 drive-strength = <2>;
0849 bias-pull-down;
0850 input-enable;
0851 };
0852
0853 i2c5_default: i2c5-default {
0854 function = "blsp_i2c5";
0855 pins = "gpio23", "gpio24";
0856 drive-strength = <2>;
0857 bias-disable;
0858 };
0859
0860 i2c5_sleep: i2c5-sleep {
0861 function = "gpio";
0862 pins = "gpio23", "gpio24";
0863 drive-strength = <2>;
0864 bias-disable;
0865 };
0866
0867 i2c6_default: i2c6-default {
0868 function = "blsp_i2c6";
0869 pins = "gpio28", "gpio27";
0870 drive-strength = <2>;
0871 bias-disable;
0872 };
0873
0874 i2c6_sleep: i2c6-sleep {
0875 function = "gpio";
0876 pins = "gpio28", "gpio27";
0877 drive-strength = <2>;
0878 bias-disable;
0879 };
0880
0881 i2c7_default: i2c7-default {
0882 function = "blsp_i2c7";
0883 pins = "gpio44", "gpio43";
0884 drive-strength = <2>;
0885 bias-disable;
0886 };
0887
0888 i2c7_sleep: i2c7-sleep {
0889 function = "gpio";
0890 pins = "gpio44", "gpio43";
0891 drive-strength = <2>;
0892 bias-disable;
0893 };
0894
0895 blsp2_spi10_default: blsp2-spi10-default {
0896 default {
0897 function = "blsp_spi10";
0898 pins = "gpio53", "gpio54", "gpio55";
0899 drive-strength = <10>;
0900 bias-pull-down;
0901 };
0902 cs {
0903 function = "gpio";
0904 pins = "gpio55";
0905 drive-strength = <2>;
0906 bias-disable;
0907 };
0908 };
0909
0910 blsp2_spi10_sleep: blsp2-spi10-sleep {
0911 pins = "gpio53", "gpio54", "gpio55";
0912 drive-strength = <2>;
0913 bias-disable;
0914 };
0915
0916 i2c11_default: i2c11-default {
0917 function = "blsp_i2c11";
0918 pins = "gpio83", "gpio84";
0919 drive-strength = <2>;
0920 bias-disable;
0921 };
0922
0923 i2c11_sleep: i2c11-sleep {
0924 function = "gpio";
0925 pins = "gpio83", "gpio84";
0926 drive-strength = <2>;
0927 bias-disable;
0928 };
0929
0930 blsp1_spi1_default: blsp1-spi1-default {
0931 default {
0932 function = "blsp_spi1";
0933 pins = "gpio0", "gpio1", "gpio3";
0934 drive-strength = <10>;
0935 bias-pull-down;
0936 };
0937 cs {
0938 function = "gpio";
0939 pins = "gpio8";
0940 drive-strength = <2>;
0941 bias-disable;
0942 };
0943 };
0944
0945 blsp1_spi1_sleep: blsp1-spi1-sleep {
0946 pins = "gpio0", "gpio1", "gpio3";
0947 drive-strength = <2>;
0948 bias-disable;
0949 };
0950
0951 sdc1_clk_on: clk-on {
0952 pins = "sdc1_clk";
0953 bias-disable;
0954 drive-strength = <16>;
0955 };
0956
0957 sdc1_clk_off: clk-off {
0958 pins = "sdc1_clk";
0959 bias-disable;
0960 drive-strength = <2>;
0961 };
0962
0963 sdc1_cmd_on: cmd-on {
0964 pins = "sdc1_cmd";
0965 bias-pull-up;
0966 drive-strength = <8>;
0967 };
0968
0969 sdc1_cmd_off: cmd-off {
0970 pins = "sdc1_cmd";
0971 bias-pull-up;
0972 drive-strength = <2>;
0973 };
0974
0975 sdc1_data_on: data-on {
0976 pins = "sdc1_data";
0977 bias-pull-up;
0978 drive-strength = <8>;
0979 };
0980
0981 sdc1_data_off: data-off {
0982 pins = "sdc1_data";
0983 bias-pull-up;
0984 drive-strength = <2>;
0985 };
0986
0987 sdc1_rclk_on: rclk-on {
0988 pins = "sdc1_rclk";
0989 bias-pull-down;
0990 };
0991
0992 sdc1_rclk_off: rclk-off {
0993 pins = "sdc1_rclk";
0994 bias-pull-down;
0995 };
0996
0997 sdc2_clk_on: sdc2-clk-on {
0998 pins = "sdc2_clk";
0999 bias-disable;
1000 drive-strength = <10>;
1001 };
1002
1003 sdc2_clk_off: sdc2-clk-off {
1004 pins = "sdc2_clk";
1005 bias-disable;
1006 drive-strength = <2>;
1007 };
1008
1009 sdc2_cmd_on: sdc2-cmd-on {
1010 pins = "sdc2_cmd";
1011 bias-pull-up;
1012 drive-strength = <10>;
1013 };
1014
1015 sdc2_cmd_off: sdc2-cmd-off {
1016 pins = "sdc2_cmd";
1017 bias-pull-up;
1018 drive-strength = <2>;
1019 };
1020
1021 sdc2_data_on: sdc2-data-on {
1022 pins = "sdc2_data";
1023 bias-pull-up;
1024 drive-strength = <10>;
1025 };
1026
1027 sdc2_data_off: sdc2-data-off {
1028 pins = "sdc2_data";
1029 bias-pull-up;
1030 drive-strength = <2>;
1031 };
1032 };
1033
1034 mmcc: clock-controller@fd8c0000 {
1035 compatible = "qcom,mmcc-msm8994";
1036 reg = <0xfd8c0000 0x5200>;
1037 #clock-cells = <1>;
1038 #reset-cells = <1>;
1039 #power-domain-cells = <1>;
1040
1041 clock-names = "xo",
1042 "gpll0",
1043 "mmssnoc_ahb",
1044 "oxili_gfx3d_clk_src",
1045 "dsi0pll",
1046 "dsi0pllbyte",
1047 "dsi1pll",
1048 "dsi1pllbyte",
1049 "hdmipll";
1050 clocks = <&xo_board>,
1051 <&gcc GPLL0_OUT_MMSSCC>,
1052 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1053 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1054 <0>,
1055 <0>,
1056 <0>,
1057 <0>,
1058 <0>;
1059
1060 assigned-clocks = <&mmcc MMPLL0_PLL>,
1061 <&mmcc MMPLL1_PLL>,
1062 <&mmcc MMPLL3_PLL>,
1063 <&mmcc MMPLL4_PLL>,
1064 <&mmcc MMPLL5_PLL>;
1065 assigned-clock-rates = <800000000>,
1066 <1167000000>,
1067 <1020000000>,
1068 <960000000>,
1069 <600000000>;
1070 };
1071
1072 ocmem: sram@fdd00000 {
1073 compatible = "qcom,msm8974-ocmem";
1074 reg = <0xfdd00000 0x2000>,
1075 <0xfec00000 0x200000>;
1076 reg-names = "ctrl", "mem";
1077 ranges = <0 0xfec00000 0x200000>;
1078 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1079 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1080 clock-names = "core", "iface";
1081
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084
1085 gmu_sram: gmu-sram@0 {
1086 reg = <0x0 0x180000>;
1087 };
1088 };
1089 };
1090
1091 timer: timer {
1092 compatible = "arm,armv8-timer";
1093 interrupts = <GIC_PPI 2 0xff08>,
1094 <GIC_PPI 3 0xff08>,
1095 <GIC_PPI 4 0xff08>,
1096 <GIC_PPI 1 0xff08>;
1097 };
1098
1099 vph_pwr: vph-pwr-regulator {
1100 compatible = "regulator-fixed";
1101 regulator-name = "vph_pwr";
1102
1103 regulator-min-microvolt = <3600000>;
1104 regulator-max-microvolt = <3600000>;
1105
1106 regulator-always-on;
1107 };
1108 };
1109
