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0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
0003
0004 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
0005 #include <dt-bindings/gpio/gpio.h>
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/power/qcom-rpmpd.h>
0008 #include <dt-bindings/thermal/thermal.h>
0009
0010 / {
0011 interrupt-parent = <&intc>;
0012
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 chosen { };
0017
0018 clocks {
0019 sleep_clk: sleep-clk {
0020 compatible = "fixed-clock";
0021 #clock-cells = <0>;
0022 clock-frequency = <32768>;
0023 };
0024
0025 xo_board: xo-board {
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <19200000>;
0029 clock-output-names = "xo";
0030 };
0031 };
0032
0033 cpus {
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036
0037 CPU0: cpu@0 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a53";
0040 reg = <0x0>;
0041 enable-method = "psci";
0042 capacity-dmips-mhz = <1024>;
0043 next-level-cache = <&L2_0>;
0044 #cooling-cells = <2>;
0045
0046 l1-icache {
0047 compatible = "cache";
0048 };
0049 l1-dcache {
0050 compatible = "cache";
0051 };
0052 };
0053
0054 CPU1: cpu@1 {
0055 device_type = "cpu";
0056 compatible = "arm,cortex-a53";
0057 reg = <0x1>;
0058 enable-method = "psci";
0059 capacity-dmips-mhz = <1024>;
0060 next-level-cache = <&L2_0>;
0061 #cooling-cells = <2>;
0062
0063 l1-icache {
0064 compatible = "cache";
0065 };
0066 l1-dcache {
0067 compatible = "cache";
0068 };
0069 };
0070
0071 CPU2: cpu@2 {
0072 device_type = "cpu";
0073 compatible = "arm,cortex-a53";
0074 reg = <0x2>;
0075 enable-method = "psci";
0076 capacity-dmips-mhz = <1024>;
0077 next-level-cache = <&L2_0>;
0078 #cooling-cells = <2>;
0079
0080 l1-icache {
0081 compatible = "cache";
0082 };
0083 l1-dcache {
0084 compatible = "cache";
0085 };
0086 };
0087
0088 CPU3: cpu@3 {
0089 device_type = "cpu";
0090 compatible = "arm,cortex-a53";
0091 reg = <0x3>;
0092 enable-method = "psci";
0093 capacity-dmips-mhz = <1024>;
0094 next-level-cache = <&L2_0>;
0095 #cooling-cells = <2>;
0096
0097 l1-icache {
0098 compatible = "cache";
0099 };
0100 l1-dcache {
0101 compatible = "cache";
0102 };
0103 };
0104
0105 CPU4: cpu@100 {
0106 device_type = "cpu";
0107 compatible = "arm,cortex-a53";
0108 reg = <0x100>;
0109 enable-method = "psci";
0110 capacity-dmips-mhz = <1024>;
0111 next-level-cache = <&L2_1>;
0112 #cooling-cells = <2>;
0113
0114 l1-icache {
0115 compatible = "cache";
0116 };
0117 l1-dcache {
0118 compatible = "cache";
0119 };
0120 };
0121
0122 CPU5: cpu@101 {
0123 device_type = "cpu";
0124 compatible = "arm,cortex-a53";
0125 reg = <0x101>;
0126 enable-method = "psci";
0127 capacity-dmips-mhz = <1024>;
0128 next-level-cache = <&L2_1>;
0129 #cooling-cells = <2>;
0130
0131 l1-icache {
0132 compatible = "cache";
0133 };
0134 l1-dcache {
0135 compatible = "cache";
0136 };
0137 };
0138
0139 CPU6: cpu@102 {
0140 device_type = "cpu";
0141 compatible = "arm,cortex-a53";
0142 reg = <0x102>;
0143 enable-method = "psci";
0144 capacity-dmips-mhz = <1024>;
0145 next-level-cache = <&L2_1>;
0146 #cooling-cells = <2>;
0147
0148 l1-icache {
0149 compatible = "cache";
0150 };
0151 l1-dcache {
0152 compatible = "cache";
0153 };
0154 };
0155
0156 CPU7: cpu@103 {
0157 device_type = "cpu";
0158 compatible = "arm,cortex-a53";
0159 reg = <0x103>;
0160 enable-method = "psci";
0161 capacity-dmips-mhz = <1024>;
0162 next-level-cache = <&L2_1>;
0163 #cooling-cells = <2>;
0164
0165 l1-icache {
0166 compatible = "cache";
0167 };
0168 l1-dcache {
0169 compatible = "cache";
0170 };
0171 };
0172
0173 cpu-map {
0174 cluster0 {
0175 core0 {
0176 cpu = <&CPU0>;
0177 };
0178 core1 {
0179 cpu = <&CPU1>;
0180 };
0181 core2 {
0182 cpu = <&CPU2>;
0183 };
0184 core3 {
0185 cpu = <&CPU3>;
0186 };
0187 };
0188
0189 cluster1 {
0190 core0 {
0191 cpu = <&CPU4>;
0192 };
0193 core1 {
0194 cpu = <&CPU5>;
0195 };
0196 core2 {
0197 cpu = <&CPU6>;
0198 };
0199 core3 {
0200 cpu = <&CPU7>;
0201 };
0202 };
0203 };
0204
0205 L2_0: l2-cache_0 {
0206 compatible = "cache";
0207 cache-level = <2>;
0208 };
0209
0210 L2_1: l2-cache_1 {
0211 compatible = "cache";
0212 cache-level = <2>;
0213 };
0214 };
0215
0216 firmware {
0217 scm: scm {
0218 compatible = "qcom,scm-msm8953", "qcom,scm";
0219 clocks = <&gcc GCC_CRYPTO_CLK>,
0220 <&gcc GCC_CRYPTO_AXI_CLK>,
0221 <&gcc GCC_CRYPTO_AHB_CLK>;
0222 clock-names = "core", "bus", "iface";
0223 #reset-cells = <1>;
0224 };
0225 };
0226
0227 memory {
0228 device_type = "memory";
0229 /* We expect the bootloader to fill in the reg */
0230 reg = <0 0 0 0>;
0231 };
0232
0233 pmu {
0234 compatible = "arm,cortex-a53-pmu";
0235 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
0236 };
0237
0238 psci {
0239 compatible = "arm,psci-1.0";
0240 method = "smc";
0241 };
0242
0243 reserved-memory {
0244 #address-cells = <2>;
0245 #size-cells = <2>;
0246 ranges;
0247
0248 zap_shader_region: memory@81800000 {
0249 compatible = "shared-dma-pool";
0250 reg = <0x0 0x81800000 0x0 0x2000>;
0251 no-map;
0252 };
0253
0254 memory@85b00000 {
0255 reg = <0x0 0x85b00000 0x0 0x800000>;
0256 no-map;
0257 };
0258
0259 smem_mem: memory@86300000 {
0260 compatible = "qcom,smem";
0261 reg = <0x0 0x86300000 0x0 0x100000>;
0262 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0263 hwlocks = <&tcsr_mutex 3>;
0264 no-map;
0265 };
0266
0267 memory@86400000 {
0268 reg = <0x0 0x86400000 0x0 0x400000>;
0269 no-map;
0270 };
0271
0272 mpss_mem: memory@86c00000 {
0273 reg = <0x0 0x86c00000 0x0 0x6a00000>;
0274 no-map;
0275 };
0276
0277 adsp_fw_mem: memory@8d600000 {
0278 reg = <0x0 0x8d600000 0x0 0x1100000>;
0279 no-map;
0280 };
0281
0282 wcnss_fw_mem: memory@8e700000 {
0283 reg = <0x0 0x8e700000 0x0 0x700000>;
0284 no-map;
0285 };
0286
0287 memory@90000000 {
0288 reg = <0 0x90000000 0 0x1000>;
0289 no-map;
0290 };
0291
0292 memory@90001000 {
0293 reg = <0x0 0x90001000 0x0 0x13ff000>;
0294 no-map;
0295 };
0296
0297 venus_mem: memory@91400000 {
0298 reg = <0x0 0x91400000 0x0 0x700000>;
0299 no-map;
0300 };
0301
0302 mba_mem: memory@92000000 {
0303 reg = <0x0 0x92000000 0x0 0x100000>;
0304 no-map;
0305 };
0306
0307 memory@f2d00000 {
0308 compatible = "qcom,rmtfs-mem";
0309 reg = <0x0 0xf2d00000 0x0 0x180000>;
0310 no-map;
0311
0312 qcom,client-id = <1>;
0313 };
0314 };
0315
0316 smd {
0317 compatible = "qcom,smd";
0318
0319 rpm {
0320 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0321 qcom,ipc = <&apcs 8 0>;
0322 qcom,smd-edge = <15>;
0323
0324 rpm_requests: rpm-requests {
0325 compatible = "qcom,rpm-msm8953";
0326 qcom,smd-channels = "rpm_requests";
0327
0328 rpmcc: rpmcc {
0329 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
0330 clocks = <&xo_board>;
0331 clock-names = "xo";
0332 #clock-cells = <1>;
0333 };
0334
0335 rpmpd: power-controller {
0336 compatible = "qcom,msm8953-rpmpd";
0337 #power-domain-cells = <1>;
0338 operating-points-v2 = <&rpmpd_opp_table>;
0339
0340 clocks = <&xo_board>;
0341 clock-names = "ref";
0342
0343 rpmpd_opp_table: opp-table {
0344 compatible = "operating-points-v2";
0345
0346 rpmpd_opp_ret: opp1 {
0347 opp-level = <RPM_SMD_LEVEL_RETENTION>;
0348 };
0349
0350 rpmpd_opp_ret_plus: opp2 {
0351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
0352 };
0353
0354 rpmpd_opp_min_svs: opp3 {
0355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
0356 };
0357
0358 rpmpd_opp_low_svs: opp4 {
0359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
0360 };
0361
0362 rpmpd_opp_svs: opp5 {
0363 opp-level = <RPM_SMD_LEVEL_SVS>;
0364 };
0365
0366 rpmpd_opp_svs_plus: opp6 {
0367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
0368 };
0369
0370 rpmpd_opp_nom: opp7 {
0371 opp-level = <RPM_SMD_LEVEL_NOM>;
0372 };
0373
0374 rpmpd_opp_nom_plus: opp8 {
0375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
0376 };
0377
0378 rpmpd_opp_turbo: opp9 {
0379 opp-level = <RPM_SMD_LEVEL_TURBO>;
0380 };
0381 };
0382 };
0383 };
0384 };
0385 };
0386
0387 smsm {
0388 compatible = "qcom,smsm";
0389
0390 #address-cells = <1>;
0391 #size-cells = <0>;
0392
0393 qcom,ipc-1 = <&apcs 8 13>;
0394 qcom,ipc-3 = <&apcs 8 19>;
0395
0396 apps_smsm: apps@0 {
0397 reg = <0>;
0398
0399 #qcom,smem-state-cells = <1>;
0400 };
0401 };
0402
0403 soc: soc@0 {
0404 #address-cells = <1>;
0405 #size-cells = <1>;
0406 ranges = <0 0 0 0xffffffff>;
0407 compatible = "simple-bus";
0408
0409 rpm_msg_ram: sram@60000 {
0410 compatible = "qcom,rpm-msg-ram";
0411 reg = <0x60000 0x8000>;
0412 };
0413
0414 hsusb_phy: phy@79000 {
0415 compatible = "qcom,msm8953-qusb2-phy";
0416 reg = <0x79000 0x180>;
0417 #phy-cells = <0>;
0418
0419 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
0420 <&gcc GCC_QUSB_REF_CLK>;
0421 clock-names = "cfg_ahb", "ref";
0422
0423 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
0424
0425 resets = <&gcc GCC_QUSB2_PHY_BCR>;
0426
0427 status = "disabled";
0428 };
0429
0430 rng@e3000 {
0431 compatible = "qcom,prng";
0432 reg = <0x000e3000 0x1000>;
0433 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0434 clock-names = "core";
0435 };
0436
0437 tsens0: thermal-sensor@4a9000 {
0438 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
0439 reg = <0x4a9000 0x1000>, /* TM */
0440 <0x4a8000 0x1000>; /* SROT */
0441 #qcom,sensors = <16>;
0442 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0443 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
0444 interrupt-names = "uplow", "critical";
0445 #thermal-sensor-cells = <1>;
0446 };
0447
0448 restart@4ab000 {
0449 compatible = "qcom,pshold";
0450 reg = <0x4ab000 0x4>;
0451 };
0452
0453 tlmm: pinctrl@1000000 {
0454 compatible = "qcom,msm8953-pinctrl";
0455 reg = <0x1000000 0x300000>;
0456 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0457 gpio-controller;
0458 gpio-ranges = <&tlmm 0 0 155>;
0459 #gpio-cells = <2>;
0460 interrupt-controller;
0461 #interrupt-cells = <2>;
0462
0463 uart_console_active: uart-console-active-pins {
0464 pins = "gpio4", "gpio5";
0465 function = "blsp_uart2";
0466 drive-strength = <2>;
0467 bias-disable;
0468 };
0469
0470 uart_console_sleep: uart-console-sleep-pins {
0471 pins = "gpio4", "gpio5";
0472 function = "blsp_uart2";
0473 drive-strength = <2>;
0474 bias-pull-down;
0475 };
0476
0477 sdc1_clk_on: sdc1-clk-on-pins {
0478 pins = "sdc1_clk";
0479 bias-disable;
0480 drive-strength = <16>;
0481 };
0482
0483 sdc1_clk_off: sdc1-clk-off-pins {
0484 pins = "sdc1_clk";
0485 bias-disable;
0486 drive-strength = <2>;
0487 };
0488
0489 sdc1_cmd_on: sdc1-cmd-on-pins {
0490 pins = "sdc1_cmd";
0491 bias-disable;
0492 drive-strength = <10>;
0493 };
0494
0495 sdc1_cmd_off: sdc1-cmd-off-pins {
0496 pins = "sdc1_cmd";
0497 bias-disable;
0498 drive-strength = <2>;
0499 };
0500
0501 sdc1_data_on: sdc1-data-on-pins {
0502 pins = "sdc1_data";
0503 bias-pull-up;
0504 drive-strength = <10>;
0505 };
0506
0507 sdc1_data_off: sdc1-data-off-pins {
0508 pins = "sdc1_data";
0509 bias-pull-up;
0510 drive-strength = <2>;
0511 };
0512
0513 sdc1_rclk_on: sdc1-rclk-on-pins {
0514 pins = "sdc1_rclk";
0515 bias-pull-down;
0516 };
0517
0518 sdc1_rclk_off: sdc1-rclk-off-pins {
0519 pins = "sdc1_rclk";
0520 bias-pull-down;
0521 };
0522
0523 sdc2_clk_on: sdc2-clk-on-pins {
0524 pins = "sdc2_clk";
0525 drive-strength = <16>;
0526 bias-disable;
0527 };
0528
0529 sdc2_clk_off: sdc2-clk-off-pins {
0530 pins = "sdc2_clk";
0531 bias-disable;
0532 drive-strength = <2>;
0533 };
0534
0535 sdc2_cmd_on: sdc2-cmd-on-pins {
0536 pins = "sdc2_cmd";
0537 bias-pull-up;
0538 drive-strength = <10>;
0539 };
0540
0541 sdc2_cmd_off: sdc2-cmd-off-pins {
0542 pins = "sdc2_cmd";
0543 bias-pull-up;
0544 drive-strength = <2>;
0545 };
0546
0547 sdc2_data_on: sdc2-data-on-pins {
0548 pins = "sdc2_data";
0549 bias-pull-up;
0550 drive-strength = <10>;
0551 };
0552
0553 sdc2_data_off: sdc2-data-off-pins {
0554 pins = "sdc2_data";
0555 bias-pull-up;
0556 drive-strength = <2>;
0557 };
0558
0559 sdc2_cd_on: cd-on-pins {
0560 pins = "gpio133";
0561 function = "gpio";
0562 drive-strength = <2>;
0563 bias-pull-up;
0564 };
0565
0566 sdc2_cd_off: cd-off-pins {
0567 pins = "gpio133";
0568 function = "gpio";
0569 drive-strength = <2>;
0570 bias-disable;
0571 };
0572
0573 gpio_key_default: gpio-key-default-pins {
0574 pins = "gpio85";
0575 function = "gpio";
0576 drive-strength = <2>;
0577 bias-pull-up;
0578 };
0579
0580 i2c_1_default: i2c-1-default-pins {
0581 pins = "gpio2", "gpio3";
0582 function = "blsp_i2c1";
0583 drive-strength = <2>;
0584 bias-disable;
0585 };
0586
0587 i2c_1_sleep: i2c-1-sleep-pins {
0588 pins = "gpio2", "gpio3";
0589 function = "gpio";
0590 drive-strength = <2>;
0591 bias-disable;
0592 };
0593
0594 i2c_2_default: i2c-2-default-pins {
0595 pins = "gpio6", "gpio7";
0596 function = "blsp_i2c2";
0597 drive-strength = <2>;
0598 bias-disable;
0599 };
0600
0601 i2c_2_sleep: i2c-2-sleep-pins {
0602 pins = "gpio6", "gpio7";
0603 function = "gpio";
0604 drive-strength = <2>;
0605 bias-disable;
0606 };
0607
0608 i2c_3_default: i2c-3-default-pins {
0609 pins = "gpio10", "gpio11";
0610 function = "blsp_i2c3";
0611 drive-strength = <2>;
0612 bias-disable;
0613 };
0614
0615 i2c_3_sleep: i2c-3-sleep-pins {
0616 pins = "gpio10", "gpio11";
0617 function = "gpio";
0618 drive-strength = <2>;
0619 bias-disable;
0620 };
0621
0622 i2c_4_default: i2c-4-default-pins {
0623 pins = "gpio14", "gpio15";
0624 function = "blsp_i2c4";
0625 drive-strength = <2>;
0626 bias-disable;
0627 };
0628
0629 i2c_4_sleep: i2c-4-sleep-pins {
0630 pins = "gpio14", "gpio15";
0631 function = "gpio";
0632 drive-strength = <2>;
0633 bias-disable;
0634 };
0635
0636 i2c_5_default: i2c-5-default-pins {
0637 pins = "gpio18", "gpio19";
0638 function = "blsp_i2c5";
0639 drive-strength = <2>;
0640 bias-disable;
0641 };
0642
0643 i2c_5_sleep: i2c-5-sleep-pins {
0644 pins = "gpio18", "gpio19";
0645 function = "gpio";
0646 drive-strength = <2>;
0647 bias-disable;
0648 };
0649
0650 i2c_6_default: i2c-6-default-pins {
0651 pins = "gpio22", "gpio23";
0652 function = "blsp_i2c6";
0653 drive-strength = <2>;
0654 bias-disable;
0655 };
0656
0657 i2c_6_sleep: i2c-6-sleep-pins {
0658 pins = "gpio22", "gpio23";
0659 function = "gpio";
0660 drive-strength = <2>;
0661 bias-disable;
0662 };
0663
0664 i2c_7_default: i2c-7-default-pins {
0665 pins = "gpio135", "gpio136";
0666 function = "blsp_i2c7";
0667 drive-strength = <2>;
0668 bias-disable;
0669 };
0670
0671 i2c_7_sleep: i2c-7-sleep-pins {
0672 pins = "gpio135", "gpio136";
0673 function = "gpio";
0674 drive-strength = <2>;
0675 bias-disable;
0676 };
0677
0678 i2c_8_default: i2c-8-default-pins {
0679 pins = "gpio98", "gpio99";
0680 function = "blsp_i2c8";
0681 drive-strength = <2>;
0682 bias-disable;
0683 };
0684
0685 i2c_8_sleep: i2c-8-sleep-pins {
0686 pins = "gpio98", "gpio99";
0687 function = "gpio";
0688 drive-strength = <2>;
0689 bias-disable;
0690 };
0691 };
0692
0693 gcc: clock-controller@1800000 {
0694 compatible = "qcom,gcc-msm8953";
0695 reg = <0x1800000 0x80000>;
0696 #clock-cells = <1>;
0697 #reset-cells = <1>;
0698 #power-domain-cells = <1>;
0699 clocks = <&xo_board>,
0700 <&sleep_clk>,
0701 <0>,
0702 <0>,
0703 <0>,
0704 <0>;
0705 clock-names = "xo",
0706 "sleep",
0707 "dsi0pll",
0708 "dsi0pllbyte",
0709 "dsi1pll",
0710 "dsi1pllbyte";
0711 };
0712
0713 tcsr_mutex: hwlock@1905000 {
0714 compatible = "qcom,tcsr-mutex";
0715 reg = <0x1905000 0x20000>;
0716 #hwlock-cells = <1>;
0717 };
0718
0719 tcsr: syscon@1937000 {
0720 compatible = "qcom,tcsr-msm8953", "syscon";
0721 reg = <0x1937000 0x30000>;
0722 };
0723
0724 tcsr_phy_clk_scheme_sel: syscon@193f044 {
0725 compatible = "syscon";
0726 reg = <0x193f044 0x4>;
0727 };
0728
0729 spmi_bus: spmi@200f000 {
0730 compatible = "qcom,spmi-pmic-arb";
0731 reg = <0x200f000 0x1000>,
0732 <0x2400000 0x800000>,
0733 <0x2c00000 0x800000>,
0734 <0x3800000 0x200000>,
0735 <0x200a000 0x2100>;
0736 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
0737 interrupt-names = "periph_irq";
0738 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0739 qcom,ee = <0>;
0740 qcom,channel = <0>;
0741 interrupt-controller;
0742
0743 #interrupt-cells = <4>;
0744 #address-cells = <2>;
0745 #size-cells = <0>;
0746 };
0747
0748 usb3: usb@70f8800 {
0749 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
0750 reg = <0x70f8800 0x400>;
0751 #address-cells = <1>;
0752 #size-cells = <1>;
0753 ranges;
0754
0755 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0756 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
0757 interrupt-names = "hs_phy_irq", "ss_phy_irq";
0758
0759 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
0760 <&gcc GCC_USB30_MASTER_CLK>,
0761 <&gcc GCC_PCNOC_USB3_AXI_CLK>,
0762 <&gcc GCC_USB30_SLEEP_CLK>,
0763 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
0764 clock-names = "cfg_noc",
0765 "core",
0766 "iface",
0767 "sleep",
0768 "mock_utmi";
0769
0770 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
0771 <&gcc GCC_USB30_MASTER_CLK>;
0772 assigned-clock-rates = <19200000>, <133330000>;
0773
0774 power-domains = <&gcc USB30_GDSC>;
0775
0776 qcom,select-utmi-as-pipe-clk;
0777
0778 status = "disabled";
0779
0780 usb3_dwc3: usb@7000000 {
0781 compatible = "snps,dwc3";
0782 reg = <0x07000000 0xcc00>;
0783 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0784 phys = <&hsusb_phy>;
0785 phy-names = "usb2-phy";
0786
0787 snps,usb2-gadget-lpm-disable;
0788 snps,dis-u1-entry-quirk;
0789 snps,dis-u2-entry-quirk;
0790 snps,is-utmi-l1-suspend;
0791 snps,hird-threshold = /bits/ 8 <0x00>;
0792
0793 maximum-speed = "high-speed";
0794 phy_mode = "utmi";
0795 };
0796 };
0797
0798 sdhc_1: mmc@7824900 {
0799 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
0800
0801 reg = <0x7824900 0x500>, <0x7824000 0x800>;
0802 reg-names = "hc_mem", "core_mem";
0803
0804 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0805 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0806 interrupt-names = "hc_irq", "pwr_irq";
0807
0808 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0809 <&gcc GCC_SDCC1_APPS_CLK>,
0810 <&xo_board>;
0811 clock-names = "iface", "core", "xo";
0812
0813 power-domains = <&rpmpd MSM8953_VDDCX>;
0814 operating-points-v2 = <&sdhc1_opp_table>;
0815
0816 pinctrl-names = "default", "sleep";
0817 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
0818 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
0819
0820 mmc-hs400-1_8v;
0821 mmc-hs200-1_8v;
0822 mmc-ddr-1_8v;
0823 bus-width = <8>;
0824 non-removable;
0825
0826 status = "disabled";
0827
0828 sdhc1_opp_table: opp-table-sdhc1 {
0829 compatible = "operating-points-v2";
0830
0831 opp-25000000 {
0832 opp-hz = /bits/ 64 <25000000>;
0833 required-opps = <&rpmpd_opp_low_svs>;
0834 };
0835
0836 opp-50000000 {
0837 opp-hz = /bits/ 64 <50000000>;
0838 required-opps = <&rpmpd_opp_svs>;
0839 };
0840
0841 opp-100000000 {
0842 opp-hz = /bits/ 64 <100000000>;
0843 required-opps = <&rpmpd_opp_svs>;
0844 };
0845
0846 opp-192000000 {
0847 opp-hz = /bits/ 64 <192000000>;
0848 required-opps = <&rpmpd_opp_nom>;
0849 };
0850
0851 opp-384000000 {
0852 opp-hz = /bits/ 64 <384000000>;
0853 required-opps = <&rpmpd_opp_nom>;
0854 };
0855 };
0856 };
0857
0858 sdhc_2: mmc@7864900 {
0859 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
0860
0861 reg = <0x7864900 0x500>, <0x7864000 0x800>;
0862 reg-names = "hc_mem", "core_mem";
0863
0864 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0865 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0866 interrupt-names = "hc_irq", "pwr_irq";
0867
0868 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
0869 <&gcc GCC_SDCC2_APPS_CLK>,
0870 <&xo_board>;
0871 clock-names = "iface", "core", "xo";
0872
0873 power-domains = <&rpmpd MSM8953_VDDCX>;
0874 operating-points-v2 = <&sdhc2_opp_table>;
0875
0876 pinctrl-names = "default", "sleep";
0877 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
0878 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
0879
0880 bus-width = <4>;
0881
0882 status = "disabled";
0883
0884 sdhc2_opp_table: opp-table-sdhc2 {
0885 compatible = "operating-points-v2";
0886
0887 opp-25000000 {
0888 opp-hz = /bits/ 64 <25000000>;
0889 required-opps = <&rpmpd_opp_low_svs>;
0890 };
0891
0892 opp-50000000 {
0893 opp-hz = /bits/ 64 <50000000>;
0894 required-opps = <&rpmpd_opp_svs>;
0895 };
0896
0897 opp-100000000 {
0898 opp-hz = /bits/ 64 <100000000>;
0899 required-opps = <&rpmpd_opp_svs>;
0900 };
0901
0902 opp-177770000 {
0903 opp-hz = /bits/ 64 <177770000>;
0904 required-opps = <&rpmpd_opp_nom>;
0905 };
0906
0907 opp-200000000 {
0908 opp-hz = /bits/ 64 <200000000>;
0909 required-opps = <&rpmpd_opp_nom>;
0910 };
0911 };
0912 };
0913
0914 uart_0: serial@78af000 {
0915 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0916 reg = <0x78af000 0x200>;
0917 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0918 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
0919 <&gcc GCC_BLSP1_AHB_CLK>;
0920 clock-names = "core", "iface";
0921
0922 status = "disabled";
0923 };
0924
0925 i2c_1: i2c@78b5000 {
0926 compatible = "qcom,i2c-qup-v2.2.1";
0927 reg = <0x78b5000 0x600>;
0928 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0929 clock-names = "core", "iface";
0930 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
0931 <&gcc GCC_BLSP1_AHB_CLK>;
0932
0933 pinctrl-names = "default", "sleep";
0934 pinctrl-0 = <&i2c_1_default>;
0935 pinctrl-1 = <&i2c_1_sleep>;
0936
0937 #address-cells = <1>;
0938 #size-cells = <0>;
0939
0940 status = "disabled";
0941 };
0942
0943 i2c_2: i2c@78b6000 {
0944 compatible = "qcom,i2c-qup-v2.2.1";
0945 reg = <0x78b6000 0x600>;
0946 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0947 clock-names = "core", "iface";
0948 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
0949 <&gcc GCC_BLSP1_AHB_CLK>;
0950
0951 pinctrl-names = "default", "sleep";
0952 pinctrl-0 = <&i2c_2_default>;
0953 pinctrl-1 = <&i2c_2_sleep>;
0954
0955 #address-cells = <1>;
0956 #size-cells = <0>;
0957
0958 status = "disabled";
0959 };
0960
0961 i2c_3: i2c@78b7000 {
0962 compatible = "qcom,i2c-qup-v2.2.1";
0963 reg = <0x78b7000 0x600>;
0964 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0965 clock-names = "core", "iface";
0966 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
0967 <&gcc GCC_BLSP1_AHB_CLK>;
0968 pinctrl-names = "default", "sleep";
0969 pinctrl-0 = <&i2c_3_default>;
0970 pinctrl-1 = <&i2c_3_sleep>;
0971
0972 #address-cells = <1>;
0973 #size-cells = <0>;
0974
0975 status = "disabled";
0976 };
0977
0978 i2c_4: i2c@78b8000 {
0979 compatible = "qcom,i2c-qup-v2.2.1";
0980 reg = <0x78b8000 0x600>;
0981 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0982 clock-names = "core", "iface";
0983 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
0984 <&gcc GCC_BLSP1_AHB_CLK>;
0985 pinctrl-names = "default", "sleep";
0986 pinctrl-0 = <&i2c_4_default>;
0987 pinctrl-1 = <&i2c_4_sleep>;
0988
0989 #address-cells = <1>;
0990 #size-cells = <0>;
0991
0992 status = "disabled";
0993 };
0994
0995 i2c_5: i2c@7af5000 {
0996 compatible = "qcom,i2c-qup-v2.2.1";
0997 reg = <0x7af5000 0x600>;
0998 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
0999 clock-names = "core", "iface";
1000 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1001 <&gcc GCC_BLSP2_AHB_CLK>;
1002 pinctrl-names = "default", "sleep";
1003 pinctrl-0 = <&i2c_5_default>;
1004 pinctrl-1 = <&i2c_5_sleep>;
1005
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008
1009 status = "disabled";
1010 };
1011
1012 i2c_6: i2c@7af6000 {
1013 compatible = "qcom,i2c-qup-v2.2.1";
1014 reg = <0x7af6000 0x600>;
1015 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1016 clock-names = "core", "iface";
1017 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1018 <&gcc GCC_BLSP2_AHB_CLK>;
1019 pinctrl-names = "default", "sleep";
1020 pinctrl-0 = <&i2c_6_default>;
1021 pinctrl-1 = <&i2c_6_sleep>;
1022
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025
1026 status = "disabled";
1027 };
1028
1029 i2c_7: i2c@7af7000 {
1030 compatible = "qcom,i2c-qup-v2.2.1";
1031 reg = <0x7af7000 0x600>;
1032 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1033 clock-names = "core", "iface";
1034 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1035 <&gcc GCC_BLSP2_AHB_CLK>;
1036 pinctrl-names = "default", "sleep";
1037 pinctrl-0 = <&i2c_7_default>;
1038 pinctrl-1 = <&i2c_7_sleep>;
1039
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042
1043 status = "disabled";
1044 };
1045
1046 i2c_8: i2c@7af8000 {
1047 compatible = "qcom,i2c-qup-v2.2.1";
1048 reg = <0x7af8000 0x600>;
1049 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1050 clock-names = "core", "iface";
1051 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1052 <&gcc GCC_BLSP2_AHB_CLK>;
1053 pinctrl-names = "default", "sleep";
1054 pinctrl-0 = <&i2c_8_default>;
1055 pinctrl-1 = <&i2c_8_sleep>;
1056
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059
1060 status = "disabled";
1061 };
1062
1063 intc: interrupt-controller@b000000 {
1064 compatible = "qcom,msm-qgic2";
1065 interrupt-controller;
1066 #interrupt-cells = <3>;
1067 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1068 };
1069
1070 apcs: mailbox@b011000 {
1071 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1072 reg = <0xb011000 0x1000>;
1073 #mbox-cells = <1>;
1074 };
1075
1076 timer@b120000 {
1077 compatible = "arm,armv7-timer-mem";
1078 reg = <0xb120000 0x1000>;
1079 #address-cells = <0x01>;
1080 #size-cells = <0x01>;
1081 ranges;
1082
1083 frame@b121000 {
1084 frame-number = <0>;
1085 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1086 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1087 reg = <0xb121000 0x1000>,
1088 <0xb122000 0x1000>;
1089 };
1090
1091 frame@b123000 {
1092 frame-number = <1>;
1093 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1094 reg = <0xb123000 0x1000>;
1095 status = "disabled";
1096 };
1097
1098 frame@b124000 {
1099 frame-number = <2>;
1100 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1101 reg = <0xb124000 0x1000>;
1102 status = "disabled";
1103 };
1104
1105 frame@b125000 {
1106 frame-number = <3>;
1107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1108 reg = <0xb125000 0x1000>;
1109 status = "disabled";
1110 };
1111
1112 frame@b126000 {
1113 frame-number = <4>;
1114 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1115 reg = <0xb126000 0x1000>;
1116 status = "disabled";
1117 };
1118
1119 frame@b127000 {
1120 frame-number = <5>;
1121 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1122 reg = <0xb127000 0x1000>;
1123 status = "disabled";
1124 };
1125
1126 frame@b128000 {
1127 frame-number = <6>;
1128 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1129 reg = <0xb128000 0x1000>;
1130 status = "disabled";
1131 };
1132 };
1133 };
1134
1135 thermal-zones {
1136 cpu0-thermal {
1137 polling-delay-passive = <250>;
1138 polling-delay = <1000>;
1139 thermal-sensors = <&tsens0 9>;
1140 trips {
1141 cpu0_alert: trip-point0 {
1142 temperature = <80000>;
1143 hysteresis = <2000>;
1144 type = "passive";
1145 };
1146 cpu0_crit: crit {
1147 temperature = <100000>;
1148 hysteresis = <2000>;
1149 type = "critical";
1150 };
1151 };
1152 cooling-maps {
1153 map0 {
1154 trip = <&cpu0_alert>;
1155 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1156 };
1157 };
1158 };
1159 cpu1-thermal {
1160 polling-delay-passive = <250>;
1161 polling-delay = <1000>;
1162 thermal-sensors = <&tsens0 10>;
1163 trips {
1164 cpu1_alert: trip-point0 {
1165 temperature = <80000>;
1166 hysteresis = <2000>;
1167 type = "passive";
1168 };
1169 cpu1_crit: crit {
1170 temperature = <100000>;
1171 hysteresis = <2000>;
1172 type = "critical";
1173 };
1174 };
1175 cooling-maps {
1176 map0 {
1177 trip = <&cpu1_alert>;
1178 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1179 };
1180 };
1181 };
1182 cpu2-thermal {
1183 polling-delay-passive = <250>;
1184 polling-delay = <1000>;
1185 thermal-sensors = <&tsens0 11>;
1186 trips {
1187 cpu2_alert: trip-point0 {
1188 temperature = <80000>;
1189 hysteresis = <2000>;
1190 type = "passive";
1191 };
1192 cpu2_crit: crit {
1193 temperature = <100000>;
1194 hysteresis = <2000>;
1195 type = "critical";
1196 };
1197 };
1198 cooling-maps {
1199 map0 {
1200 trip = <&cpu2_alert>;
1201 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1202 };
1203 };
1204 };
1205 cpu3-thermal {
1206 polling-delay-passive = <250>;
1207 polling-delay = <1000>;
1208 thermal-sensors = <&tsens0 12>;
1209 trips {
1210 cpu3_alert: trip-point0 {
1211 temperature = <80000>;
1212 hysteresis = <2000>;
1213 type = "passive";
1214 };
1215 cpu3_crit: crit {
1216 temperature = <100000>;
1217 hysteresis = <2000>;
1218 type = "critical";
1219 };
1220 };
1221 cooling-maps {
1222 map0 {
1223 trip = <&cpu3_alert>;
1224 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1225 };
1226 };
1227 };
1228 cpu4-thermal {
1229 polling-delay-passive = <250>;
1230 polling-delay = <1000>;
1231 thermal-sensors = <&tsens0 4>;
1232 trips {
1233 cpu4_alert: trip-point0 {
1234 temperature = <80000>;
1235 hysteresis = <2000>;
1236 type = "passive";
1237 };
1238 cpu4_crit: crit {
1239 temperature = <100000>;
1240 hysteresis = <2000>;
1241 type = "critical";
1242 };
1243 };
1244 cooling-maps {
1245 map0 {
1246 trip = <&cpu4_alert>;
1247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1248 };
1249 };
1250 };
1251 cpu5-thermal {
1252 polling-delay-passive = <250>;
1253 polling-delay = <1000>;
1254 thermal-sensors = <&tsens0 5>;
1255 trips {
1256 cpu5_alert: trip-point0 {
1257 temperature = <80000>;
1258 hysteresis = <2000>;
1259 type = "passive";
1260 };
1261 cpu5_crit: crit {
1262 temperature = <100000>;
1263 hysteresis = <2000>;
1264 type = "critical";
1265 };
1266 };
1267 cooling-maps {
1268 map0 {
1269 trip = <&cpu5_alert>;
1270 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1271 };
1272 };
1273 };
1274 cpu6-thermal {
1275 polling-delay-passive = <250>;
1276 polling-delay = <1000>;
1277 thermal-sensors = <&tsens0 6>;
1278 trips {
1279 cpu6_alert: trip-point0 {
1280 temperature = <80000>;
1281 hysteresis = <2000>;
1282 type = "passive";
1283 };
1284 cpu6_crit: crit {
1285 temperature = <100000>;
1286 hysteresis = <2000>;
1287 type = "critical";
1288 };
1289 };
1290 cooling-maps {
1291 map0 {
1292 trip = <&cpu6_alert>;
1293 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1294 };
1295 };
1296 };
1297 cpu7-thermal {
1298 polling-delay-passive = <250>;
1299 polling-delay = <1000>;
1300 thermal-sensors = <&tsens0 7>;
1301 trips {
1302 cpu7_alert: trip-point0 {
1303 temperature = <80000>;
1304 hysteresis = <2000>;
1305 type = "passive";
1306 };
1307 cpu7_crit: crit {
1308 temperature = <100000>;
1309 hysteresis = <2000>;
1310 type = "critical";
1311 };
1312 };
1313 cooling-maps {
1314 map0 {
1315 trip = <&cpu7_alert>;
1316 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1317 };
1318 };
1319 };
1320 };
1321
1322 timer {
1323 compatible = "arm,armv8-timer";
1324 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1325 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1326 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1327 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1328 };
1329 };
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