0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/arm/coresight-cti-dt.h>
0007 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
0008 #include <dt-bindings/clock/qcom,rpmcc.h>
0009 #include <dt-bindings/interconnect/qcom,msm8916.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/power/qcom-rpmpd.h>
0012 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 interrupt-parent = <&intc>;
0017
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 mmc0 = &sdhc_1; /* SDC1 eMMC slot */
0023 mmc1 = &sdhc_2; /* SDC2 SD card slot */
0024 };
0025
0026 chosen { };
0027
0028 memory@80000000 {
0029 device_type = "memory";
0030 /* We expect the bootloader to fill in the reg */
0031 reg = <0 0x80000000 0 0>;
0032 };
0033
0034 reserved-memory {
0035 #address-cells = <2>;
0036 #size-cells = <2>;
0037 ranges;
0038
0039 tz-apps@86000000 {
0040 reg = <0x0 0x86000000 0x0 0x300000>;
0041 no-map;
0042 };
0043
0044 smem@86300000 {
0045 compatible = "qcom,smem";
0046 reg = <0x0 0x86300000 0x0 0x100000>;
0047 no-map;
0048
0049 hwlocks = <&tcsr_mutex 3>;
0050 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0051 };
0052
0053 hypervisor@86400000 {
0054 reg = <0x0 0x86400000 0x0 0x100000>;
0055 no-map;
0056 };
0057
0058 tz@86500000 {
0059 reg = <0x0 0x86500000 0x0 0x180000>;
0060 no-map;
0061 };
0062
0063 reserved@86680000 {
0064 reg = <0x0 0x86680000 0x0 0x80000>;
0065 no-map;
0066 };
0067
0068 rmtfs@86700000 {
0069 compatible = "qcom,rmtfs-mem";
0070 reg = <0x0 0x86700000 0x0 0xe0000>;
0071 no-map;
0072
0073 qcom,client-id = <1>;
0074 };
0075
0076 rfsa@867e0000 {
0077 reg = <0x0 0x867e0000 0x0 0x20000>;
0078 no-map;
0079 };
0080
0081 mpss_mem: mpss@86800000 {
0082 reg = <0x0 0x86800000 0x0 0x2b00000>;
0083 no-map;
0084 };
0085
0086 wcnss_mem: wcnss@89300000 {
0087 reg = <0x0 0x89300000 0x0 0x600000>;
0088 no-map;
0089 };
0090
0091 venus_mem: venus@89900000 {
0092 reg = <0x0 0x89900000 0x0 0x600000>;
0093 no-map;
0094 };
0095
0096 mba_mem: mba@8ea00000 {
0097 no-map;
0098 reg = <0 0x8ea00000 0 0x100000>;
0099 };
0100 };
0101
0102 clocks {
0103 xo_board: xo-board {
0104 compatible = "fixed-clock";
0105 #clock-cells = <0>;
0106 clock-frequency = <19200000>;
0107 };
0108
0109 sleep_clk: sleep-clk {
0110 compatible = "fixed-clock";
0111 #clock-cells = <0>;
0112 clock-frequency = <32768>;
0113 };
0114 };
0115
0116 cpus {
0117 #address-cells = <1>;
0118 #size-cells = <0>;
0119
0120 CPU0: cpu@0 {
0121 device_type = "cpu";
0122 compatible = "arm,cortex-a53";
0123 reg = <0x0>;
0124 next-level-cache = <&L2_0>;
0125 enable-method = "psci";
0126 clocks = <&apcs>;
0127 operating-points-v2 = <&cpu_opp_table>;
0128 #cooling-cells = <2>;
0129 power-domains = <&CPU_PD0>;
0130 power-domain-names = "psci";
0131 qcom,acc = <&cpu0_acc>;
0132 qcom,saw = <&cpu0_saw>;
0133 };
0134
0135 CPU1: cpu@1 {
0136 device_type = "cpu";
0137 compatible = "arm,cortex-a53";
0138 reg = <0x1>;
0139 next-level-cache = <&L2_0>;
0140 enable-method = "psci";
0141 clocks = <&apcs>;
0142 operating-points-v2 = <&cpu_opp_table>;
0143 #cooling-cells = <2>;
0144 power-domains = <&CPU_PD1>;
0145 power-domain-names = "psci";
0146 qcom,acc = <&cpu1_acc>;
0147 qcom,saw = <&cpu1_saw>;
0148 };
0149
0150 CPU2: cpu@2 {
0151 device_type = "cpu";
0152 compatible = "arm,cortex-a53";
0153 reg = <0x2>;
0154 next-level-cache = <&L2_0>;
0155 enable-method = "psci";
0156 clocks = <&apcs>;
0157 operating-points-v2 = <&cpu_opp_table>;
0158 #cooling-cells = <2>;
0159 power-domains = <&CPU_PD2>;
0160 power-domain-names = "psci";
0161 qcom,acc = <&cpu2_acc>;
0162 qcom,saw = <&cpu2_saw>;
0163 };
0164
0165 CPU3: cpu@3 {
0166 device_type = "cpu";
0167 compatible = "arm,cortex-a53";
0168 reg = <0x3>;
0169 next-level-cache = <&L2_0>;
0170 enable-method = "psci";
0171 clocks = <&apcs>;
0172 operating-points-v2 = <&cpu_opp_table>;
0173 #cooling-cells = <2>;
0174 power-domains = <&CPU_PD3>;
0175 power-domain-names = "psci";
0176 qcom,acc = <&cpu3_acc>;
0177 qcom,saw = <&cpu3_saw>;
0178 };
0179
0180 L2_0: l2-cache {
0181 compatible = "cache";
0182 cache-level = <2>;
0183 };
0184
0185 idle-states {
0186 entry-method = "psci";
0187
0188 CPU_SLEEP_0: cpu-sleep-0 {
0189 compatible = "arm,idle-state";
0190 idle-state-name = "standalone-power-collapse";
0191 arm,psci-suspend-param = <0x40000002>;
0192 entry-latency-us = <130>;
0193 exit-latency-us = <150>;
0194 min-residency-us = <2000>;
0195 local-timer-stop;
0196 };
0197 };
0198
0199 domain-idle-states {
0200
0201 CLUSTER_RET: cluster-retention {
0202 compatible = "domain-idle-state";
0203 arm,psci-suspend-param = <0x41000012>;
0204 entry-latency-us = <500>;
0205 exit-latency-us = <500>;
0206 min-residency-us = <2000>;
0207 };
0208
0209 CLUSTER_PWRDN: cluster-gdhs {
0210 compatible = "domain-idle-state";
0211 arm,psci-suspend-param = <0x41000032>;
0212 entry-latency-us = <2000>;
0213 exit-latency-us = <2000>;
0214 min-residency-us = <6000>;
0215 };
0216 };
0217 };
0218
0219 cpu_opp_table: opp-table-cpu {
0220 compatible = "operating-points-v2";
0221 opp-shared;
0222
0223 opp-200000000 {
0224 opp-hz = /bits/ 64 <200000000>;
0225 };
0226 opp-400000000 {
0227 opp-hz = /bits/ 64 <400000000>;
0228 };
0229 opp-800000000 {
0230 opp-hz = /bits/ 64 <800000000>;
0231 };
0232 opp-998400000 {
0233 opp-hz = /bits/ 64 <998400000>;
0234 };
0235 };
0236
0237 firmware {
0238 scm: scm {
0239 compatible = "qcom,scm-msm8916", "qcom,scm";
0240 clocks = <&gcc GCC_CRYPTO_CLK>,
0241 <&gcc GCC_CRYPTO_AXI_CLK>,
0242 <&gcc GCC_CRYPTO_AHB_CLK>;
0243 clock-names = "core", "bus", "iface";
0244 #reset-cells = <1>;
0245
0246 qcom,dload-mode = <&tcsr 0x6100>;
0247 };
0248 };
0249
0250 pmu {
0251 compatible = "arm,cortex-a53-pmu";
0252 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0253 };
0254
0255 psci {
0256 compatible = "arm,psci-1.0";
0257 method = "smc";
0258
0259 CPU_PD0: power-domain-cpu0 {
0260 #power-domain-cells = <0>;
0261 power-domains = <&CLUSTER_PD>;
0262 domain-idle-states = <&CPU_SLEEP_0>;
0263 };
0264
0265 CPU_PD1: power-domain-cpu1 {
0266 #power-domain-cells = <0>;
0267 power-domains = <&CLUSTER_PD>;
0268 domain-idle-states = <&CPU_SLEEP_0>;
0269 };
0270
0271 CPU_PD2: power-domain-cpu2 {
0272 #power-domain-cells = <0>;
0273 power-domains = <&CLUSTER_PD>;
0274 domain-idle-states = <&CPU_SLEEP_0>;
0275 };
0276
0277 CPU_PD3: power-domain-cpu3 {
0278 #power-domain-cells = <0>;
0279 power-domains = <&CLUSTER_PD>;
0280 domain-idle-states = <&CPU_SLEEP_0>;
0281 };
0282
0283 CLUSTER_PD: power-domain-cluster {
0284 #power-domain-cells = <0>;
0285 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
0286 };
0287 };
0288
0289 smd {
0290 compatible = "qcom,smd";
0291
0292 rpm {
0293 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0294 qcom,ipc = <&apcs 8 0>;
0295 qcom,smd-edge = <15>;
0296
0297 rpm_requests: rpm-requests {
0298 compatible = "qcom,rpm-msm8916";
0299 qcom,smd-channels = "rpm_requests";
0300
0301 rpmcc: clock-controller {
0302 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
0303 #clock-cells = <1>;
0304 clocks = <&xo_board>;
0305 clock-names = "xo";
0306 };
0307
0308 rpmpd: power-controller {
0309 compatible = "qcom,msm8916-rpmpd";
0310 #power-domain-cells = <1>;
0311 operating-points-v2 = <&rpmpd_opp_table>;
0312
0313 rpmpd_opp_table: opp-table {
0314 compatible = "operating-points-v2";
0315
0316 rpmpd_opp_ret: opp1 {
0317 opp-level = <1>;
0318 };
0319 rpmpd_opp_svs_krait: opp2 {
0320 opp-level = <2>;
0321 };
0322 rpmpd_opp_svs_soc: opp3 {
0323 opp-level = <3>;
0324 };
0325 rpmpd_opp_nom: opp4 {
0326 opp-level = <4>;
0327 };
0328 rpmpd_opp_turbo: opp5 {
0329 opp-level = <5>;
0330 };
0331 rpmpd_opp_super_turbo: opp6 {
0332 opp-level = <6>;
0333 };
0334 };
0335 };
0336 };
0337 };
0338 };
0339
0340 smp2p-hexagon {
0341 compatible = "qcom,smp2p";
0342 qcom,smem = <435>, <428>;
0343
0344 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
0345
0346 qcom,ipc = <&apcs 8 14>;
0347
0348 qcom,local-pid = <0>;
0349 qcom,remote-pid = <1>;
0350
0351 hexagon_smp2p_out: master-kernel {
0352 qcom,entry-name = "master-kernel";
0353
0354 #qcom,smem-state-cells = <1>;
0355 };
0356
0357 hexagon_smp2p_in: slave-kernel {
0358 qcom,entry-name = "slave-kernel";
0359
0360 interrupt-controller;
0361 #interrupt-cells = <2>;
0362 };
0363 };
0364
0365 smp2p-wcnss {
0366 compatible = "qcom,smp2p";
0367 qcom,smem = <451>, <431>;
0368
0369 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
0370
0371 qcom,ipc = <&apcs 8 18>;
0372
0373 qcom,local-pid = <0>;
0374 qcom,remote-pid = <4>;
0375
0376 wcnss_smp2p_out: master-kernel {
0377 qcom,entry-name = "master-kernel";
0378
0379 #qcom,smem-state-cells = <1>;
0380 };
0381
0382 wcnss_smp2p_in: slave-kernel {
0383 qcom,entry-name = "slave-kernel";
0384
0385 interrupt-controller;
0386 #interrupt-cells = <2>;
0387 };
0388 };
0389
0390 smsm {
0391 compatible = "qcom,smsm";
0392
0393 #address-cells = <1>;
0394 #size-cells = <0>;
0395
0396 qcom,ipc-1 = <&apcs 8 13>;
0397 qcom,ipc-3 = <&apcs 8 19>;
0398
0399 apps_smsm: apps@0 {
0400 reg = <0>;
0401
0402 #qcom,smem-state-cells = <1>;
0403 };
0404
0405 hexagon_smsm: hexagon@1 {
0406 reg = <1>;
0407 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
0408
0409 interrupt-controller;
0410 #interrupt-cells = <2>;
0411 };
0412
0413 wcnss_smsm: wcnss@6 {
0414 reg = <6>;
0415 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
0416
0417 interrupt-controller;
0418 #interrupt-cells = <2>;
0419 };
0420 };
0421
0422 soc: soc@0 {
0423 #address-cells = <1>;
0424 #size-cells = <1>;
0425 ranges = <0 0 0 0xffffffff>;
0426 compatible = "simple-bus";
0427
0428 rng@22000 {
0429 compatible = "qcom,prng";
0430 reg = <0x00022000 0x200>;
0431 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0432 clock-names = "core";
0433 };
0434
0435 restart@4ab000 {
0436 compatible = "qcom,pshold";
0437 reg = <0x004ab000 0x4>;
0438 };
0439
0440 qfprom: qfprom@5c000 {
0441 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
0442 reg = <0x0005c000 0x1000>;
0443 #address-cells = <1>;
0444 #size-cells = <1>;
0445 tsens_caldata: caldata@d0 {
0446 reg = <0xd0 0x8>;
0447 };
0448 tsens_calsel: calsel@ec {
0449 reg = <0xec 0x4>;
0450 };
0451 };
0452
0453 rpm_msg_ram: sram@60000 {
0454 compatible = "qcom,rpm-msg-ram";
0455 reg = <0x00060000 0x8000>;
0456 };
0457
0458 sram@290000 {
0459 compatible = "qcom,msm8916-rpm-stats";
0460 reg = <0x00290000 0x10000>;
0461 };
0462
0463 bimc: interconnect@400000 {
0464 compatible = "qcom,msm8916-bimc";
0465 reg = <0x00400000 0x62000>;
0466 #interconnect-cells = <1>;
0467 clock-names = "bus", "bus_a";
0468 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
0469 <&rpmcc RPM_SMD_BIMC_A_CLK>;
0470 };
0471
0472 tsens: thermal-sensor@4a9000 {
0473 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
0474 reg = <0x004a9000 0x1000>, /* TM */
0475 <0x004a8000 0x1000>; /* SROT */
0476 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
0477 nvmem-cell-names = "calib", "calib_sel";
0478 #qcom,sensors = <5>;
0479 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0480 interrupt-names = "uplow";
0481 #thermal-sensor-cells = <1>;
0482 };
0483
0484 pcnoc: interconnect@500000 {
0485 compatible = "qcom,msm8916-pcnoc";
0486 reg = <0x00500000 0x11000>;
0487 #interconnect-cells = <1>;
0488 clock-names = "bus", "bus_a";
0489 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
0490 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
0491 };
0492
0493 snoc: interconnect@580000 {
0494 compatible = "qcom,msm8916-snoc";
0495 reg = <0x00580000 0x14000>;
0496 #interconnect-cells = <1>;
0497 clock-names = "bus", "bus_a";
0498 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
0499 <&rpmcc RPM_SMD_SNOC_A_CLK>;
0500 };
0501
0502 stm: stm@802000 {
0503 compatible = "arm,coresight-stm", "arm,primecell";
0504 reg = <0x00802000 0x1000>,
0505 <0x09280000 0x180000>;
0506 reg-names = "stm-base", "stm-stimulus-base";
0507
0508 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0509 clock-names = "apb_pclk", "atclk";
0510
0511 status = "disabled";
0512
0513 out-ports {
0514 port {
0515 stm_out: endpoint {
0516 remote-endpoint = <&funnel0_in7>;
0517 };
0518 };
0519 };
0520 };
0521
0522 /* System CTIs */
0523 /* CTI 0 - TMC connections */
0524 cti0: cti@810000 {
0525 compatible = "arm,coresight-cti", "arm,primecell";
0526 reg = <0x00810000 0x1000>;
0527
0528 clocks = <&rpmcc RPM_QDSS_CLK>;
0529 clock-names = "apb_pclk";
0530
0531 status = "disabled";
0532 };
0533
0534 /* CTI 1 - TPIU connections */
0535 cti1: cti@811000 {
0536 compatible = "arm,coresight-cti", "arm,primecell";
0537 reg = <0x00811000 0x1000>;
0538
0539 clocks = <&rpmcc RPM_QDSS_CLK>;
0540 clock-names = "apb_pclk";
0541
0542 status = "disabled";
0543 };
0544
0545 /* CTIs 2-11 - no information - not instantiated */
0546
0547 tpiu: tpiu@820000 {
0548 compatible = "arm,coresight-tpiu", "arm,primecell";
0549 reg = <0x00820000 0x1000>;
0550
0551 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0552 clock-names = "apb_pclk", "atclk";
0553
0554 status = "disabled";
0555
0556 in-ports {
0557 port {
0558 tpiu_in: endpoint {
0559 remote-endpoint = <&replicator_out1>;
0560 };
0561 };
0562 };
0563 };
0564
0565 funnel0: funnel@821000 {
0566 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0567 reg = <0x00821000 0x1000>;
0568
0569 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0570 clock-names = "apb_pclk", "atclk";
0571
0572 status = "disabled";
0573
0574 in-ports {
0575 #address-cells = <1>;
0576 #size-cells = <0>;
0577
0578 /*
0579 * Not described input ports:
0580 * 0 - connected to Resource and Power Manger CPU ETM
0581 * 1 - not-connected
0582 * 2 - connected to Modem CPU ETM
0583 * 3 - not-connected
0584 * 5 - not-connected
0585 * 6 - connected trought funnel to Wireless CPU ETM
0586 * 7 - connected to STM component
0587 */
0588
0589 port@4 {
0590 reg = <4>;
0591 funnel0_in4: endpoint {
0592 remote-endpoint = <&funnel1_out>;
0593 };
0594 };
0595
0596 port@7 {
0597 reg = <7>;
0598 funnel0_in7: endpoint {
0599 remote-endpoint = <&stm_out>;
0600 };
0601 };
0602 };
0603
0604 out-ports {
0605 port {
0606 funnel0_out: endpoint {
0607 remote-endpoint = <&etf_in>;
0608 };
0609 };
0610 };
0611 };
0612
0613 replicator: replicator@824000 {
0614 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
0615 reg = <0x00824000 0x1000>;
0616
0617 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0618 clock-names = "apb_pclk", "atclk";
0619
0620 status = "disabled";
0621
0622 out-ports {
0623 #address-cells = <1>;
0624 #size-cells = <0>;
0625
0626 port@0 {
0627 reg = <0>;
0628 replicator_out0: endpoint {
0629 remote-endpoint = <&etr_in>;
0630 };
0631 };
0632 port@1 {
0633 reg = <1>;
0634 replicator_out1: endpoint {
0635 remote-endpoint = <&tpiu_in>;
0636 };
0637 };
0638 };
0639
0640 in-ports {
0641 port {
0642 replicator_in: endpoint {
0643 remote-endpoint = <&etf_out>;
0644 };
0645 };
0646 };
0647 };
0648
0649 etf: etf@825000 {
0650 compatible = "arm,coresight-tmc", "arm,primecell";
0651 reg = <0x00825000 0x1000>;
0652
0653 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0654 clock-names = "apb_pclk", "atclk";
0655
0656 status = "disabled";
0657
0658 in-ports {
0659 port {
0660 etf_in: endpoint {
0661 remote-endpoint = <&funnel0_out>;
0662 };
0663 };
0664 };
0665
0666 out-ports {
0667 port {
0668 etf_out: endpoint {
0669 remote-endpoint = <&replicator_in>;
0670 };
0671 };
0672 };
0673 };
0674
0675 etr: etr@826000 {
0676 compatible = "arm,coresight-tmc", "arm,primecell";
0677 reg = <0x00826000 0x1000>;
0678
0679 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0680 clock-names = "apb_pclk", "atclk";
0681
0682 status = "disabled";
0683
0684 in-ports {
0685 port {
0686 etr_in: endpoint {
0687 remote-endpoint = <&replicator_out0>;
0688 };
0689 };
0690 };
0691 };
0692
0693 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
0694 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0695 reg = <0x00841000 0x1000>;
0696
0697 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0698 clock-names = "apb_pclk", "atclk";
0699
0700 status = "disabled";
0701
0702 in-ports {
0703 #address-cells = <1>;
0704 #size-cells = <0>;
0705
0706 port@0 {
0707 reg = <0>;
0708 funnel1_in0: endpoint {
0709 remote-endpoint = <&etm0_out>;
0710 };
0711 };
0712 port@1 {
0713 reg = <1>;
0714 funnel1_in1: endpoint {
0715 remote-endpoint = <&etm1_out>;
0716 };
0717 };
0718 port@2 {
0719 reg = <2>;
0720 funnel1_in2: endpoint {
0721 remote-endpoint = <&etm2_out>;
0722 };
0723 };
0724 port@3 {
0725 reg = <3>;
0726 funnel1_in3: endpoint {
0727 remote-endpoint = <&etm3_out>;
0728 };
0729 };
0730 };
0731
0732 out-ports {
0733 port {
0734 funnel1_out: endpoint {
0735 remote-endpoint = <&funnel0_in4>;
0736 };
0737 };
0738 };
0739 };
0740
0741 debug0: debug@850000 {
0742 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0743 reg = <0x00850000 0x1000>;
0744 clocks = <&rpmcc RPM_QDSS_CLK>;
0745 clock-names = "apb_pclk";
0746 cpu = <&CPU0>;
0747 status = "disabled";
0748 };
0749
0750 debug1: debug@852000 {
0751 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0752 reg = <0x00852000 0x1000>;
0753 clocks = <&rpmcc RPM_QDSS_CLK>;
0754 clock-names = "apb_pclk";
0755 cpu = <&CPU1>;
0756 status = "disabled";
0757 };
0758
0759 debug2: debug@854000 {
0760 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0761 reg = <0x00854000 0x1000>;
0762 clocks = <&rpmcc RPM_QDSS_CLK>;
0763 clock-names = "apb_pclk";
0764 cpu = <&CPU2>;
0765 status = "disabled";
0766 };
0767
0768 debug3: debug@856000 {
0769 compatible = "arm,coresight-cpu-debug", "arm,primecell";
0770 reg = <0x00856000 0x1000>;
0771 clocks = <&rpmcc RPM_QDSS_CLK>;
0772 clock-names = "apb_pclk";
0773 cpu = <&CPU3>;
0774 status = "disabled";
0775 };
0776
0777 /* Core CTIs; CTIs 12-15 */
0778 /* CTI - CPU-0 */
0779 cti12: cti@858000 {
0780 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0781 "arm,primecell";
0782 reg = <0x00858000 0x1000>;
0783
0784 clocks = <&rpmcc RPM_QDSS_CLK>;
0785 clock-names = "apb_pclk";
0786
0787 cpu = <&CPU0>;
0788 arm,cs-dev-assoc = <&etm0>;
0789
0790 status = "disabled";
0791 };
0792
0793 /* CTI - CPU-1 */
0794 cti13: cti@859000 {
0795 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0796 "arm,primecell";
0797 reg = <0x00859000 0x1000>;
0798
0799 clocks = <&rpmcc RPM_QDSS_CLK>;
0800 clock-names = "apb_pclk";
0801
0802 cpu = <&CPU1>;
0803 arm,cs-dev-assoc = <&etm1>;
0804
0805 status = "disabled";
0806 };
0807
0808 /* CTI - CPU-2 */
0809 cti14: cti@85a000 {
0810 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0811 "arm,primecell";
0812 reg = <0x0085a000 0x1000>;
0813
0814 clocks = <&rpmcc RPM_QDSS_CLK>;
0815 clock-names = "apb_pclk";
0816
0817 cpu = <&CPU2>;
0818 arm,cs-dev-assoc = <&etm2>;
0819
0820 status = "disabled";
0821 };
0822
0823 /* CTI - CPU-3 */
0824 cti15: cti@85b000 {
0825 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
0826 "arm,primecell";
0827 reg = <0x0085b000 0x1000>;
0828
0829 clocks = <&rpmcc RPM_QDSS_CLK>;
0830 clock-names = "apb_pclk";
0831
0832 cpu = <&CPU3>;
0833 arm,cs-dev-assoc = <&etm3>;
0834
0835 status = "disabled";
0836 };
0837
0838 etm0: etm@85c000 {
0839 compatible = "arm,coresight-etm4x", "arm,primecell";
0840 reg = <0x0085c000 0x1000>;
0841
0842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0843 clock-names = "apb_pclk", "atclk";
0844 arm,coresight-loses-context-with-cpu;
0845
0846 cpu = <&CPU0>;
0847
0848 status = "disabled";
0849
0850 out-ports {
0851 port {
0852 etm0_out: endpoint {
0853 remote-endpoint = <&funnel1_in0>;
0854 };
0855 };
0856 };
0857 };
0858
0859 etm1: etm@85d000 {
0860 compatible = "arm,coresight-etm4x", "arm,primecell";
0861 reg = <0x0085d000 0x1000>;
0862
0863 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0864 clock-names = "apb_pclk", "atclk";
0865 arm,coresight-loses-context-with-cpu;
0866
0867 cpu = <&CPU1>;
0868
0869 status = "disabled";
0870
0871 out-ports {
0872 port {
0873 etm1_out: endpoint {
0874 remote-endpoint = <&funnel1_in1>;
0875 };
0876 };
0877 };
0878 };
0879
0880 etm2: etm@85e000 {
0881 compatible = "arm,coresight-etm4x", "arm,primecell";
0882 reg = <0x0085e000 0x1000>;
0883
0884 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0885 clock-names = "apb_pclk", "atclk";
0886 arm,coresight-loses-context-with-cpu;
0887
0888 cpu = <&CPU2>;
0889
0890 status = "disabled";
0891
0892 out-ports {
0893 port {
0894 etm2_out: endpoint {
0895 remote-endpoint = <&funnel1_in2>;
0896 };
0897 };
0898 };
0899 };
0900
0901 etm3: etm@85f000 {
0902 compatible = "arm,coresight-etm4x", "arm,primecell";
0903 reg = <0x0085f000 0x1000>;
0904
0905 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
0906 clock-names = "apb_pclk", "atclk";
0907 arm,coresight-loses-context-with-cpu;
0908
0909 cpu = <&CPU3>;
0910
0911 status = "disabled";
0912
0913 out-ports {
0914 port {
0915 etm3_out: endpoint {
0916 remote-endpoint = <&funnel1_in3>;
0917 };
0918 };
0919 };
0920 };
0921
0922 msmgpio: pinctrl@1000000 {
0923 compatible = "qcom,msm8916-pinctrl";
0924 reg = <0x01000000 0x300000>;
0925 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0926 gpio-controller;
0927 gpio-ranges = <&msmgpio 0 0 122>;
0928 #gpio-cells = <2>;
0929 interrupt-controller;
0930 #interrupt-cells = <2>;
0931 };
0932
0933 gcc: clock-controller@1800000 {
0934 compatible = "qcom,gcc-msm8916";
0935 #clock-cells = <1>;
0936 #reset-cells = <1>;
0937 #power-domain-cells = <1>;
0938 reg = <0x01800000 0x80000>;
0939 };
0940
0941 tcsr_mutex: hwlock@1905000 {
0942 compatible = "qcom,tcsr-mutex";
0943 reg = <0x01905000 0x20000>;
0944 #hwlock-cells = <1>;
0945 };
0946
0947 tcsr: syscon@1937000 {
0948 compatible = "qcom,tcsr-msm8916", "syscon";
0949 reg = <0x01937000 0x30000>;
0950 };
0951
0952 mdss: mdss@1a00000 {
0953 status = "disabled";
0954 compatible = "qcom,mdss";
0955 reg = <0x01a00000 0x1000>,
0956 <0x01ac8000 0x3000>;
0957 reg-names = "mdss_phys", "vbif_phys";
0958
0959 power-domains = <&gcc MDSS_GDSC>;
0960
0961 clocks = <&gcc GCC_MDSS_AHB_CLK>,
0962 <&gcc GCC_MDSS_AXI_CLK>,
0963 <&gcc GCC_MDSS_VSYNC_CLK>;
0964 clock-names = "iface",
0965 "bus",
0966 "vsync";
0967
0968 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0969
0970 interrupt-controller;
0971 #interrupt-cells = <1>;
0972
0973 #address-cells = <1>;
0974 #size-cells = <1>;
0975 ranges;
0976
0977 mdp: mdp@1a01000 {
0978 compatible = "qcom,mdp5";
0979 reg = <0x01a01000 0x89000>;
0980 reg-names = "mdp_phys";
0981
0982 interrupt-parent = <&mdss>;
0983 interrupts = <0>;
0984
0985 clocks = <&gcc GCC_MDSS_AHB_CLK>,
0986 <&gcc GCC_MDSS_AXI_CLK>,
0987 <&gcc GCC_MDSS_MDP_CLK>,
0988 <&gcc GCC_MDSS_VSYNC_CLK>;
0989 clock-names = "iface",
0990 "bus",
0991 "core",
0992 "vsync";
0993
0994 iommus = <&apps_iommu 4>;
0995
0996 ports {
0997 #address-cells = <1>;
0998 #size-cells = <0>;
0999
1000 port@0 {
1001 reg = <0>;
1002 mdp5_intf1_out: endpoint {
1003 remote-endpoint = <&dsi0_in>;
1004 };
1005 };
1006 };
1007 };
1008
1009 dsi0: dsi@1a98000 {
1010 compatible = "qcom,mdss-dsi-ctrl";
1011 reg = <0x01a98000 0x25c>;
1012 reg-names = "dsi_ctrl";
1013
1014 interrupt-parent = <&mdss>;
1015 interrupts = <4>;
1016
1017 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1018 <&gcc PCLK0_CLK_SRC>;
1019 assigned-clock-parents = <&dsi_phy0 0>,
1020 <&dsi_phy0 1>;
1021
1022 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1023 <&gcc GCC_MDSS_AHB_CLK>,
1024 <&gcc GCC_MDSS_AXI_CLK>,
1025 <&gcc GCC_MDSS_BYTE0_CLK>,
1026 <&gcc GCC_MDSS_PCLK0_CLK>,
1027 <&gcc GCC_MDSS_ESC0_CLK>;
1028 clock-names = "mdp_core",
1029 "iface",
1030 "bus",
1031 "byte",
1032 "pixel",
1033 "core";
1034 phys = <&dsi_phy0>;
1035 phy-names = "dsi-phy";
1036
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039
1040 ports {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043
1044 port@0 {
1045 reg = <0>;
1046 dsi0_in: endpoint {
1047 remote-endpoint = <&mdp5_intf1_out>;
1048 };
1049 };
1050
1051 port@1 {
1052 reg = <1>;
1053 dsi0_out: endpoint {
1054 };
1055 };
1056 };
1057 };
1058
1059 dsi_phy0: dsi-phy@1a98300 {
1060 compatible = "qcom,dsi-phy-28nm-lp";
1061 reg = <0x01a98300 0xd4>,
1062 <0x01a98500 0x280>,
1063 <0x01a98780 0x30>;
1064 reg-names = "dsi_pll",
1065 "dsi_phy",
1066 "dsi_phy_regulator";
1067
1068 #clock-cells = <1>;
1069 #phy-cells = <0>;
1070
1071 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1072 <&xo_board>;
1073 clock-names = "iface", "ref";
1074 };
1075 };
1076
1077 camss: camss@1b00000 {
1078 compatible = "qcom,msm8916-camss";
1079 reg = <0x01b0ac00 0x200>,
1080 <0x01b00030 0x4>,
1081 <0x01b0b000 0x200>,
1082 <0x01b00038 0x4>,
1083 <0x01b08000 0x100>,
1084 <0x01b08400 0x100>,
1085 <0x01b0a000 0x500>,
1086 <0x01b00020 0x10>,
1087 <0x01b10000 0x1000>;
1088 reg-names = "csiphy0",
1089 "csiphy0_clk_mux",
1090 "csiphy1",
1091 "csiphy1_clk_mux",
1092 "csid0",
1093 "csid1",
1094 "ispif",
1095 "csi_clk_mux",
1096 "vfe0";
1097 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1098 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1099 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1100 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1101 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1102 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1103 interrupt-names = "csiphy0",
1104 "csiphy1",
1105 "csid0",
1106 "csid1",
1107 "ispif",
1108 "vfe0";
1109 power-domains = <&gcc VFE_GDSC>;
1110 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1111 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1112 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1113 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1114 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1115 <&gcc GCC_CAMSS_CSI0_CLK>,
1116 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1117 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1118 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1119 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1120 <&gcc GCC_CAMSS_CSI1_CLK>,
1121 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1122 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1123 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1124 <&gcc GCC_CAMSS_AHB_CLK>,
1125 <&gcc GCC_CAMSS_VFE0_CLK>,
1126 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1127 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1128 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1129 clock-names = "top_ahb",
1130 "ispif_ahb",
1131 "csiphy0_timer",
1132 "csiphy1_timer",
1133 "csi0_ahb",
1134 "csi0",
1135 "csi0_phy",
1136 "csi0_pix",
1137 "csi0_rdi",
1138 "csi1_ahb",
1139 "csi1",
1140 "csi1_phy",
1141 "csi1_pix",
1142 "csi1_rdi",
1143 "ahb",
1144 "vfe0",
1145 "csi_vfe0",
1146 "vfe_ahb",
1147 "vfe_axi";
1148 iommus = <&apps_iommu 3>;
1149 status = "disabled";
1150 ports {
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 };
1154 };
1155
1156 cci: cci@1b0c000 {
1157 compatible = "qcom,msm8916-cci";
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 reg = <0x01b0c000 0x1000>;
1161 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1162 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1163 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1164 <&gcc GCC_CAMSS_CCI_CLK>,
1165 <&gcc GCC_CAMSS_AHB_CLK>;
1166 clock-names = "camss_top_ahb", "cci_ahb",
1167 "cci", "camss_ahb";
1168 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1169 <&gcc GCC_CAMSS_CCI_CLK>;
1170 assigned-clock-rates = <80000000>, <19200000>;
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&cci0_default>;
1173 status = "disabled";
1174
1175 cci_i2c0: i2c-bus@0 {
1176 reg = <0>;
1177 clock-frequency = <400000>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 };
1181 };
1182
1183 gpu@1c00000 {
1184 compatible = "qcom,adreno-306.0", "qcom,adreno";
1185 reg = <0x01c00000 0x20000>;
1186 reg-names = "kgsl_3d0_reg_memory";
1187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1188 interrupt-names = "kgsl_3d0_irq";
1189 clock-names =
1190 "core",
1191 "iface",
1192 "mem",
1193 "mem_iface",
1194 "alt_mem_iface",
1195 "gfx3d";
1196 clocks =
1197 <&gcc GCC_OXILI_GFX3D_CLK>,
1198 <&gcc GCC_OXILI_AHB_CLK>,
1199 <&gcc GCC_OXILI_GMEM_CLK>,
1200 <&gcc GCC_BIMC_GFX_CLK>,
1201 <&gcc GCC_BIMC_GPU_CLK>,
1202 <&gcc GFX3D_CLK_SRC>;
1203 power-domains = <&gcc OXILI_GDSC>;
1204 operating-points-v2 = <&gpu_opp_table>;
1205 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1206
1207 gpu_opp_table: opp-table {
1208 compatible = "operating-points-v2";
1209
1210 opp-400000000 {
1211 opp-hz = /bits/ 64 <400000000>;
1212 };
1213 opp-19200000 {
1214 opp-hz = /bits/ 64 <19200000>;
1215 };
1216 };
1217 };
1218
1219 venus: video-codec@1d00000 {
1220 compatible = "qcom,msm8916-venus";
1221 reg = <0x01d00000 0xff000>;
1222 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1223 power-domains = <&gcc VENUS_GDSC>;
1224 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1225 <&gcc GCC_VENUS0_AHB_CLK>,
1226 <&gcc GCC_VENUS0_AXI_CLK>;
1227 clock-names = "core", "iface", "bus";
1228 iommus = <&apps_iommu 5>;
1229 memory-region = <&venus_mem>;
1230 status = "okay";
1231
1232 video-decoder {
1233 compatible = "venus-decoder";
1234 };
1235
1236 video-encoder {
1237 compatible = "venus-encoder";
1238 };
1239 };
1240
1241 apps_iommu: iommu@1ef0000 {
1242 #address-cells = <1>;
1243 #size-cells = <1>;
1244 #iommu-cells = <1>;
1245 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1246 ranges = <0 0x01e20000 0x40000>;
1247 reg = <0x01ef0000 0x3000>;
1248 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1249 <&gcc GCC_APSS_TCU_CLK>;
1250 clock-names = "iface", "bus";
1251 qcom,iommu-secure-id = <17>;
1252
1253 // vfe:
1254 iommu-ctx@3000 {
1255 compatible = "qcom,msm-iommu-v1-sec";
1256 reg = <0x3000 0x1000>;
1257 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1258 };
1259
1260 // mdp_0:
1261 iommu-ctx@4000 {
1262 compatible = "qcom,msm-iommu-v1-ns";
1263 reg = <0x4000 0x1000>;
1264 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1265 };
1266
1267 // venus_ns:
1268 iommu-ctx@5000 {
1269 compatible = "qcom,msm-iommu-v1-sec";
1270 reg = <0x5000 0x1000>;
1271 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1272 };
1273 };
1274
1275 gpu_iommu: iommu@1f08000 {
1276 #address-cells = <1>;
1277 #size-cells = <1>;
1278 #iommu-cells = <1>;
1279 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1280 ranges = <0 0x01f08000 0x10000>;
1281 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1282 <&gcc GCC_GFX_TCU_CLK>;
1283 clock-names = "iface", "bus";
1284 qcom,iommu-secure-id = <18>;
1285
1286 // gfx3d_user:
1287 iommu-ctx@1000 {
1288 compatible = "qcom,msm-iommu-v1-ns";
1289 reg = <0x1000 0x1000>;
1290 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1291 };
1292
1293 // gfx3d_priv:
1294 iommu-ctx@2000 {
1295 compatible = "qcom,msm-iommu-v1-ns";
1296 reg = <0x2000 0x1000>;
1297 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1298 };
1299 };
1300
1301 spmi_bus: spmi@200f000 {
1302 compatible = "qcom,spmi-pmic-arb";
1303 reg = <0x0200f000 0x001000>,
1304 <0x02400000 0x400000>,
1305 <0x02c00000 0x400000>,
1306 <0x03800000 0x200000>,
1307 <0x0200a000 0x002100>;
1308 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1309 interrupt-names = "periph_irq";
1310 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1311 qcom,ee = <0>;
1312 qcom,channel = <0>;
1313 #address-cells = <2>;
1314 #size-cells = <0>;
1315 interrupt-controller;
1316 #interrupt-cells = <4>;
1317 };
1318
1319 bam_dmux_dma: dma-controller@4044000 {
1320 compatible = "qcom,bam-v1.7.0";
1321 reg = <0x04044000 0x19000>;
1322 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1323 #dma-cells = <1>;
1324 qcom,ee = <0>;
1325
1326 num-channels = <6>;
1327 qcom,num-ees = <1>;
1328 qcom,powered-remotely;
1329
1330 status = "disabled";
1331 };
1332
1333 mpss: remoteproc@4080000 {
1334 compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1335 reg = <0x04080000 0x100>,
1336 <0x04020000 0x040>;
1337
1338 reg-names = "qdsp6", "rmb";
1339
1340 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1341 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1342 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1343 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1344 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1345 interrupt-names = "wdog", "fatal", "ready",
1346 "handover", "stop-ack";
1347
1348 power-domains = <&rpmpd MSM8916_VDDCX>,
1349 <&rpmpd MSM8916_VDDMX>;
1350 power-domain-names = "cx", "mx";
1351
1352 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1353 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1354 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1355 <&xo_board>;
1356 clock-names = "iface", "bus", "mem", "xo";
1357
1358 qcom,smem-states = <&hexagon_smp2p_out 0>;
1359 qcom,smem-state-names = "stop";
1360
1361 resets = <&scm 0>;
1362 reset-names = "mss_restart";
1363
1364 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1365
1366 status = "disabled";
1367
1368 mba {
1369 memory-region = <&mba_mem>;
1370 };
1371
1372 mpss {
1373 memory-region = <&mpss_mem>;
1374 };
1375
1376 bam_dmux: bam-dmux {
1377 compatible = "qcom,bam-dmux";
1378
1379 interrupt-parent = <&hexagon_smsm>;
1380 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1381 interrupt-names = "pc", "pc-ack";
1382
1383 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1384 qcom,smem-state-names = "pc", "pc-ack";
1385
1386 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1387 dma-names = "tx", "rx";
1388
1389 status = "disabled";
1390 };
1391
1392 smd-edge {
1393 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1394
1395 qcom,smd-edge = <0>;
1396 qcom,ipc = <&apcs 8 12>;
1397 qcom,remote-pid = <1>;
1398
1399 label = "hexagon";
1400
1401 fastrpc {
1402 compatible = "qcom,fastrpc";
1403 qcom,smd-channels = "fastrpcsmd-apps-dsp";
1404 label = "adsp";
1405 qcom,non-secure-domain;
1406
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1409
1410 cb@1 {
1411 compatible = "qcom,fastrpc-compute-cb";
1412 reg = <1>;
1413 };
1414 };
1415 };
1416 };
1417
1418 sound: sound@7702000 {
1419 status = "disabled";
1420 compatible = "qcom,apq8016-sbc-sndcard";
1421 reg = <0x07702000 0x4>, <0x07702004 0x4>;
1422 reg-names = "mic-iomux", "spkr-iomux";
1423 };
1424
1425 lpass: audio-controller@7708000 {
1426 status = "disabled";
1427 compatible = "qcom,lpass-cpu-apq8016";
1428
1429 /*
1430 * Note: Unlike the name would suggest, the SEC_I2S_CLK
1431 * is actually only used by Tertiary MI2S while
1432 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
1433 */
1434 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1435 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1436 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1437 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1438 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1439 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1440 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1441
1442 clock-names = "ahbix-clk",
1443 "pcnoc-mport-clk",
1444 "pcnoc-sway-clk",
1445 "mi2s-bit-clk0",
1446 "mi2s-bit-clk1",
1447 "mi2s-bit-clk2",
1448 "mi2s-bit-clk3";
1449 #sound-dai-cells = <1>;
1450
1451 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1452 interrupt-names = "lpass-irq-lpaif";
1453 reg = <0x07708000 0x10000>;
1454 reg-names = "lpass-lpaif";
1455
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 };
1459
1460 lpass_codec: audio-codec@771c000 {
1461 compatible = "qcom,msm8916-wcd-digital-codec";
1462 reg = <0x0771c000 0x400>;
1463 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1464 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1465 clock-names = "ahbix-clk", "mclk";
1466 #sound-dai-cells = <1>;
1467 };
1468
1469 sdhc_1: mmc@7824000 {
1470 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1471 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1472 reg-names = "hc_mem", "core_mem";
1473
1474 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1476 interrupt-names = "hc_irq", "pwr_irq";
1477 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1478 <&gcc GCC_SDCC1_APPS_CLK>,
1479 <&xo_board>;
1480 clock-names = "iface", "core", "xo";
1481 mmc-ddr-1_8v;
1482 bus-width = <8>;
1483 non-removable;
1484 status = "disabled";
1485 };
1486
1487 sdhc_2: mmc@7864000 {
1488 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1489 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1490 reg-names = "hc_mem", "core_mem";
1491
1492 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1494 interrupt-names = "hc_irq", "pwr_irq";
1495 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1496 <&gcc GCC_SDCC2_APPS_CLK>,
1497 <&xo_board>;
1498 clock-names = "iface", "core", "xo";
1499 bus-width = <4>;
1500 status = "disabled";
1501 };
1502
1503 blsp_dma: dma-controller@7884000 {
1504 compatible = "qcom,bam-v1.7.0";
1505 reg = <0x07884000 0x23000>;
1506 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1508 clock-names = "bam_clk";
1509 #dma-cells = <1>;
1510 qcom,ee = <0>;
1511 status = "disabled";
1512 };
1513
1514 blsp1_uart1: serial@78af000 {
1515 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1516 reg = <0x078af000 0x200>;
1517 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1518 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1519 clock-names = "core", "iface";
1520 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1521 dma-names = "tx", "rx";
1522 pinctrl-names = "default", "sleep";
1523 pinctrl-0 = <&blsp1_uart1_default>;
1524 pinctrl-1 = <&blsp1_uart1_sleep>;
1525 status = "disabled";
1526 };
1527
1528 blsp1_uart2: serial@78b0000 {
1529 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1530 reg = <0x078b0000 0x200>;
1531 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1532 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1533 clock-names = "core", "iface";
1534 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1535 dma-names = "tx", "rx";
1536 pinctrl-names = "default", "sleep";
1537 pinctrl-0 = <&blsp1_uart2_default>;
1538 pinctrl-1 = <&blsp1_uart2_sleep>;
1539 status = "disabled";
1540 };
1541
1542 blsp_i2c1: i2c@78b5000 {
1543 compatible = "qcom,i2c-qup-v2.2.1";
1544 reg = <0x078b5000 0x500>;
1545 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1546 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1547 <&gcc GCC_BLSP1_AHB_CLK>;
1548 clock-names = "core", "iface";
1549 pinctrl-names = "default", "sleep";
1550 pinctrl-0 = <&i2c1_default>;
1551 pinctrl-1 = <&i2c1_sleep>;
1552 #address-cells = <1>;
1553 #size-cells = <0>;
1554 status = "disabled";
1555 };
1556
1557 blsp_spi1: spi@78b5000 {
1558 compatible = "qcom,spi-qup-v2.2.1";
1559 reg = <0x078b5000 0x500>;
1560 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1561 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1562 <&gcc GCC_BLSP1_AHB_CLK>;
1563 clock-names = "core", "iface";
1564 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1565 dma-names = "tx", "rx";
1566 pinctrl-names = "default", "sleep";
1567 pinctrl-0 = <&spi1_default>;
1568 pinctrl-1 = <&spi1_sleep>;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 status = "disabled";
1572 };
1573
1574 blsp_i2c2: i2c@78b6000 {
1575 compatible = "qcom,i2c-qup-v2.2.1";
1576 reg = <0x078b6000 0x500>;
1577 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1578 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1579 <&gcc GCC_BLSP1_AHB_CLK>;
1580 clock-names = "core", "iface";
1581 pinctrl-names = "default", "sleep";
1582 pinctrl-0 = <&i2c2_default>;
1583 pinctrl-1 = <&i2c2_sleep>;
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1586 status = "disabled";
1587 };
1588
1589 blsp_spi2: spi@78b6000 {
1590 compatible = "qcom,spi-qup-v2.2.1";
1591 reg = <0x078b6000 0x500>;
1592 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1593 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1594 <&gcc GCC_BLSP1_AHB_CLK>;
1595 clock-names = "core", "iface";
1596 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1597 dma-names = "tx", "rx";
1598 pinctrl-names = "default", "sleep";
1599 pinctrl-0 = <&spi2_default>;
1600 pinctrl-1 = <&spi2_sleep>;
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1603 status = "disabled";
1604 };
1605
1606 blsp_i2c3: i2c@78b7000 {
1607 compatible = "qcom,i2c-qup-v2.2.1";
1608 reg = <0x078b7000 0x500>;
1609 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1610 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1611 <&gcc GCC_BLSP1_AHB_CLK>;
1612 clock-names = "core", "iface";
1613 pinctrl-names = "default", "sleep";
1614 pinctrl-0 = <&i2c3_default>;
1615 pinctrl-1 = <&i2c3_sleep>;
1616 #address-cells = <1>;
1617 #size-cells = <0>;
1618 status = "disabled";
1619 };
1620
1621 blsp_spi3: spi@78b7000 {
1622 compatible = "qcom,spi-qup-v2.2.1";
1623 reg = <0x078b7000 0x500>;
1624 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1625 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1626 <&gcc GCC_BLSP1_AHB_CLK>;
1627 clock-names = "core", "iface";
1628 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1629 dma-names = "tx", "rx";
1630 pinctrl-names = "default", "sleep";
1631 pinctrl-0 = <&spi3_default>;
1632 pinctrl-1 = <&spi3_sleep>;
1633 #address-cells = <1>;
1634 #size-cells = <0>;
1635 status = "disabled";
1636 };
1637
1638 blsp_i2c4: i2c@78b8000 {
1639 compatible = "qcom,i2c-qup-v2.2.1";
1640 reg = <0x078b8000 0x500>;
1641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1643 <&gcc GCC_BLSP1_AHB_CLK>;
1644 clock-names = "core", "iface";
1645 pinctrl-names = "default", "sleep";
1646 pinctrl-0 = <&i2c4_default>;
1647 pinctrl-1 = <&i2c4_sleep>;
1648 #address-cells = <1>;
1649 #size-cells = <0>;
1650 status = "disabled";
1651 };
1652
1653 blsp_spi4: spi@78b8000 {
1654 compatible = "qcom,spi-qup-v2.2.1";
1655 reg = <0x078b8000 0x500>;
1656 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1657 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1658 <&gcc GCC_BLSP1_AHB_CLK>;
1659 clock-names = "core", "iface";
1660 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1661 dma-names = "tx", "rx";
1662 pinctrl-names = "default", "sleep";
1663 pinctrl-0 = <&spi4_default>;
1664 pinctrl-1 = <&spi4_sleep>;
1665 #address-cells = <1>;
1666 #size-cells = <0>;
1667 status = "disabled";
1668 };
1669
1670 blsp_i2c5: i2c@78b9000 {
1671 compatible = "qcom,i2c-qup-v2.2.1";
1672 reg = <0x078b9000 0x500>;
1673 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1674 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1675 <&gcc GCC_BLSP1_AHB_CLK>;
1676 clock-names = "core", "iface";
1677 pinctrl-names = "default", "sleep";
1678 pinctrl-0 = <&i2c5_default>;
1679 pinctrl-1 = <&i2c5_sleep>;
1680 #address-cells = <1>;
1681 #size-cells = <0>;
1682 status = "disabled";
1683 };
1684
1685 blsp_spi5: spi@78b9000 {
1686 compatible = "qcom,spi-qup-v2.2.1";
1687 reg = <0x078b9000 0x500>;
1688 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1689 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1690 <&gcc GCC_BLSP1_AHB_CLK>;
1691 clock-names = "core", "iface";
1692 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1693 dma-names = "tx", "rx";
1694 pinctrl-names = "default", "sleep";
1695 pinctrl-0 = <&spi5_default>;
1696 pinctrl-1 = <&spi5_sleep>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1699 status = "disabled";
1700 };
1701
1702 blsp_i2c6: i2c@78ba000 {
1703 compatible = "qcom,i2c-qup-v2.2.1";
1704 reg = <0x078ba000 0x500>;
1705 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1706 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1707 <&gcc GCC_BLSP1_AHB_CLK>;
1708 clock-names = "core", "iface";
1709 pinctrl-names = "default", "sleep";
1710 pinctrl-0 = <&i2c6_default>;
1711 pinctrl-1 = <&i2c6_sleep>;
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1714 status = "disabled";
1715 };
1716
1717 blsp_spi6: spi@78ba000 {
1718 compatible = "qcom,spi-qup-v2.2.1";
1719 reg = <0x078ba000 0x500>;
1720 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1721 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1722 <&gcc GCC_BLSP1_AHB_CLK>;
1723 clock-names = "core", "iface";
1724 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1725 dma-names = "tx", "rx";
1726 pinctrl-names = "default", "sleep";
1727 pinctrl-0 = <&spi6_default>;
1728 pinctrl-1 = <&spi6_sleep>;
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1731 status = "disabled";
1732 };
1733
1734 usb: usb@78d9000 {
1735 compatible = "qcom,ci-hdrc";
1736 reg = <0x078d9000 0x200>,
1737 <0x078d9200 0x200>;
1738 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1740 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1741 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1742 clock-names = "iface", "core";
1743 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1744 assigned-clock-rates = <80000000>;
1745 resets = <&gcc GCC_USB_HS_BCR>;
1746 reset-names = "core";
1747 phy_type = "ulpi";
1748 dr_mode = "otg";
1749 hnp-disable;
1750 srp-disable;
1751 adp-disable;
1752 ahb-burst-config = <0>;
1753 phy-names = "usb-phy";
1754 phys = <&usb_hs_phy>;
1755 status = "disabled";
1756 #reset-cells = <1>;
1757
1758 ulpi {
1759 usb_hs_phy: phy {
1760 compatible = "qcom,usb-hs-phy-msm8916",
1761 "qcom,usb-hs-phy";
1762 #phy-cells = <0>;
1763 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1764 clock-names = "ref", "sleep";
1765 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1766 reset-names = "phy", "por";
1767 qcom,init-seq = /bits/ 8 <0x0 0x44>,
1768 <0x1 0x6b>,
1769 <0x2 0x24>,
1770 <0x3 0x13>;
1771 };
1772 };
1773 };
1774
1775 pronto: remoteproc@a21b000 {
1776 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1777 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1778 reg-names = "ccu", "dxe", "pmu";
1779
1780 memory-region = <&wcnss_mem>;
1781
1782 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1783 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1784 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1785 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1786 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1787 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1788
1789 power-domains = <&rpmpd MSM8916_VDDCX>,
1790 <&rpmpd MSM8916_VDDMX>;
1791 power-domain-names = "cx", "mx";
1792
1793 qcom,smem-states = <&wcnss_smp2p_out 0>;
1794 qcom,smem-state-names = "stop";
1795
1796 pinctrl-names = "default";
1797 pinctrl-0 = <&wcnss_pin_a>;
1798
1799 status = "disabled";
1800
1801 iris {
1802 compatible = "qcom,wcn3620";
1803
1804 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1805 clock-names = "xo";
1806 };
1807
1808 smd-edge {
1809 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1810
1811 qcom,ipc = <&apcs 8 17>;
1812 qcom,smd-edge = <6>;
1813 qcom,remote-pid = <4>;
1814
1815 label = "pronto";
1816
1817 wcnss_ctrl: wcnss {
1818 compatible = "qcom,wcnss";
1819 qcom,smd-channels = "WCNSS_CTRL";
1820
1821 qcom,mmio = <&pronto>;
1822
1823 bluetooth {
1824 compatible = "qcom,wcnss-bt";
1825 };
1826
1827 wifi {
1828 compatible = "qcom,wcnss-wlan";
1829
1830 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1832 interrupt-names = "tx", "rx";
1833
1834 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1835 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1836 };
1837 };
1838 };
1839 };
1840
1841 intc: interrupt-controller@b000000 {
1842 compatible = "qcom,msm-qgic2";
1843 interrupt-controller;
1844 #interrupt-cells = <3>;
1845 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1846 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1847 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1848 };
1849
1850 apcs: mailbox@b011000 {
1851 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1852 reg = <0x0b011000 0x1000>;
1853 #mbox-cells = <1>;
1854 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1855 clock-names = "pll", "aux";
1856 #clock-cells = <0>;
1857 };
1858
1859 a53pll: clock@b016000 {
1860 compatible = "qcom,msm8916-a53pll";
1861 reg = <0x0b016000 0x40>;
1862 #clock-cells = <0>;
1863 clocks = <&xo_board>;
1864 clock-names = "xo";
1865 };
1866
1867 timer@b020000 {
1868 #address-cells = <1>;
1869 #size-cells = <1>;
1870 ranges;
1871 compatible = "arm,armv7-timer-mem";
1872 reg = <0x0b020000 0x1000>;
1873 clock-frequency = <19200000>;
1874
1875 frame@b021000 {
1876 frame-number = <0>;
1877 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1879 reg = <0x0b021000 0x1000>,
1880 <0x0b022000 0x1000>;
1881 };
1882
1883 frame@b023000 {
1884 frame-number = <1>;
1885 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1886 reg = <0x0b023000 0x1000>;
1887 status = "disabled";
1888 };
1889
1890 frame@b024000 {
1891 frame-number = <2>;
1892 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1893 reg = <0x0b024000 0x1000>;
1894 status = "disabled";
1895 };
1896
1897 frame@b025000 {
1898 frame-number = <3>;
1899 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1900 reg = <0x0b025000 0x1000>;
1901 status = "disabled";
1902 };
1903
1904 frame@b026000 {
1905 frame-number = <4>;
1906 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1907 reg = <0x0b026000 0x1000>;
1908 status = "disabled";
1909 };
1910
1911 frame@b027000 {
1912 frame-number = <5>;
1913 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1914 reg = <0x0b027000 0x1000>;
1915 status = "disabled";
1916 };
1917
1918 frame@b028000 {
1919 frame-number = <6>;
1920 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1921 reg = <0x0b028000 0x1000>;
1922 status = "disabled";
1923 };
1924 };
1925
1926 cpu0_acc: power-manager@b088000 {
1927 compatible = "qcom,msm8916-acc";
1928 reg = <0x0b088000 0x1000>;
1929 status = "reserved"; /* Controlled by PSCI firmware */
1930 };
1931
1932 cpu0_saw: power-manager@b089000 {
1933 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1934 reg = <0x0b089000 0x1000>;
1935 status = "reserved"; /* Controlled by PSCI firmware */
1936 };
1937
1938 cpu1_acc: power-manager@b098000 {
1939 compatible = "qcom,msm8916-acc";
1940 reg = <0x0b098000 0x1000>;
1941 status = "reserved"; /* Controlled by PSCI firmware */
1942 };
1943
1944 cpu1_saw: power-manager@b099000 {
1945 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1946 reg = <0x0b099000 0x1000>;
1947 status = "reserved"; /* Controlled by PSCI firmware */
1948 };
1949
1950 cpu2_acc: power-manager@b0a8000 {
1951 compatible = "qcom,msm8916-acc";
1952 reg = <0x0b0a8000 0x1000>;
1953 status = "reserved"; /* Controlled by PSCI firmware */
1954 };
1955
1956 cpu2_saw: power-manager@b0a9000 {
1957 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1958 reg = <0x0b0a9000 0x1000>;
1959 status = "reserved"; /* Controlled by PSCI firmware */
1960 };
1961
1962 cpu3_acc: power-manager@b0b8000 {
1963 compatible = "qcom,msm8916-acc";
1964 reg = <0x0b0b8000 0x1000>;
1965 status = "reserved"; /* Controlled by PSCI firmware */
1966 };
1967
1968 cpu3_saw: power-manager@b0b9000 {
1969 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1970 reg = <0x0b0b9000 0x1000>;
1971 status = "reserved"; /* Controlled by PSCI firmware */
1972 };
1973 };
1974
1975 thermal-zones {
1976 cpu0-1-thermal {
1977 polling-delay-passive = <250>;
1978 polling-delay = <1000>;
1979
1980 thermal-sensors = <&tsens 5>;
1981
1982 trips {
1983 cpu0_1_alert0: trip-point0 {
1984 temperature = <75000>;
1985 hysteresis = <2000>;
1986 type = "passive";
1987 };
1988 cpu0_1_crit: cpu_crit {
1989 temperature = <110000>;
1990 hysteresis = <2000>;
1991 type = "critical";
1992 };
1993 };
1994
1995 cooling-maps {
1996 map0 {
1997 trip = <&cpu0_1_alert0>;
1998 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1999 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2000 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2001 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2002 };
2003 };
2004 };
2005
2006 cpu2-3-thermal {
2007 polling-delay-passive = <250>;
2008 polling-delay = <1000>;
2009
2010 thermal-sensors = <&tsens 4>;
2011
2012 trips {
2013 cpu2_3_alert0: trip-point0 {
2014 temperature = <75000>;
2015 hysteresis = <2000>;
2016 type = "passive";
2017 };
2018 cpu2_3_crit: cpu_crit {
2019 temperature = <110000>;
2020 hysteresis = <2000>;
2021 type = "critical";
2022 };
2023 };
2024
2025 cooling-maps {
2026 map0 {
2027 trip = <&cpu2_3_alert0>;
2028 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2029 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2030 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2031 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2032 };
2033 };
2034 };
2035
2036 gpu-thermal {
2037 polling-delay-passive = <250>;
2038 polling-delay = <1000>;
2039
2040 thermal-sensors = <&tsens 2>;
2041
2042 trips {
2043 gpu_alert0: trip-point0 {
2044 temperature = <75000>;
2045 hysteresis = <2000>;
2046 type = "passive";
2047 };
2048 gpu_crit: gpu_crit {
2049 temperature = <95000>;
2050 hysteresis = <2000>;
2051 type = "critical";
2052 };
2053 };
2054 };
2055
2056 camera-thermal {
2057 polling-delay-passive = <250>;
2058 polling-delay = <1000>;
2059
2060 thermal-sensors = <&tsens 1>;
2061
2062 trips {
2063 cam_alert0: trip-point0 {
2064 temperature = <75000>;
2065 hysteresis = <2000>;
2066 type = "hot";
2067 };
2068 };
2069 };
2070
2071 modem-thermal {
2072 polling-delay-passive = <250>;
2073 polling-delay = <1000>;
2074
2075 thermal-sensors = <&tsens 0>;
2076
2077 trips {
2078 modem_alert0: trip-point0 {
2079 temperature = <85000>;
2080 hysteresis = <2000>;
2081 type = "hot";
2082 };
2083 };
2084 };
2085
2086 };
2087
2088 timer {
2089 compatible = "arm,armv8-timer";
2090 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2091 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2092 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2093 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2094 };
2095 };
2096
2097 #include "msm8916-pins.dtsi"
