0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
0008
0009 / {
0010 #address-cells = <2>;
0011 #size-cells = <2>;
0012
0013 model = "Qualcomm Technologies, Inc. IPQ8074";
0014 compatible = "qcom,ipq8074";
0015 interrupt-parent = <&intc>;
0016
0017 clocks {
0018 sleep_clk: sleep_clk {
0019 compatible = "fixed-clock";
0020 clock-frequency = <32768>;
0021 #clock-cells = <0>;
0022 };
0023
0024 xo: xo {
0025 compatible = "fixed-clock";
0026 clock-frequency = <19200000>;
0027 #clock-cells = <0>;
0028 };
0029 };
0030
0031 cpus {
0032 #address-cells = <0x1>;
0033 #size-cells = <0x0>;
0034
0035 CPU0: cpu@0 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a53";
0038 reg = <0x0>;
0039 next-level-cache = <&L2_0>;
0040 enable-method = "psci";
0041 };
0042
0043 CPU1: cpu@1 {
0044 device_type = "cpu";
0045 compatible = "arm,cortex-a53";
0046 enable-method = "psci";
0047 reg = <0x1>;
0048 next-level-cache = <&L2_0>;
0049 };
0050
0051 CPU2: cpu@2 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a53";
0054 enable-method = "psci";
0055 reg = <0x2>;
0056 next-level-cache = <&L2_0>;
0057 };
0058
0059 CPU3: cpu@3 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a53";
0062 enable-method = "psci";
0063 reg = <0x3>;
0064 next-level-cache = <&L2_0>;
0065 };
0066
0067 L2_0: l2-cache {
0068 compatible = "cache";
0069 cache-level = <0x2>;
0070 };
0071 };
0072
0073 pmu {
0074 compatible = "arm,cortex-a53-pmu";
0075 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0076 };
0077
0078 psci {
0079 compatible = "arm,psci-1.0";
0080 method = "smc";
0081 };
0082
0083 reserved-memory {
0084 #address-cells = <2>;
0085 #size-cells = <2>;
0086 ranges;
0087
0088 smem@4ab00000 {
0089 compatible = "qcom,smem";
0090 reg = <0x0 0x4ab00000 0x0 0x00100000>;
0091 no-map;
0092
0093 hwlocks = <&tcsr_mutex 0>;
0094 };
0095
0096 memory@4ac00000 {
0097 no-map;
0098 reg = <0x0 0x4ac00000 0x0 0x00400000>;
0099 };
0100 };
0101
0102 firmware {
0103 scm {
0104 compatible = "qcom,scm-ipq8074", "qcom,scm";
0105 };
0106 };
0107
0108 soc: soc {
0109 #address-cells = <0x1>;
0110 #size-cells = <0x1>;
0111 ranges = <0 0 0 0xffffffff>;
0112 compatible = "simple-bus";
0113
0114 ssphy_1: phy@58000 {
0115 compatible = "qcom,ipq8074-qmp-usb3-phy";
0116 reg = <0x00058000 0x1c4>;
0117 #address-cells = <1>;
0118 #size-cells = <1>;
0119 ranges;
0120
0121 clocks = <&gcc GCC_USB1_AUX_CLK>,
0122 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
0123 <&xo>;
0124 clock-names = "aux", "cfg_ahb", "ref";
0125
0126 resets = <&gcc GCC_USB1_PHY_BCR>,
0127 <&gcc GCC_USB3PHY_1_PHY_BCR>;
0128 reset-names = "phy","common";
0129 status = "disabled";
0130
0131 usb1_ssphy: phy@58200 {
0132 reg = <0x00058200 0x130>, /* Tx */
0133 <0x00058400 0x200>, /* Rx */
0134 <0x00058800 0x1f8>, /* PCS */
0135 <0x00058600 0x044>; /* PCS misc*/
0136 #phy-cells = <0>;
0137 #clock-cells = <0>;
0138 clocks = <&gcc GCC_USB1_PIPE_CLK>;
0139 clock-names = "pipe0";
0140 clock-output-names = "gcc_usb1_pipe_clk_src";
0141 };
0142 };
0143
0144 qusb_phy_1: phy@59000 {
0145 compatible = "qcom,ipq8074-qusb2-phy";
0146 reg = <0x00059000 0x180>;
0147 #phy-cells = <0>;
0148
0149 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
0150 <&xo>;
0151 clock-names = "cfg_ahb", "ref";
0152
0153 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
0154 status = "disabled";
0155 };
0156
0157 ssphy_0: phy@78000 {
0158 compatible = "qcom,ipq8074-qmp-usb3-phy";
0159 reg = <0x00078000 0x1c4>;
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 ranges;
0163
0164 clocks = <&gcc GCC_USB0_AUX_CLK>,
0165 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
0166 <&xo>;
0167 clock-names = "aux", "cfg_ahb", "ref";
0168
0169 resets = <&gcc GCC_USB0_PHY_BCR>,
0170 <&gcc GCC_USB3PHY_0_PHY_BCR>;
0171 reset-names = "phy","common";
0172 status = "disabled";
0173
0174 usb0_ssphy: phy@78200 {
0175 reg = <0x00078200 0x130>, /* Tx */
0176 <0x00078400 0x200>, /* Rx */
0177 <0x00078800 0x1f8>, /* PCS */
0178 <0x00078600 0x044>; /* PCS misc*/
0179 #phy-cells = <0>;
0180 #clock-cells = <0>;
0181 clocks = <&gcc GCC_USB0_PIPE_CLK>;
0182 clock-names = "pipe0";
0183 clock-output-names = "gcc_usb0_pipe_clk_src";
0184 };
0185 };
0186
0187 qusb_phy_0: phy@79000 {
0188 compatible = "qcom,ipq8074-qusb2-phy";
0189 reg = <0x00079000 0x180>;
0190 #phy-cells = <0>;
0191
0192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
0193 <&xo>;
0194 clock-names = "cfg_ahb", "ref";
0195
0196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
0197 status = "disabled";
0198 };
0199
0200 pcie_qmp0: phy@86000 {
0201 compatible = "qcom,ipq8074-qmp-pcie-phy";
0202 reg = <0x00086000 0x1000>;
0203 #address-cells = <1>;
0204 #size-cells = <1>;
0205 ranges;
0206
0207 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
0208 <&gcc GCC_PCIE0_AHB_CLK>;
0209 clock-names = "aux", "cfg_ahb";
0210 resets = <&gcc GCC_PCIE0_PHY_BCR>,
0211 <&gcc GCC_PCIE0PHY_PHY_BCR>;
0212 reset-names = "phy",
0213 "common";
0214 status = "disabled";
0215
0216 pcie_phy0: phy@86200 {
0217 reg = <0x86200 0x16c>,
0218 <0x86400 0x200>,
0219 <0x86800 0x4f4>;
0220 #phy-cells = <0>;
0221 #clock-cells = <0>;
0222 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
0223 clock-names = "pipe0";
0224 clock-output-names = "pcie_0_pipe_clk";
0225 };
0226 };
0227
0228 pcie_qmp1: phy@8e000 {
0229 compatible = "qcom,ipq8074-qmp-pcie-phy";
0230 reg = <0x0008e000 0x1000>;
0231 #address-cells = <1>;
0232 #size-cells = <1>;
0233 ranges;
0234
0235 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
0236 <&gcc GCC_PCIE1_AHB_CLK>;
0237 clock-names = "aux", "cfg_ahb";
0238 resets = <&gcc GCC_PCIE1_PHY_BCR>,
0239 <&gcc GCC_PCIE1PHY_PHY_BCR>;
0240 reset-names = "phy",
0241 "common";
0242 status = "disabled";
0243
0244 pcie_phy1: phy@8e200 {
0245 reg = <0x8e200 0x16c>,
0246 <0x8e400 0x200>,
0247 <0x8e800 0x4f4>;
0248 #phy-cells = <0>;
0249 #clock-cells = <0>;
0250 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
0251 clock-names = "pipe0";
0252 clock-output-names = "pcie_1_pipe_clk";
0253 };
0254 };
0255
0256 mdio: mdio@90000 {
0257 compatible = "qcom,ipq4019-mdio";
0258 reg = <0x00090000 0x64>;
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261
0262 clocks = <&gcc GCC_MDIO_AHB_CLK>;
0263 clock-names = "gcc_mdio_ahb_clk";
0264
0265 status = "disabled";
0266 };
0267
0268 prng: rng@e3000 {
0269 compatible = "qcom,prng-ee";
0270 reg = <0x000e3000 0x1000>;
0271 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0272 clock-names = "core";
0273 status = "disabled";
0274 };
0275
0276 cryptobam: dma-controller@704000 {
0277 compatible = "qcom,bam-v1.7.0";
0278 reg = <0x00704000 0x20000>;
0279 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
0280 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
0281 clock-names = "bam_clk";
0282 #dma-cells = <1>;
0283 qcom,ee = <1>;
0284 qcom,controlled-remotely;
0285 status = "disabled";
0286 };
0287
0288 crypto: crypto@73a000 {
0289 compatible = "qcom,crypto-v5.1";
0290 reg = <0x0073a000 0x6000>;
0291 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
0292 <&gcc GCC_CRYPTO_AXI_CLK>,
0293 <&gcc GCC_CRYPTO_CLK>;
0294 clock-names = "iface", "bus", "core";
0295 dmas = <&cryptobam 2>, <&cryptobam 3>;
0296 dma-names = "rx", "tx";
0297 status = "disabled";
0298 };
0299
0300 tlmm: pinctrl@1000000 {
0301 compatible = "qcom,ipq8074-pinctrl";
0302 reg = <0x01000000 0x300000>;
0303 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0304 gpio-controller;
0305 gpio-ranges = <&tlmm 0 0 70>;
0306 #gpio-cells = <0x2>;
0307 interrupt-controller;
0308 #interrupt-cells = <0x2>;
0309
0310 serial_4_pins: serial4-pinmux {
0311 pins = "gpio23", "gpio24";
0312 function = "blsp4_uart1";
0313 drive-strength = <8>;
0314 bias-disable;
0315 };
0316
0317 i2c_0_pins: i2c-0-pinmux {
0318 pins = "gpio42", "gpio43";
0319 function = "blsp1_i2c";
0320 drive-strength = <8>;
0321 bias-disable;
0322 };
0323
0324 spi_0_pins: spi-0-pins {
0325 pins = "gpio38", "gpio39", "gpio40", "gpio41";
0326 function = "blsp0_spi";
0327 drive-strength = <8>;
0328 bias-disable;
0329 };
0330
0331 hsuart_pins: hsuart-pins {
0332 pins = "gpio46", "gpio47", "gpio48", "gpio49";
0333 function = "blsp2_uart";
0334 drive-strength = <8>;
0335 bias-disable;
0336 };
0337
0338 qpic_pins: qpic-pins {
0339 pins = "gpio1", "gpio3", "gpio4",
0340 "gpio5", "gpio6", "gpio7",
0341 "gpio8", "gpio10", "gpio11",
0342 "gpio12", "gpio13", "gpio14",
0343 "gpio15", "gpio16", "gpio17";
0344 function = "qpic";
0345 drive-strength = <8>;
0346 bias-disable;
0347 };
0348 };
0349
0350 gcc: gcc@1800000 {
0351 compatible = "qcom,gcc-ipq8074";
0352 reg = <0x01800000 0x80000>;
0353 #clock-cells = <0x1>;
0354 #power-domain-cells = <1>;
0355 #reset-cells = <0x1>;
0356 };
0357
0358 tcsr_mutex: hwlock@1905000 {
0359 compatible = "qcom,tcsr-mutex";
0360 reg = <0x01905000 0x20000>;
0361 #hwlock-cells = <1>;
0362 };
0363
0364 spmi_bus: spmi@200f000 {
0365 compatible = "qcom,spmi-pmic-arb";
0366 reg = <0x0200f000 0x001000>,
0367 <0x02400000 0x800000>,
0368 <0x02c00000 0x800000>,
0369 <0x03800000 0x200000>,
0370 <0x0200a000 0x000700>;
0371 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
0372 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0373 interrupt-names = "periph_irq";
0374 qcom,ee = <0>;
0375 qcom,channel = <0>;
0376 #address-cells = <2>;
0377 #size-cells = <0>;
0378 interrupt-controller;
0379 #interrupt-cells = <4>;
0380 cell-index = <0>;
0381 };
0382
0383 sdhc_1: mmc@7824900 {
0384 compatible = "qcom,sdhci-msm-v4";
0385 reg = <0x7824900 0x500>, <0x7824000 0x800>;
0386 reg-names = "hc_mem", "core_mem";
0387
0388 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0389 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0390 interrupt-names = "hc_irq", "pwr_irq";
0391
0392 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0393 <&gcc GCC_SDCC1_APPS_CLK>,
0394 <&xo>;
0395 clock-names = "iface", "core", "xo";
0396 resets = <&gcc GCC_SDCC1_BCR>;
0397 max-frequency = <384000000>;
0398 mmc-ddr-1_8v;
0399 mmc-hs200-1_8v;
0400 mmc-hs400-1_8v;
0401 bus-width = <8>;
0402
0403 status = "disabled";
0404 };
0405
0406 blsp_dma: dma-controller@7884000 {
0407 compatible = "qcom,bam-v1.7.0";
0408 reg = <0x07884000 0x2b000>;
0409 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
0410 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
0411 clock-names = "bam_clk";
0412 #dma-cells = <1>;
0413 qcom,ee = <0>;
0414 };
0415
0416 blsp1_uart1: serial@78af000 {
0417 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0418 reg = <0x078af000 0x200>;
0419 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0420 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
0421 <&gcc GCC_BLSP1_AHB_CLK>;
0422 clock-names = "core", "iface";
0423 status = "disabled";
0424 };
0425
0426 blsp1_uart3: serial@78b1000 {
0427 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0428 reg = <0x078b1000 0x200>;
0429 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
0430 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
0431 <&gcc GCC_BLSP1_AHB_CLK>;
0432 clock-names = "core", "iface";
0433 dmas = <&blsp_dma 4>,
0434 <&blsp_dma 5>;
0435 dma-names = "tx", "rx";
0436 pinctrl-0 = <&hsuart_pins>;
0437 pinctrl-names = "default";
0438 status = "disabled";
0439 };
0440
0441 blsp1_uart5: serial@78b3000 {
0442 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0443 reg = <0x078b3000 0x200>;
0444 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
0445 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
0446 <&gcc GCC_BLSP1_AHB_CLK>;
0447 clock-names = "core", "iface";
0448 pinctrl-0 = <&serial_4_pins>;
0449 pinctrl-names = "default";
0450 status = "disabled";
0451 };
0452
0453 blsp1_spi1: spi@78b5000 {
0454 compatible = "qcom,spi-qup-v2.2.1";
0455 #address-cells = <1>;
0456 #size-cells = <0>;
0457 reg = <0x078b5000 0x600>;
0458 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0459 spi-max-frequency = <50000000>;
0460 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
0461 <&gcc GCC_BLSP1_AHB_CLK>;
0462 clock-names = "core", "iface";
0463 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
0464 dma-names = "tx", "rx";
0465 pinctrl-0 = <&spi_0_pins>;
0466 pinctrl-names = "default";
0467 status = "disabled";
0468 };
0469
0470 blsp1_i2c2: i2c@78b6000 {
0471 compatible = "qcom,i2c-qup-v2.2.1";
0472 #address-cells = <1>;
0473 #size-cells = <0>;
0474 reg = <0x078b6000 0x600>;
0475 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0476 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
0477 <&gcc GCC_BLSP1_AHB_CLK>;
0478 clock-names = "core", "iface";
0479 clock-frequency = <400000>;
0480 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
0481 dma-names = "tx", "rx";
0482 pinctrl-0 = <&i2c_0_pins>;
0483 pinctrl-names = "default";
0484 status = "disabled";
0485 };
0486
0487 blsp1_i2c3: i2c@78b7000 {
0488 compatible = "qcom,i2c-qup-v2.2.1";
0489 #address-cells = <1>;
0490 #size-cells = <0>;
0491 reg = <0x078b7000 0x600>;
0492 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0493 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
0494 <&gcc GCC_BLSP1_AHB_CLK>;
0495 clock-names = "core", "iface";
0496 clock-frequency = <100000>;
0497 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
0498 dma-names = "tx", "rx";
0499 status = "disabled";
0500 };
0501
0502 blsp1_i2c5: i2c@78b9000 {
0503 compatible = "qcom,i2c-qup-v2.2.1";
0504 #address-cells = <1>;
0505 #size-cells = <0>;
0506 reg = <0x78b9000 0x600>;
0507 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
0508 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
0509 <&gcc GCC_BLSP1_AHB_CLK>;
0510 clock-names = "core", "iface";
0511 clock-frequency = <400000>;
0512 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
0513 dma-names = "tx", "rx";
0514 status = "disabled";
0515 };
0516
0517 blsp1_i2c6: i2c@78ba000 {
0518 compatible = "qcom,i2c-qup-v2.2.1";
0519 #address-cells = <1>;
0520 #size-cells = <0>;
0521 reg = <0x078ba000 0x600>;
0522 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
0523 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
0524 <&gcc GCC_BLSP1_AHB_CLK>;
0525 clock-names = "core", "iface";
0526 clock-frequency = <100000>;
0527 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
0528 dma-names = "tx", "rx";
0529 status = "disabled";
0530 };
0531
0532 qpic_bam: dma-controller@7984000 {
0533 compatible = "qcom,bam-v1.7.0";
0534 reg = <0x07984000 0x1a000>;
0535 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0536 clocks = <&gcc GCC_QPIC_AHB_CLK>;
0537 clock-names = "bam_clk";
0538 #dma-cells = <1>;
0539 qcom,ee = <0>;
0540 status = "disabled";
0541 };
0542
0543 qpic_nand: nand-controller@79b0000 {
0544 compatible = "qcom,ipq8074-nand";
0545 reg = <0x079b0000 0x10000>;
0546 #address-cells = <1>;
0547 #size-cells = <0>;
0548 clocks = <&gcc GCC_QPIC_CLK>,
0549 <&gcc GCC_QPIC_AHB_CLK>;
0550 clock-names = "core", "aon";
0551
0552 dmas = <&qpic_bam 0>,
0553 <&qpic_bam 1>,
0554 <&qpic_bam 2>;
0555 dma-names = "tx", "rx", "cmd";
0556 pinctrl-0 = <&qpic_pins>;
0557 pinctrl-names = "default";
0558 status = "disabled";
0559 };
0560
0561 usb_0: usb@8af8800 {
0562 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
0563 reg = <0x08af8800 0x400>;
0564 #address-cells = <1>;
0565 #size-cells = <1>;
0566 ranges;
0567
0568 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
0569 <&gcc GCC_USB0_MASTER_CLK>,
0570 <&gcc GCC_USB0_SLEEP_CLK>,
0571 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
0572 clock-names = "cfg_noc",
0573 "core",
0574 "sleep",
0575 "mock_utmi";
0576
0577 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
0578 <&gcc GCC_USB0_MASTER_CLK>,
0579 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
0580 assigned-clock-rates = <133330000>,
0581 <133330000>,
0582 <19200000>;
0583
0584 power-domains = <&gcc USB0_GDSC>;
0585
0586 resets = <&gcc GCC_USB0_BCR>;
0587 status = "disabled";
0588
0589 dwc_0: usb@8a00000 {
0590 compatible = "snps,dwc3";
0591 reg = <0x8a00000 0xcd00>;
0592 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0593 phys = <&qusb_phy_0>, <&usb0_ssphy>;
0594 phy-names = "usb2-phy", "usb3-phy";
0595 snps,is-utmi-l1-suspend;
0596 snps,hird-threshold = /bits/ 8 <0x0>;
0597 snps,dis_u2_susphy_quirk;
0598 snps,dis_u3_susphy_quirk;
0599 dr_mode = "host";
0600 };
0601 };
0602
0603 usb_1: usb@8cf8800 {
0604 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
0605 reg = <0x08cf8800 0x400>;
0606 #address-cells = <1>;
0607 #size-cells = <1>;
0608 ranges;
0609
0610 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
0611 <&gcc GCC_USB1_MASTER_CLK>,
0612 <&gcc GCC_USB1_SLEEP_CLK>,
0613 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
0614 clock-names = "cfg_noc",
0615 "core",
0616 "sleep",
0617 "mock_utmi";
0618
0619 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
0620 <&gcc GCC_USB1_MASTER_CLK>,
0621 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
0622 assigned-clock-rates = <133330000>,
0623 <133330000>,
0624 <19200000>;
0625
0626 power-domains = <&gcc USB1_GDSC>;
0627
0628 resets = <&gcc GCC_USB1_BCR>;
0629 status = "disabled";
0630
0631 dwc_1: usb@8c00000 {
0632 compatible = "snps,dwc3";
0633 reg = <0x8c00000 0xcd00>;
0634 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0635 phys = <&qusb_phy_1>, <&usb1_ssphy>;
0636 phy-names = "usb2-phy", "usb3-phy";
0637 snps,is-utmi-l1-suspend;
0638 snps,hird-threshold = /bits/ 8 <0x0>;
0639 snps,dis_u2_susphy_quirk;
0640 snps,dis_u3_susphy_quirk;
0641 dr_mode = "host";
0642 };
0643 };
0644
0645 intc: interrupt-controller@b000000 {
0646 compatible = "qcom,msm-qgic2";
0647 #address-cells = <1>;
0648 #size-cells = <1>;
0649 interrupt-controller;
0650 #interrupt-cells = <0x3>;
0651 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
0652 ranges = <0 0xb00a000 0xffd>;
0653
0654 v2m@0 {
0655 compatible = "arm,gic-v2m-frame";
0656 msi-controller;
0657 reg = <0x0 0xffd>;
0658 };
0659 };
0660
0661 watchdog: watchdog@b017000 {
0662 compatible = "qcom,kpss-wdt";
0663 reg = <0xb017000 0x1000>;
0664 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
0665 clocks = <&sleep_clk>;
0666 timeout-sec = <30>;
0667 };
0668
0669 apcs_glb: mailbox@b111000 {
0670 compatible = "qcom,ipq8074-apcs-apps-global";
0671 reg = <0x0b111000 0x6000>;
0672
0673 #clock-cells = <1>;
0674 #mbox-cells = <1>;
0675 };
0676
0677 timer@b120000 {
0678 #address-cells = <1>;
0679 #size-cells = <1>;
0680 ranges;
0681 compatible = "arm,armv7-timer-mem";
0682 reg = <0x0b120000 0x1000>;
0683
0684 frame@b120000 {
0685 frame-number = <0>;
0686 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0687 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0688 reg = <0x0b121000 0x1000>,
0689 <0x0b122000 0x1000>;
0690 };
0691
0692 frame@b123000 {
0693 frame-number = <1>;
0694 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0695 reg = <0x0b123000 0x1000>;
0696 status = "disabled";
0697 };
0698
0699 frame@b124000 {
0700 frame-number = <2>;
0701 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0702 reg = <0x0b124000 0x1000>;
0703 status = "disabled";
0704 };
0705
0706 frame@b125000 {
0707 frame-number = <3>;
0708 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0709 reg = <0x0b125000 0x1000>;
0710 status = "disabled";
0711 };
0712
0713 frame@b126000 {
0714 frame-number = <4>;
0715 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0716 reg = <0x0b126000 0x1000>;
0717 status = "disabled";
0718 };
0719
0720 frame@b127000 {
0721 frame-number = <5>;
0722 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0723 reg = <0x0b127000 0x1000>;
0724 status = "disabled";
0725 };
0726
0727 frame@b128000 {
0728 frame-number = <6>;
0729 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0730 reg = <0x0b128000 0x1000>;
0731 status = "disabled";
0732 };
0733 };
0734
0735 pcie1: pci@10000000 {
0736 compatible = "qcom,pcie-ipq8074";
0737 reg = <0x10000000 0xf1d>,
0738 <0x10000f20 0xa8>,
0739 <0x00088000 0x2000>,
0740 <0x10100000 0x1000>;
0741 reg-names = "dbi", "elbi", "parf", "config";
0742 device_type = "pci";
0743 linux,pci-domain = <1>;
0744 bus-range = <0x00 0xff>;
0745 num-lanes = <1>;
0746 #address-cells = <3>;
0747 #size-cells = <2>;
0748
0749 phys = <&pcie_phy1>;
0750 phy-names = "pciephy";
0751
0752 ranges = <0x81000000 0 0x10200000 0x10200000
0753 0 0x100000 /* downstream I/O */
0754 0x82000000 0 0x10300000 0x10300000
0755 0 0xd00000>; /* non-prefetchable memory */
0756
0757 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0758 interrupt-names = "msi";
0759 #interrupt-cells = <1>;
0760 interrupt-map-mask = <0 0 0 0x7>;
0761 interrupt-map = <0 0 0 1 &intc 0 142
0762 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
0763 <0 0 0 2 &intc 0 143
0764 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
0765 <0 0 0 3 &intc 0 144
0766 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
0767 <0 0 0 4 &intc 0 145
0768 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
0769
0770 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
0771 <&gcc GCC_PCIE1_AXI_M_CLK>,
0772 <&gcc GCC_PCIE1_AXI_S_CLK>,
0773 <&gcc GCC_PCIE1_AHB_CLK>,
0774 <&gcc GCC_PCIE1_AUX_CLK>;
0775 clock-names = "iface",
0776 "axi_m",
0777 "axi_s",
0778 "ahb",
0779 "aux";
0780 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
0781 <&gcc GCC_PCIE1_SLEEP_ARES>,
0782 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
0783 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
0784 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
0785 <&gcc GCC_PCIE1_AHB_ARES>,
0786 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
0787 reset-names = "pipe",
0788 "sleep",
0789 "sticky",
0790 "axi_m",
0791 "axi_s",
0792 "ahb",
0793 "axi_m_sticky";
0794 status = "disabled";
0795 };
0796
0797 pcie0: pci@20000000 {
0798 compatible = "qcom,pcie-ipq8074";
0799 reg = <0x20000000 0xf1d>,
0800 <0x20000f20 0xa8>,
0801 <0x00080000 0x2000>,
0802 <0x20100000 0x1000>;
0803 reg-names = "dbi", "elbi", "parf", "config";
0804 device_type = "pci";
0805 linux,pci-domain = <0>;
0806 bus-range = <0x00 0xff>;
0807 num-lanes = <1>;
0808 #address-cells = <3>;
0809 #size-cells = <2>;
0810
0811 phys = <&pcie_phy0>;
0812 phy-names = "pciephy";
0813
0814 ranges = <0x81000000 0 0x20200000 0x20200000
0815 0 0x100000 /* downstream I/O */
0816 0x82000000 0 0x20300000 0x20300000
0817 0 0xd00000>; /* non-prefetchable memory */
0818
0819 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0820 interrupt-names = "msi";
0821 #interrupt-cells = <1>;
0822 interrupt-map-mask = <0 0 0 0x7>;
0823 interrupt-map = <0 0 0 1 &intc 0 75
0824 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
0825 <0 0 0 2 &intc 0 78
0826 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
0827 <0 0 0 3 &intc 0 79
0828 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
0829 <0 0 0 4 &intc 0 83
0830 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
0831
0832 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
0833 <&gcc GCC_PCIE0_AXI_M_CLK>,
0834 <&gcc GCC_PCIE0_AXI_S_CLK>,
0835 <&gcc GCC_PCIE0_AHB_CLK>,
0836 <&gcc GCC_PCIE0_AUX_CLK>;
0837
0838 clock-names = "iface",
0839 "axi_m",
0840 "axi_s",
0841 "ahb",
0842 "aux";
0843 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
0844 <&gcc GCC_PCIE0_SLEEP_ARES>,
0845 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
0846 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
0847 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
0848 <&gcc GCC_PCIE0_AHB_ARES>,
0849 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
0850 reset-names = "pipe",
0851 "sleep",
0852 "sticky",
0853 "axi_m",
0854 "axi_s",
0855 "ahb",
0856 "axi_m_sticky";
0857 status = "disabled";
0858 };
0859 };
0860
0861 timer {
0862 compatible = "arm,armv8-timer";
0863 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0864 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0865 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0866 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0867 };
0868 };
