0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003 * IPQ6018 SoC device tree source
0004 *
0005 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
0010 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
0011 #include <dt-bindings/clock/qcom,apss-ipq.h>
0012
0013 / {
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016 interrupt-parent = <&intc>;
0017
0018 clocks {
0019 sleep_clk: sleep-clk {
0020 compatible = "fixed-clock";
0021 clock-frequency = <32000>;
0022 #clock-cells = <0>;
0023 };
0024
0025 xo: xo {
0026 compatible = "fixed-clock";
0027 clock-frequency = <24000000>;
0028 #clock-cells = <0>;
0029 };
0030 };
0031
0032 cpus: cpus {
0033 #address-cells = <1>;
0034 #size-cells = <0>;
0035
0036 CPU0: cpu@0 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a53";
0039 reg = <0x0>;
0040 enable-method = "psci";
0041 next-level-cache = <&L2_0>;
0042 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
0043 clock-names = "cpu";
0044 operating-points-v2 = <&cpu_opp_table>;
0045 cpu-supply = <&ipq6018_s2>;
0046 };
0047
0048 CPU1: cpu@1 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a53";
0051 enable-method = "psci";
0052 reg = <0x1>;
0053 next-level-cache = <&L2_0>;
0054 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
0055 clock-names = "cpu";
0056 operating-points-v2 = <&cpu_opp_table>;
0057 cpu-supply = <&ipq6018_s2>;
0058 };
0059
0060 CPU2: cpu@2 {
0061 device_type = "cpu";
0062 compatible = "arm,cortex-a53";
0063 enable-method = "psci";
0064 reg = <0x2>;
0065 next-level-cache = <&L2_0>;
0066 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
0067 clock-names = "cpu";
0068 operating-points-v2 = <&cpu_opp_table>;
0069 cpu-supply = <&ipq6018_s2>;
0070 };
0071
0072 CPU3: cpu@3 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a53";
0075 enable-method = "psci";
0076 reg = <0x3>;
0077 next-level-cache = <&L2_0>;
0078 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
0079 clock-names = "cpu";
0080 operating-points-v2 = <&cpu_opp_table>;
0081 cpu-supply = <&ipq6018_s2>;
0082 };
0083
0084 L2_0: l2-cache {
0085 compatible = "cache";
0086 cache-level = <0x2>;
0087 };
0088 };
0089
0090 cpu_opp_table: opp-table-cpu {
0091 compatible = "operating-points-v2";
0092 opp-shared;
0093
0094 opp-864000000 {
0095 opp-hz = /bits/ 64 <864000000>;
0096 opp-microvolt = <725000>;
0097 clock-latency-ns = <200000>;
0098 };
0099 opp-1056000000 {
0100 opp-hz = /bits/ 64 <1056000000>;
0101 opp-microvolt = <787500>;
0102 clock-latency-ns = <200000>;
0103 };
0104 opp-1320000000 {
0105 opp-hz = /bits/ 64 <1320000000>;
0106 opp-microvolt = <862500>;
0107 clock-latency-ns = <200000>;
0108 };
0109 opp-1440000000 {
0110 opp-hz = /bits/ 64 <1440000000>;
0111 opp-microvolt = <925000>;
0112 clock-latency-ns = <200000>;
0113 };
0114 opp-1608000000 {
0115 opp-hz = /bits/ 64 <1608000000>;
0116 opp-microvolt = <987500>;
0117 clock-latency-ns = <200000>;
0118 };
0119 opp-1800000000 {
0120 opp-hz = /bits/ 64 <1800000000>;
0121 opp-microvolt = <1062500>;
0122 clock-latency-ns = <200000>;
0123 };
0124 };
0125
0126 firmware {
0127 scm {
0128 compatible = "qcom,scm-ipq6018", "qcom,scm";
0129 };
0130 };
0131
0132 tcsr_mutex: hwlock {
0133 compatible = "qcom,tcsr-mutex";
0134 syscon = <&tcsr_mutex_regs 0 0x80>;
0135 #hwlock-cells = <1>;
0136 };
0137
0138 pmuv8: pmu {
0139 compatible = "arm,cortex-a53-pmu";
0140 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
0141 IRQ_TYPE_LEVEL_HIGH)>;
0142 };
0143
0144 psci: psci {
0145 compatible = "arm,psci-1.0";
0146 method = "smc";
0147 };
0148
0149 reserved-memory {
0150 #address-cells = <2>;
0151 #size-cells = <2>;
0152 ranges;
0153
0154 rpm_msg_ram: memory@60000 {
0155 reg = <0x0 0x60000 0x0 0x6000>;
0156 no-map;
0157 };
0158
0159 tz: memory@4a600000 {
0160 reg = <0x0 0x4a600000 0x0 0x00400000>;
0161 no-map;
0162 };
0163
0164 smem_region: memory@4aa00000 {
0165 reg = <0x0 0x4aa00000 0x0 0x00100000>;
0166 no-map;
0167 };
0168
0169 q6_region: memory@4ab00000 {
0170 reg = <0x0 0x4ab00000 0x0 0x05500000>;
0171 no-map;
0172 };
0173 };
0174
0175 smem {
0176 compatible = "qcom,smem";
0177 memory-region = <&smem_region>;
0178 hwlocks = <&tcsr_mutex 0>;
0179 };
0180
0181 soc: soc {
0182 #address-cells = <2>;
0183 #size-cells = <2>;
0184 ranges = <0 0 0 0 0x0 0xffffffff>;
0185 dma-ranges;
0186 compatible = "simple-bus";
0187
0188 prng: qrng@e1000 {
0189 compatible = "qcom,prng-ee";
0190 reg = <0x0 0xe3000 0x0 0x1000>;
0191 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0192 clock-names = "core";
0193 };
0194
0195 cryptobam: dma-controller@704000 {
0196 compatible = "qcom,bam-v1.7.0";
0197 reg = <0x0 0x00704000 0x0 0x20000>;
0198 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
0199 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
0200 clock-names = "bam_clk";
0201 #dma-cells = <1>;
0202 qcom,ee = <1>;
0203 qcom,controlled-remotely;
0204 };
0205
0206 crypto: crypto@73a000 {
0207 compatible = "qcom,crypto-v5.1";
0208 reg = <0x0 0x0073a000 0x0 0x6000>;
0209 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
0210 <&gcc GCC_CRYPTO_AXI_CLK>,
0211 <&gcc GCC_CRYPTO_CLK>;
0212 clock-names = "iface", "bus", "core";
0213 dmas = <&cryptobam 2>, <&cryptobam 3>;
0214 dma-names = "rx", "tx";
0215 };
0216
0217 tlmm: pinctrl@1000000 {
0218 compatible = "qcom,ipq6018-pinctrl";
0219 reg = <0x0 0x01000000 0x0 0x300000>;
0220 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0221 gpio-controller;
0222 #gpio-cells = <2>;
0223 gpio-ranges = <&tlmm 0 0 80>;
0224 interrupt-controller;
0225 #interrupt-cells = <2>;
0226
0227 serial_3_pins: serial3-pinmux {
0228 pins = "gpio44", "gpio45";
0229 function = "blsp2_uart";
0230 drive-strength = <8>;
0231 bias-pull-down;
0232 };
0233
0234 qpic_pins: qpic-pins {
0235 pins = "gpio1", "gpio3", "gpio4",
0236 "gpio5", "gpio6", "gpio7",
0237 "gpio8", "gpio10", "gpio11",
0238 "gpio12", "gpio13", "gpio14",
0239 "gpio15", "gpio17";
0240 function = "qpic_pad";
0241 drive-strength = <8>;
0242 bias-disable;
0243 };
0244 };
0245
0246 gcc: gcc@1800000 {
0247 compatible = "qcom,gcc-ipq6018";
0248 reg = <0x0 0x01800000 0x0 0x80000>;
0249 clocks = <&xo>, <&sleep_clk>;
0250 clock-names = "xo", "sleep_clk";
0251 #clock-cells = <1>;
0252 #reset-cells = <1>;
0253 };
0254
0255 tcsr_mutex_regs: syscon@1905000 {
0256 compatible = "syscon";
0257 reg = <0x0 0x01905000 0x0 0x8000>;
0258 };
0259
0260 tcsr: syscon@1937000 {
0261 compatible = "syscon";
0262 reg = <0x0 0x01937000 0x0 0x21000>;
0263 };
0264
0265 blsp_dma: dma-controller@7884000 {
0266 compatible = "qcom,bam-v1.7.0";
0267 reg = <0x0 0x07884000 0x0 0x2b000>;
0268 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
0269 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
0270 clock-names = "bam_clk";
0271 #dma-cells = <1>;
0272 qcom,ee = <0>;
0273 };
0274
0275 blsp1_uart3: serial@78b1000 {
0276 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0277 reg = <0x0 0x078b1000 0x0 0x200>;
0278 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
0279 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
0280 <&gcc GCC_BLSP1_AHB_CLK>;
0281 clock-names = "core", "iface";
0282 status = "disabled";
0283 };
0284
0285 blsp1_spi1: spi@78b5000 {
0286 compatible = "qcom,spi-qup-v2.2.1";
0287 #address-cells = <1>;
0288 #size-cells = <0>;
0289 reg = <0x0 0x078b5000 0x0 0x600>;
0290 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0291 spi-max-frequency = <50000000>;
0292 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
0293 <&gcc GCC_BLSP1_AHB_CLK>;
0294 clock-names = "core", "iface";
0295 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
0296 dma-names = "tx", "rx";
0297 status = "disabled";
0298 };
0299
0300 blsp1_spi2: spi@78b6000 {
0301 compatible = "qcom,spi-qup-v2.2.1";
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304 reg = <0x0 0x078b6000 0x0 0x600>;
0305 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0306 spi-max-frequency = <50000000>;
0307 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
0308 <&gcc GCC_BLSP1_AHB_CLK>;
0309 clock-names = "core", "iface";
0310 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
0311 dma-names = "tx", "rx";
0312 status = "disabled";
0313 };
0314
0315 blsp1_i2c2: i2c@78b6000 {
0316 compatible = "qcom,i2c-qup-v2.2.1";
0317 #address-cells = <1>;
0318 #size-cells = <0>;
0319 reg = <0x0 0x078b6000 0x0 0x600>;
0320 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0321 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
0322 <&gcc GCC_BLSP1_AHB_CLK>;
0323 clock-names = "core", "iface";
0324 clock-frequency = <400000>;
0325 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
0326 dma-names = "tx", "rx";
0327 status = "disabled";
0328 };
0329
0330 blsp1_i2c3: i2c@78b7000 {
0331 compatible = "qcom,i2c-qup-v2.2.1";
0332 #address-cells = <1>;
0333 #size-cells = <0>;
0334 reg = <0x0 0x078b7000 0x0 0x600>;
0335 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0336 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
0337 <&gcc GCC_BLSP1_AHB_CLK>;
0338 clock-names = "core", "iface";
0339 clock-frequency = <400000>;
0340 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
0341 dma-names = "tx", "rx";
0342 status = "disabled";
0343 };
0344
0345 qpic_bam: dma-controller@7984000 {
0346 compatible = "qcom,bam-v1.7.0";
0347 reg = <0x0 0x07984000 0x0 0x1a000>;
0348 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0349 clocks = <&gcc GCC_QPIC_AHB_CLK>;
0350 clock-names = "bam_clk";
0351 #dma-cells = <1>;
0352 qcom,ee = <0>;
0353 status = "disabled";
0354 };
0355
0356 qpic_nand: nand@79b0000 {
0357 compatible = "qcom,ipq6018-nand";
0358 reg = <0x0 0x079b0000 0x0 0x10000>;
0359 #address-cells = <1>;
0360 #size-cells = <0>;
0361 clocks = <&gcc GCC_QPIC_CLK>,
0362 <&gcc GCC_QPIC_AHB_CLK>;
0363 clock-names = "core", "aon";
0364
0365 dmas = <&qpic_bam 0>,
0366 <&qpic_bam 1>,
0367 <&qpic_bam 2>;
0368 dma-names = "tx", "rx", "cmd";
0369 pinctrl-0 = <&qpic_pins>;
0370 pinctrl-names = "default";
0371 status = "disabled";
0372 };
0373
0374 intc: interrupt-controller@b000000 {
0375 compatible = "qcom,msm-qgic2";
0376 #address-cells = <2>;
0377 #size-cells = <2>;
0378 interrupt-controller;
0379 #interrupt-cells = <0x3>;
0380 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
0381 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
0382 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
0383 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
0384 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0385 ranges = <0 0 0 0xb00a000 0 0xffd>;
0386
0387 v2m@0 {
0388 compatible = "arm,gic-v2m-frame";
0389 msi-controller;
0390 reg = <0x0 0x0 0x0 0xffd>;
0391 };
0392 };
0393
0394 pcie_phy: phy@84000 {
0395 compatible = "qcom,ipq6018-qmp-pcie-phy";
0396 reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
0397 status = "disabled";
0398 #address-cells = <2>;
0399 #size-cells = <2>;
0400 ranges;
0401
0402 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
0403 <&gcc GCC_PCIE0_AHB_CLK>;
0404 clock-names = "aux", "cfg_ahb";
0405
0406 resets = <&gcc GCC_PCIE0_PHY_BCR>,
0407 <&gcc GCC_PCIE0PHY_PHY_BCR>;
0408 reset-names = "phy",
0409 "common";
0410
0411 pcie_phy0: phy@84200 {
0412 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
0413 <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
0414 <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
0415 #phy-cells = <0>;
0416
0417 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
0418 clock-names = "pipe0";
0419 clock-output-names = "gcc_pcie0_pipe_clk_src";
0420 #clock-cells = <0>;
0421 };
0422 };
0423
0424 pcie0: pci@20000000 {
0425 compatible = "qcom,pcie-ipq6018";
0426 reg = <0x0 0x20000000 0x0 0xf1d>,
0427 <0x0 0x20000f20 0x0 0xa8>,
0428 <0x0 0x20001000 0x0 0x1000>,
0429 <0x0 0x80000 0x0 0x4000>,
0430 <0x0 0x20100000 0x0 0x1000>;
0431 reg-names = "dbi", "elbi", "atu", "parf", "config";
0432
0433 device_type = "pci";
0434 linux,pci-domain = <0>;
0435 bus-range = <0x00 0xff>;
0436 num-lanes = <1>;
0437 max-link-speed = <3>;
0438 #address-cells = <3>;
0439 #size-cells = <2>;
0440
0441 phys = <&pcie_phy0>;
0442 phy-names = "pciephy";
0443
0444 ranges = <0x81000000 0 0x20200000 0 0x20200000
0445 0 0x10000>, /* downstream I/O */
0446 <0x82000000 0 0x20220000 0 0x20220000
0447 0 0xfde0000>; /* non-prefetchable memory */
0448
0449 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0450 interrupt-names = "msi";
0451
0452 #interrupt-cells = <1>;
0453 interrupt-map-mask = <0 0 0 0x7>;
0454 interrupt-map = <0 0 0 1 &intc 0 75
0455 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
0456 <0 0 0 2 &intc 0 78
0457 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
0458 <0 0 0 3 &intc 0 79
0459 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
0460 <0 0 0 4 &intc 0 83
0461 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
0462
0463 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
0464 <&gcc GCC_PCIE0_AXI_M_CLK>,
0465 <&gcc GCC_PCIE0_AXI_S_CLK>,
0466 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
0467 <&gcc PCIE0_RCHNG_CLK>;
0468 clock-names = "iface",
0469 "axi_m",
0470 "axi_s",
0471 "axi_bridge",
0472 "rchng";
0473
0474 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
0475 <&gcc GCC_PCIE0_SLEEP_ARES>,
0476 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
0477 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
0478 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
0479 <&gcc GCC_PCIE0_AHB_ARES>,
0480 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
0481 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
0482 reset-names = "pipe",
0483 "sleep",
0484 "sticky",
0485 "axi_m",
0486 "axi_s",
0487 "ahb",
0488 "axi_m_sticky",
0489 "axi_s_sticky";
0490
0491 status = "disabled";
0492 };
0493
0494 watchdog@b017000 {
0495 compatible = "qcom,kpss-wdt";
0496 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
0497 reg = <0x0 0x0b017000 0x0 0x40>;
0498 clocks = <&sleep_clk>;
0499 timeout-sec = <10>;
0500 };
0501
0502 apcs_glb: mailbox@b111000 {
0503 compatible = "qcom,ipq6018-apcs-apps-global";
0504 reg = <0x0 0x0b111000 0x0 0x1000>;
0505 #clock-cells = <1>;
0506 clocks = <&a53pll>, <&xo>;
0507 clock-names = "pll", "xo";
0508 #mbox-cells = <1>;
0509 };
0510
0511 a53pll: clock@b116000 {
0512 compatible = "qcom,ipq6018-a53pll";
0513 reg = <0x0 0x0b116000 0x0 0x40>;
0514 #clock-cells = <0>;
0515 clocks = <&xo>;
0516 clock-names = "xo";
0517 };
0518
0519 timer {
0520 compatible = "arm,armv8-timer";
0521 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0522 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0523 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0524 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0525 };
0526
0527 timer@b120000 {
0528 #address-cells = <1>;
0529 #size-cells = <1>;
0530 ranges = <0 0 0 0x10000000>;
0531 compatible = "arm,armv7-timer-mem";
0532 reg = <0x0 0x0b120000 0x0 0x1000>;
0533
0534 frame@b120000 {
0535 frame-number = <0>;
0536 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0537 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0538 reg = <0x0b121000 0x1000>,
0539 <0x0b122000 0x1000>;
0540 };
0541
0542 frame@b123000 {
0543 frame-number = <1>;
0544 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0545 reg = <0x0b123000 0x1000>;
0546 status = "disabled";
0547 };
0548
0549 frame@b124000 {
0550 frame-number = <2>;
0551 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0552 reg = <0x0b124000 0x1000>;
0553 status = "disabled";
0554 };
0555
0556 frame@b125000 {
0557 frame-number = <3>;
0558 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0559 reg = <0x0b125000 0x1000>;
0560 status = "disabled";
0561 };
0562
0563 frame@b126000 {
0564 frame-number = <4>;
0565 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0566 reg = <0x0b126000 0x1000>;
0567 status = "disabled";
0568 };
0569
0570 frame@b127000 {
0571 frame-number = <5>;
0572 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0573 reg = <0x0b127000 0x1000>;
0574 status = "disabled";
0575 };
0576
0577 frame@b128000 {
0578 frame-number = <6>;
0579 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0580 reg = <0x0b128000 0x1000>;
0581 status = "disabled";
0582 };
0583 };
0584
0585 q6v5_wcss: remoteproc@cd00000 {
0586 compatible = "qcom,ipq6018-wcss-pil";
0587 reg = <0x0 0x0cd00000 0x0 0x4040>,
0588 <0x0 0x004ab000 0x0 0x20>;
0589 reg-names = "qdsp6",
0590 "rmb";
0591 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
0592 <&wcss_smp2p_in 0 0>,
0593 <&wcss_smp2p_in 1 0>,
0594 <&wcss_smp2p_in 2 0>,
0595 <&wcss_smp2p_in 3 0>;
0596 interrupt-names = "wdog",
0597 "fatal",
0598 "ready",
0599 "handover",
0600 "stop-ack";
0601
0602 resets = <&gcc GCC_WCSSAON_RESET>,
0603 <&gcc GCC_WCSS_BCR>,
0604 <&gcc GCC_WCSS_Q6_BCR>;
0605
0606 reset-names = "wcss_aon_reset",
0607 "wcss_reset",
0608 "wcss_q6_reset";
0609
0610 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0611 clock-names = "prng";
0612
0613 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
0614
0615 qcom,smem-states = <&wcss_smp2p_out 0>,
0616 <&wcss_smp2p_out 1>;
0617 qcom,smem-state-names = "shutdown",
0618 "stop";
0619
0620 memory-region = <&q6_region>;
0621
0622 glink-edge {
0623 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
0624 label = "rtr";
0625 qcom,remote-pid = <1>;
0626 mboxes = <&apcs_glb 8>;
0627
0628 qrtr_requests {
0629 qcom,glink-channels = "IPCRTR";
0630 };
0631 };
0632 };
0633
0634 mdio: mdio@90000 {
0635 #address-cells = <1>;
0636 #size-cells = <0>;
0637 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
0638 reg = <0x0 0x90000 0x0 0x64>;
0639 clocks = <&gcc GCC_MDIO_AHB_CLK>;
0640 clock-names = "gcc_mdio_ahb_clk";
0641 status = "disabled";
0642 };
0643
0644 qusb_phy_1: qusb@59000 {
0645 compatible = "qcom,ipq6018-qusb2-phy";
0646 reg = <0x0 0x059000 0x0 0x180>;
0647 #phy-cells = <0>;
0648
0649 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
0650 <&xo>;
0651 clock-names = "cfg_ahb", "ref";
0652
0653 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
0654 status = "disabled";
0655 };
0656
0657 usb2: usb@70f8800 {
0658 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
0659 reg = <0x0 0x070F8800 0x0 0x400>;
0660 #address-cells = <2>;
0661 #size-cells = <2>;
0662 ranges;
0663 clocks = <&gcc GCC_USB1_MASTER_CLK>,
0664 <&gcc GCC_USB1_SLEEP_CLK>,
0665 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
0666 clock-names = "core",
0667 "sleep",
0668 "mock_utmi";
0669
0670 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
0671 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
0672 assigned-clock-rates = <133330000>,
0673 <24000000>;
0674 resets = <&gcc GCC_USB1_BCR>;
0675 status = "disabled";
0676
0677 dwc_1: usb@7000000 {
0678 compatible = "snps,dwc3";
0679 reg = <0x0 0x7000000 0x0 0xcd00>;
0680 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0681 phys = <&qusb_phy_1>;
0682 phy-names = "usb2-phy";
0683 tx-fifo-resize;
0684 snps,is-utmi-l1-suspend;
0685 snps,hird-threshold = /bits/ 8 <0x0>;
0686 snps,dis_u2_susphy_quirk;
0687 snps,dis_u3_susphy_quirk;
0688 dr_mode = "host";
0689 };
0690 };
0691
0692 ssphy_0: ssphy@78000 {
0693 compatible = "qcom,ipq6018-qmp-usb3-phy";
0694 reg = <0x0 0x78000 0x0 0x1C4>;
0695 #address-cells = <2>;
0696 #size-cells = <2>;
0697 ranges;
0698
0699 clocks = <&gcc GCC_USB0_AUX_CLK>,
0700 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
0701 clock-names = "aux", "cfg_ahb", "ref";
0702
0703 resets = <&gcc GCC_USB0_PHY_BCR>,
0704 <&gcc GCC_USB3PHY_0_PHY_BCR>;
0705 reset-names = "phy","common";
0706 status = "disabled";
0707
0708 usb0_ssphy: phy@78200 {
0709 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
0710 <0x0 0x00078400 0x0 0x200>, /* Rx */
0711 <0x0 0x00078800 0x0 0x1F8>, /* PCS */
0712 <0x0 0x00078600 0x0 0x044>; /* PCS misc */
0713 #phy-cells = <0>;
0714 #clock-cells = <0>;
0715 clocks = <&gcc GCC_USB0_PIPE_CLK>;
0716 clock-names = "pipe0";
0717 clock-output-names = "gcc_usb0_pipe_clk_src";
0718 };
0719 };
0720
0721 qusb_phy_0: qusb@79000 {
0722 compatible = "qcom,ipq6018-qusb2-phy";
0723 reg = <0x0 0x079000 0x0 0x180>;
0724 #phy-cells = <0>;
0725
0726 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
0727 <&xo>;
0728 clock-names = "cfg_ahb", "ref";
0729
0730 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
0731 status = "disabled";
0732 };
0733
0734 usb3: usb@8af8800 {
0735 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
0736 reg = <0x0 0x8AF8800 0x0 0x400>;
0737 #address-cells = <2>;
0738 #size-cells = <2>;
0739 ranges;
0740
0741 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
0742 <&gcc GCC_USB0_MASTER_CLK>,
0743 <&gcc GCC_USB0_SLEEP_CLK>,
0744 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
0745 clock-names = "cfg_noc",
0746 "core",
0747 "sleep",
0748 "mock_utmi";
0749
0750 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
0751 <&gcc GCC_USB0_MASTER_CLK>,
0752 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
0753 assigned-clock-rates = <133330000>,
0754 <133330000>,
0755 <20000000>;
0756
0757 resets = <&gcc GCC_USB0_BCR>;
0758 status = "disabled";
0759
0760 dwc_0: usb@8a00000 {
0761 compatible = "snps,dwc3";
0762 reg = <0x0 0x8A00000 0x0 0xcd00>;
0763 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0764 phys = <&qusb_phy_0>, <&usb0_ssphy>;
0765 phy-names = "usb2-phy", "usb3-phy";
0766 clocks = <&xo>;
0767 clock-names = "ref";
0768 tx-fifo-resize;
0769 snps,is-utmi-l1-suspend;
0770 snps,hird-threshold = /bits/ 8 <0x0>;
0771 snps,dis_u2_susphy_quirk;
0772 snps,dis_u3_susphy_quirk;
0773 dr_mode = "host";
0774 };
0775 };
0776 };
0777
0778 wcss: wcss-smp2p {
0779 compatible = "qcom,smp2p";
0780 qcom,smem = <435>, <428>;
0781
0782 interrupt-parent = <&intc>;
0783 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
0784
0785 mboxes = <&apcs_glb 9>;
0786
0787 qcom,local-pid = <0>;
0788 qcom,remote-pid = <1>;
0789
0790 wcss_smp2p_out: master-kernel {
0791 qcom,entry-name = "master-kernel";
0792 #qcom,smem-state-cells = <1>;
0793 };
0794
0795 wcss_smp2p_in: slave-kernel {
0796 qcom,entry-name = "slave-kernel";
0797 interrupt-controller;
0798 #interrupt-cells = <2>;
0799 };
0800 };
0801
0802 rpm-glink {
0803 compatible = "qcom,glink-rpm";
0804 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0805 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0806 mboxes = <&apcs_glb 0>;
0807
0808 rpm_requests: glink-channel {
0809 compatible = "qcom,rpm-ipq6018";
0810 qcom,glink-channels = "rpm_requests";
0811
0812 regulators {
0813 compatible = "qcom,rpm-mp5496-regulators";
0814
0815 ipq6018_s2: s2 {
0816 regulator-min-microvolt = <725000>;
0817 regulator-max-microvolt = <1062500>;
0818 regulator-always-on;
0819 };
0820 };
0821 };
0822 };
0823 };
