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0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/input/gpio-keys.h>
0005 #include <dt-bindings/input/linux-event-codes.h>
0006 #include <dt-bindings/mfd/max77620.h>
0007
0008 #include "tegra210.dtsi"
0009
0010 / {
0011 model = "NVIDIA Jetson Nano Developer Kit";
0012 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
0013
0014 aliases {
0015 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
0016 rtc0 = "/i2c@7000d000/pmic@3c";
0017 rtc1 = "/rtc@7000e000";
0018 serial0 = &uarta;
0019 };
0020
0021 chosen {
0022 stdout-path = "serial0:115200n8";
0023 };
0024
0025 memory@80000000 {
0026 device_type = "memory";
0027 reg = <0x0 0x80000000 0x1 0x0>;
0028 };
0029
0030 pcie@1003000 {
0031 status = "okay";
0032
0033 hvddio-pex-supply = <&vdd_1v8>;
0034 dvddio-pex-supply = <&vdd_pex_1v05>;
0035 vddio-pex-ctl-supply = <&vdd_1v8>;
0036
0037 pci@1,0 {
0038 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
0039 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
0040 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
0041 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
0042 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
0043 nvidia,num-lanes = <4>;
0044 status = "okay";
0045 };
0046
0047 pci@2,0 {
0048 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
0049 phy-names = "pcie-0";
0050 status = "okay";
0051
0052 ethernet@0,0 {
0053 reg = <0x000000 0 0 0 0>;
0054 local-mac-address = [ 00 00 00 00 00 00 ];
0055 };
0056 };
0057 };
0058
0059 host1x@50000000 {
0060 dpaux@54040000 {
0061 status = "okay";
0062 };
0063
0064 vi@54080000 {
0065 status = "okay";
0066
0067 avdd-dsi-csi-supply = <&vdd_sys_1v2>;
0068
0069 csi@838 {
0070 status = "okay";
0071 };
0072 };
0073
0074 sor@54540000 {
0075 status = "okay";
0076
0077 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
0078 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
0079
0080 nvidia,xbar-cfg = <2 1 0 3 4>;
0081 nvidia,dpaux = <&dpaux>;
0082 };
0083
0084 sor@54580000 {
0085 status = "okay";
0086
0087 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
0088 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
0089 hdmi-supply = <&vdd_hdmi>;
0090
0091 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0092 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
0093 GPIO_ACTIVE_LOW>;
0094 nvidia,xbar-cfg = <0 1 2 3 4>;
0095 };
0096
0097 dpaux@545c0000 {
0098 status = "okay";
0099 };
0100
0101 i2c@546c0000 {
0102 status = "okay";
0103 };
0104 };
0105
0106 gpu@57000000 {
0107 vdd-supply = <&vdd_gpu>;
0108 status = "okay";
0109 };
0110
0111 pinmux@700008d4 {
0112 dvfs_pwm_active_state: dvfs_pwm_active {
0113 dvfs_pwm_pbb1 {
0114 nvidia,pins = "dvfs_pwm_pbb1";
0115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0116 };
0117 };
0118
0119 dvfs_pwm_inactive_state: dvfs_pwm_inactive {
0120 dvfs_pwm_pbb1 {
0121 nvidia,pins = "dvfs_pwm_pbb1";
0122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0123 };
0124 };
0125 };
0126
0127 /* debug port */
0128 serial@70006000 {
0129 status = "okay";
0130 };
0131
0132 pwm@7000a000 {
0133 status = "okay";
0134 };
0135
0136 i2c@7000c500 {
0137 status = "okay";
0138 clock-frequency = <100000>;
0139
0140 eeprom@50 {
0141 compatible = "atmel,24c02";
0142 reg = <0x50>;
0143
0144 label = "module";
0145 vcc-supply = <&vdd_1v8>;
0146 address-width = <8>;
0147 pagesize = <8>;
0148 size = <256>;
0149 read-only;
0150 };
0151
0152 eeprom@57 {
0153 compatible = "atmel,24c02";
0154 reg = <0x57>;
0155
0156 label = "system";
0157 vcc-supply = <&vdd_1v8>;
0158 address-width = <8>;
0159 pagesize = <8>;
0160 size = <256>;
0161 read-only;
0162 };
0163 };
0164
0165 hdmi_ddc: i2c@7000c700 {
0166 status = "okay";
0167 clock-frequency = <100000>;
0168 };
0169
0170 i2c@7000d000 {
0171 status = "okay";
0172 clock-frequency = <400000>;
0173
0174 pmic: pmic@3c {
0175 compatible = "maxim,max77620";
0176 reg = <0x3c>;
0177 interrupt-parent = <&tegra_pmc>;
0178 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
0179
0180 #interrupt-cells = <2>;
0181 interrupt-controller;
0182
0183 #gpio-cells = <2>;
0184 gpio-controller;
0185
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&max77620_default>;
0188
0189 max77620_default: pinmux {
0190 gpio0 {
0191 pins = "gpio0";
0192 function = "gpio";
0193 };
0194
0195 gpio1 {
0196 pins = "gpio1";
0197 function = "fps-out";
0198 drive-push-pull = <1>;
0199 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
0200 maxim,active-fps-power-up-slot = <0>;
0201 maxim,active-fps-power-down-slot = <7>;
0202 };
0203
0204 gpio2 {
0205 pins = "gpio2";
0206 function = "fps-out";
0207 drive-open-drain = <1>;
0208 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
0209 maxim,active-fps-power-up-slot = <0>;
0210 maxim,active-fps-power-down-slot = <7>;
0211 };
0212
0213 gpio3 {
0214 pins = "gpio3";
0215 function = "fps-out";
0216 drive-open-drain = <1>;
0217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
0218 maxim,active-fps-power-up-slot = <4>;
0219 maxim,active-fps-power-down-slot = <3>;
0220 };
0221
0222 gpio4 {
0223 pins = "gpio4";
0224 function = "32k-out1";
0225 };
0226
0227 gpio5_6_7 {
0228 pins = "gpio5", "gpio6", "gpio7";
0229 function = "gpio";
0230 drive-push-pull = <1>;
0231 };
0232 };
0233
0234 fps {
0235 fps0 {
0236 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
0237 maxim,suspend-fps-time-period-us = <5120>;
0238 };
0239
0240 fps1 {
0241 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
0242 maxim,suspend-fps-time-period-us = <5120>;
0243 };
0244
0245 fps2 {
0246 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
0247 };
0248 };
0249
0250 regulators {
0251 in-ldo0-1-supply = <&vdd_pre>;
0252 in-ldo2-supply = <&vdd_3v3_sys>;
0253 in-ldo3-5-supply = <&vdd_1v8>;
0254 in-ldo4-6-supply = <&vdd_5v0_sys>;
0255 in-ldo7-8-supply = <&vdd_pre>;
0256 in-sd0-supply = <&vdd_5v0_sys>;
0257 in-sd1-supply = <&vdd_5v0_sys>;
0258 in-sd2-supply = <&vdd_5v0_sys>;
0259 in-sd3-supply = <&vdd_5v0_sys>;
0260
0261 vdd_soc: sd0 {
0262 regulator-name = "VDD_SOC";
0263 regulator-min-microvolt = <1000000>;
0264 regulator-max-microvolt = <1170000>;
0265 regulator-enable-ramp-delay = <146>;
0266 regulator-ramp-delay = <27500>;
0267 regulator-ramp-delay-scale = <300>;
0268 regulator-always-on;
0269 regulator-boot-on;
0270
0271 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
0272 maxim,active-fps-power-up-slot = <1>;
0273 maxim,active-fps-power-down-slot = <6>;
0274 };
0275
0276 vdd_ddr: sd1 {
0277 regulator-name = "VDD_DDR_1V1_PMIC";
0278 regulator-min-microvolt = <1150000>;
0279 regulator-max-microvolt = <1150000>;
0280 regulator-enable-ramp-delay = <176>;
0281 regulator-ramp-delay = <27500>;
0282 regulator-ramp-delay-scale = <300>;
0283 regulator-always-on;
0284 regulator-boot-on;
0285
0286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
0287 maxim,active-fps-power-up-slot = <5>;
0288 maxim,active-fps-power-down-slot = <2>;
0289 };
0290
0291 vdd_pre: sd2 {
0292 regulator-name = "VDD_PRE_REG_1V35";
0293 regulator-min-microvolt = <1350000>;
0294 regulator-max-microvolt = <1350000>;
0295 regulator-enable-ramp-delay = <176>;
0296 regulator-ramp-delay = <27500>;
0297 regulator-ramp-delay-scale = <350>;
0298 regulator-always-on;
0299 regulator-boot-on;
0300
0301 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
0302 maxim,active-fps-power-up-slot = <2>;
0303 maxim,active-fps-power-down-slot = <5>;
0304 };
0305
0306 vdd_1v8: sd3 {
0307 regulator-name = "VDD_1V8";
0308 regulator-min-microvolt = <1800000>;
0309 regulator-max-microvolt = <1800000>;
0310 regulator-enable-ramp-delay = <242>;
0311 regulator-ramp-delay = <27500>;
0312 regulator-ramp-delay-scale = <360>;
0313 regulator-always-on;
0314 regulator-boot-on;
0315
0316 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
0317 maxim,active-fps-power-up-slot = <3>;
0318 maxim,active-fps-power-down-slot = <4>;
0319 };
0320
0321 vdd_sys_1v2: ldo0 {
0322 regulator-name = "AVDD_SYS_1V2";
0323 regulator-min-microvolt = <1200000>;
0324 regulator-max-microvolt = <1200000>;
0325 regulator-enable-ramp-delay = <26>;
0326 regulator-ramp-delay = <100000>;
0327 regulator-ramp-delay-scale = <200>;
0328 regulator-always-on;
0329 regulator-boot-on;
0330
0331 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
0332 maxim,active-fps-power-up-slot = <0>;
0333 maxim,active-fps-power-down-slot = <7>;
0334 };
0335
0336 vdd_pex_1v05: ldo1 {
0337 regulator-name = "VDD_PEX_1V05";
0338 regulator-min-microvolt = <1050000>;
0339 regulator-max-microvolt = <1050000>;
0340 regulator-enable-ramp-delay = <22>;
0341 regulator-ramp-delay = <100000>;
0342 regulator-ramp-delay-scale = <200>;
0343
0344 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
0345 maxim,active-fps-power-up-slot = <0>;
0346 maxim,active-fps-power-down-slot = <7>;
0347 };
0348
0349 vddio_sdmmc: ldo2 {
0350 regulator-name = "VDDIO_SDMMC";
0351 regulator-min-microvolt = <1800000>;
0352 regulator-max-microvolt = <3300000>;
0353 regulator-enable-ramp-delay = <62>;
0354 regulator-ramp-delay = <100000>;
0355 regulator-ramp-delay-scale = <200>;
0356
0357 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
0358 maxim,active-fps-power-up-slot = <0>;
0359 maxim,active-fps-power-down-slot = <7>;
0360 };
0361
0362 ldo3 {
0363 status = "disabled";
0364 };
0365
0366 vdd_rtc: ldo4 {
0367 regulator-name = "VDD_RTC";
0368 regulator-min-microvolt = <850000>;
0369 regulator-max-microvolt = <1100000>;
0370 regulator-enable-ramp-delay = <22>;
0371 regulator-ramp-delay = <100000>;
0372 regulator-ramp-delay-scale = <200>;
0373 regulator-disable-active-discharge;
0374 regulator-always-on;
0375 regulator-boot-on;
0376
0377 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
0378 maxim,active-fps-power-up-slot = <1>;
0379 maxim,active-fps-power-down-slot = <6>;
0380 };
0381
0382 ldo5 {
0383 status = "disabled";
0384 };
0385
0386 ldo6 {
0387 status = "disabled";
0388 };
0389
0390 avdd_1v05_pll: ldo7 {
0391 regulator-name = "AVDD_1V05_PLL";
0392 regulator-min-microvolt = <1050000>;
0393 regulator-max-microvolt = <1050000>;
0394 regulator-enable-ramp-delay = <24>;
0395 regulator-ramp-delay = <100000>;
0396 regulator-ramp-delay-scale = <200>;
0397
0398 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
0399 maxim,active-fps-power-up-slot = <3>;
0400 maxim,active-fps-power-down-slot = <4>;
0401 };
0402
0403 avdd_1v05: ldo8 {
0404 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
0405 regulator-min-microvolt = <1050000>;
0406 regulator-max-microvolt = <1050000>;
0407 regulator-enable-ramp-delay = <22>;
0408 regulator-ramp-delay = <100000>;
0409 regulator-ramp-delay-scale = <200>;
0410
0411 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
0412 maxim,active-fps-power-up-slot = <6>;
0413 maxim,active-fps-power-down-slot = <1>;
0414 };
0415 };
0416 };
0417 };
0418
0419 pmc@7000e400 {
0420 nvidia,invert-interrupt;
0421 nvidia,suspend-mode = <0>;
0422 nvidia,cpu-pwr-good-time = <0>;
0423 nvidia,cpu-pwr-off-time = <0>;
0424 nvidia,core-pwr-good-time = <4587 3876>;
0425 nvidia,core-pwr-off-time = <39065>;
0426 nvidia,core-power-req-active-high;
0427 nvidia,sys-clock-req-active-high;
0428 };
0429
0430 hda@70030000 {
0431 nvidia,model = "NVIDIA Jetson Nano HDA";
0432
0433 status = "okay";
0434 };
0435
0436 usb@70090000 {
0437 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
0438 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
0439 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
0440 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
0441 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
0442
0443 avdd-usb-supply = <&vdd_3v3_sys>;
0444 dvddio-pex-supply = <&vdd_pex_1v05>;
0445 hvddio-pex-supply = <&vdd_1v8>;
0446
0447 status = "okay";
0448 };
0449
0450 padctl@7009f000 {
0451 status = "okay";
0452
0453 avdd-pll-utmip-supply = <&vdd_1v8>;
0454 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
0455 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
0456 hvdd-pex-pll-e-supply = <&vdd_1v8>;
0457
0458 pads {
0459 usb2 {
0460 status = "okay";
0461
0462 lanes {
0463 micro_b: usb2-0 {
0464 nvidia,function = "xusb";
0465 status = "okay";
0466 };
0467
0468 usb2-1 {
0469 nvidia,function = "xusb";
0470 status = "okay";
0471 };
0472
0473 usb2-2 {
0474 nvidia,function = "xusb";
0475 status = "okay";
0476 };
0477 };
0478 };
0479
0480 pcie {
0481 status = "okay";
0482
0483 lanes {
0484 pcie-0 {
0485 nvidia,function = "pcie-x1";
0486 status = "okay";
0487 };
0488
0489 pcie-1 {
0490 nvidia,function = "pcie-x4";
0491 status = "okay";
0492 };
0493
0494 pcie-2 {
0495 nvidia,function = "pcie-x4";
0496 status = "okay";
0497 };
0498
0499 pcie-3 {
0500 nvidia,function = "pcie-x4";
0501 status = "okay";
0502 };
0503
0504 pcie-4 {
0505 nvidia,function = "pcie-x4";
0506 status = "okay";
0507 };
0508
0509 pcie-5 {
0510 nvidia,function = "usb3-ss";
0511 status = "okay";
0512 };
0513
0514 pcie-6 {
0515 nvidia,function = "usb3-ss";
0516 status = "okay";
0517 };
0518 };
0519 };
0520 };
0521
0522 ports {
0523 usb2-0 {
0524 status = "okay";
0525 mode = "peripheral";
0526 usb-role-switch;
0527
0528 vbus-supply = <&vdd_5v0_usb>;
0529
0530 connector {
0531 compatible = "gpio-usb-b-connector",
0532 "usb-b-connector";
0533 label = "micro-USB";
0534 type = "micro";
0535 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
0536 GPIO_ACTIVE_LOW>;
0537 };
0538 };
0539
0540 usb2-1 {
0541 status = "okay";
0542 mode = "host";
0543 };
0544
0545 usb2-2 {
0546 status = "okay";
0547 mode = "host";
0548 };
0549
0550 usb3-0 {
0551 status = "okay";
0552 nvidia,usb2-companion = <1>;
0553 vbus-supply = <&vdd_hub_3v3>;
0554 };
0555 };
0556 };
0557
0558 mmc@700b0000 {
0559 status = "okay";
0560 bus-width = <4>;
0561
0562 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
0563 disable-wp;
0564
0565 vqmmc-supply = <&vddio_sdmmc>;
0566 vmmc-supply = <&vdd_3v3_sd>;
0567 };
0568
0569 mmc@700b0400 {
0570 status = "okay";
0571 bus-width = <4>;
0572
0573 vqmmc-supply = <&vdd_1v8>;
0574 vmmc-supply = <&vdd_3v3_sys>;
0575
0576 non-removable;
0577 cap-sdio-irq;
0578 keep-power-in-suspend;
0579 wakeup-source;
0580 };
0581
0582 usb@700d0000 {
0583 status = "okay";
0584 phys = <µ_b>;
0585 phy-names = "usb2-0";
0586 avddio-usb-supply = <&vdd_3v3_sys>;
0587 hvdd-usb-supply = <&vdd_1v8>;
0588 };
0589
0590 clock@70110000 {
0591 status = "okay";
0592
0593 nvidia,cf = <6>;
0594 nvidia,ci = <0>;
0595 nvidia,cg = <2>;
0596 nvidia,droop-ctrl = <0x00000f00>;
0597 nvidia,force-mode = <1>;
0598 nvidia,sample-rate = <25000>;
0599
0600 nvidia,pwm-min-microvolts = <708000>;
0601 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
0602 nvidia,pwm-to-pmic;
0603 nvidia,pwm-tristate-microvolts = <1000000>;
0604 nvidia,pwm-voltage-step-microvolts = <19200>;
0605
0606 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
0607 pinctrl-0 = <&dvfs_pwm_active_state>;
0608 pinctrl-1 = <&dvfs_pwm_inactive_state>;
0609 };
0610
0611 aconnect@702c0000 {
0612 status = "okay";
0613
0614 dma-controller@702e2000 {
0615 status = "okay";
0616 };
0617
0618 interrupt-controller@702f9000 {
0619 status = "okay";
0620 };
0621
0622 ahub@702d0800 {
0623 status = "okay";
0624
0625 admaif@702d0000 {
0626 status = "okay";
0627 };
0628
0629 i2s@702d1200 {
0630 status = "okay";
0631
0632 ports {
0633 #address-cells = <1>;
0634 #size-cells = <0>;
0635
0636 port@0 {
0637 reg = <0>;
0638
0639 i2s3_cif_ep: endpoint {
0640 remote-endpoint = <&xbar_i2s3_ep>;
0641 };
0642 };
0643
0644 i2s3_port: port@1 {
0645 reg = <1>;
0646
0647 i2s3_dap_ep: endpoint {
0648 dai-format = "i2s";
0649 /* Placeholder for external Codec */
0650 };
0651 };
0652 };
0653 };
0654
0655 i2s@702d1300 {
0656 status = "okay";
0657
0658 ports {
0659 #address-cells = <1>;
0660 #size-cells = <0>;
0661
0662 port@0 {
0663 reg = <0>;
0664
0665 i2s4_cif_ep: endpoint {
0666 remote-endpoint = <&xbar_i2s4_ep>;
0667 };
0668 };
0669
0670 i2s4_port: port@1 {
0671 reg = <1>;
0672
0673 i2s4_dap_ep: endpoint {
0674 dai-format = "i2s";
0675 /* Placeholder for external Codec */
0676 };
0677 };
0678 };
0679 };
0680
0681 dmic@702d4000 {
0682 status = "okay";
0683
0684 ports {
0685 #address-cells = <1>;
0686 #size-cells = <0>;
0687
0688 port@0 {
0689 reg = <0>;
0690
0691 dmic1_cif_ep: endpoint {
0692 remote-endpoint = <&xbar_dmic1_ep>;
0693 };
0694 };
0695
0696 dmic1_port: port@1 {
0697 reg = <1>;
0698
0699 dmic1_dap_ep: endpoint {
0700 /* Placeholder for external Codec */
0701 };
0702 };
0703 };
0704 };
0705
0706 dmic@702d4100 {
0707 status = "okay";
0708
0709 ports {
0710 #address-cells = <1>;
0711 #size-cells = <0>;
0712
0713 port@0 {
0714 reg = <0>;
0715
0716 dmic2_cif_ep: endpoint {
0717 remote-endpoint = <&xbar_dmic2_ep>;
0718 };
0719 };
0720
0721 dmic2_port: port@1 {
0722 reg = <1>;
0723
0724 dmic2_dap_ep: endpoint {
0725 /* Placeholder for external Codec */
0726 };
0727 };
0728 };
0729 };
0730
0731 sfc@702d2000 {
0732 status = "okay";
0733
0734 ports {
0735 #address-cells = <1>;
0736 #size-cells = <0>;
0737
0738 port@0 {
0739 reg = <0>;
0740
0741 sfc1_cif_in_ep: endpoint {
0742 remote-endpoint = <&xbar_sfc1_in_ep>;
0743 };
0744 };
0745
0746 sfc1_out_port: port@1 {
0747 reg = <1>;
0748
0749 sfc1_cif_out_ep: endpoint {
0750 remote-endpoint = <&xbar_sfc1_out_ep>;
0751 };
0752 };
0753 };
0754 };
0755
0756 sfc@702d2200 {
0757 status = "okay";
0758
0759 ports {
0760 #address-cells = <1>;
0761 #size-cells = <0>;
0762
0763 port@0 {
0764 reg = <0>;
0765
0766 sfc2_cif_in_ep: endpoint {
0767 remote-endpoint = <&xbar_sfc2_in_ep>;
0768 };
0769 };
0770
0771 sfc2_out_port: port@1 {
0772 reg = <1>;
0773
0774 sfc2_cif_out_ep: endpoint {
0775 remote-endpoint = <&xbar_sfc2_out_ep>;
0776 };
0777 };
0778 };
0779 };
0780
0781 sfc@702d2400 {
0782 status = "okay";
0783
0784 ports {
0785 #address-cells = <1>;
0786 #size-cells = <0>;
0787
0788 port@0 {
0789 reg = <0>;
0790
0791 sfc3_cif_in_ep: endpoint {
0792 remote-endpoint = <&xbar_sfc3_in_ep>;
0793 };
0794 };
0795
0796 sfc3_out_port: port@1 {
0797 reg = <1>;
0798
0799 sfc3_cif_out_ep: endpoint {
0800 remote-endpoint = <&xbar_sfc3_out_ep>;
0801 };
0802 };
0803 };
0804 };
0805
0806 sfc@702d2600 {
0807 status = "okay";
0808
0809 ports {
0810 #address-cells = <1>;
0811 #size-cells = <0>;
0812
0813 port@0 {
0814 reg = <0>;
0815
0816 sfc4_cif_in_ep: endpoint {
0817 remote-endpoint = <&xbar_sfc4_in_ep>;
0818 };
0819 };
0820
0821 sfc4_out_port: port@1 {
0822 reg = <1>;
0823
0824 sfc4_cif_out_ep: endpoint {
0825 remote-endpoint = <&xbar_sfc4_out_ep>;
0826 };
0827 };
0828 };
0829 };
0830
0831 mvc@702da000 {
0832 status = "okay";
0833
0834 ports {
0835 #address-cells = <1>;
0836 #size-cells = <0>;
0837
0838 port@0 {
0839 reg = <0>;
0840
0841 mvc1_cif_in_ep: endpoint {
0842 remote-endpoint = <&xbar_mvc1_in_ep>;
0843 };
0844 };
0845
0846 mvc1_out_port: port@1 {
0847 reg = <1>;
0848
0849 mvc1_cif_out_ep: endpoint {
0850 remote-endpoint = <&xbar_mvc1_out_ep>;
0851 };
0852 };
0853 };
0854 };
0855
0856 mvc@702da200 {
0857 status = "okay";
0858
0859 ports {
0860 #address-cells = <1>;
0861 #size-cells = <0>;
0862
0863 port@0 {
0864 reg = <0>;
0865
0866 mvc2_cif_in_ep: endpoint {
0867 remote-endpoint = <&xbar_mvc2_in_ep>;
0868 };
0869 };
0870
0871 mvc2_out_port: port@1 {
0872 reg = <1>;
0873
0874 mvc2_cif_out_ep: endpoint {
0875 remote-endpoint = <&xbar_mvc2_out_ep>;
0876 };
0877 };
0878 };
0879 };
0880
0881 amx@702d3000 {
0882 status = "okay";
0883
0884 ports {
0885 #address-cells = <1>;
0886 #size-cells = <0>;
0887
0888 port@0 {
0889 reg = <0>;
0890
0891 amx1_in1_ep: endpoint {
0892 remote-endpoint = <&xbar_amx1_in1_ep>;
0893 };
0894 };
0895
0896 port@1 {
0897 reg = <1>;
0898
0899 amx1_in2_ep: endpoint {
0900 remote-endpoint = <&xbar_amx1_in2_ep>;
0901 };
0902 };
0903
0904 port@2 {
0905 reg = <2>;
0906
0907 amx1_in3_ep: endpoint {
0908 remote-endpoint = <&xbar_amx1_in3_ep>;
0909 };
0910 };
0911
0912 port@3 {
0913 reg = <3>;
0914
0915 amx1_in4_ep: endpoint {
0916 remote-endpoint = <&xbar_amx1_in4_ep>;
0917 };
0918 };
0919
0920 amx1_out_port: port@4 {
0921 reg = <4>;
0922
0923 amx1_out_ep: endpoint {
0924 remote-endpoint = <&xbar_amx1_out_ep>;
0925 };
0926 };
0927 };
0928 };
0929
0930 amx@702d3100 {
0931 status = "okay";
0932
0933 ports {
0934 #address-cells = <1>;
0935 #size-cells = <0>;
0936
0937 port@0 {
0938 reg = <0>;
0939
0940 amx2_in1_ep: endpoint {
0941 remote-endpoint = <&xbar_amx2_in1_ep>;
0942 };
0943 };
0944
0945 port@1 {
0946 reg = <1>;
0947
0948 amx2_in2_ep: endpoint {
0949 remote-endpoint = <&xbar_amx2_in2_ep>;
0950 };
0951 };
0952
0953 amx2_in3_port: port@2 {
0954 reg = <2>;
0955
0956 amx2_in3_ep: endpoint {
0957 remote-endpoint = <&xbar_amx2_in3_ep>;
0958 };
0959 };
0960
0961 amx2_in4_port: port@3 {
0962 reg = <3>;
0963
0964 amx2_in4_ep: endpoint {
0965 remote-endpoint = <&xbar_amx2_in4_ep>;
0966 };
0967 };
0968
0969 amx2_out_port: port@4 {
0970 reg = <4>;
0971
0972 amx2_out_ep: endpoint {
0973 remote-endpoint = <&xbar_amx2_out_ep>;
0974 };
0975 };
0976 };
0977 };
0978
0979 adx@702d3800 {
0980 status = "okay";
0981
0982 ports {
0983 #address-cells = <1>;
0984 #size-cells = <0>;
0985
0986 port@0 {
0987 reg = <0>;
0988
0989 adx1_in_ep: endpoint {
0990 remote-endpoint = <&xbar_adx1_in_ep>;
0991 };
0992 };
0993
0994 adx1_out1_port: port@1 {
0995 reg = <1>;
0996
0997 adx1_out1_ep: endpoint {
0998 remote-endpoint = <&xbar_adx1_out1_ep>;
0999 };
1000 };
1001
1002 adx1_out2_port: port@2 {
1003 reg = <2>;
1004
1005 adx1_out2_ep: endpoint {
1006 remote-endpoint = <&xbar_adx1_out2_ep>;
1007 };
1008 };
1009
1010 adx1_out3_port: port@3 {
1011 reg = <3>;
1012
1013 adx1_out3_ep: endpoint {
1014 remote-endpoint = <&xbar_adx1_out3_ep>;
1015 };
1016 };
1017
1018 adx1_out4_port: port@4 {
1019 reg = <4>;
1020
1021 adx1_out4_ep: endpoint {
1022 remote-endpoint = <&xbar_adx1_out4_ep>;
1023 };
1024 };
1025 };
1026 };
1027
1028 adx@702d3900 {
1029 status = "okay";
1030
1031 ports {
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034
1035 port@0 {
1036 reg = <0>;
1037
1038 adx2_in_ep: endpoint {
1039 remote-endpoint = <&xbar_adx2_in_ep>;
1040 };
1041 };
1042
1043 adx2_out1_port: port@1 {
1044 reg = <1>;
1045
1046 adx2_out1_ep: endpoint {
1047 remote-endpoint = <&xbar_adx2_out1_ep>;
1048 };
1049 };
1050
1051 adx2_out2_port: port@2 {
1052 reg = <2>;
1053
1054 adx2_out2_ep: endpoint {
1055 remote-endpoint = <&xbar_adx2_out2_ep>;
1056 };
1057 };
1058
1059 adx2_out3_port: port@3 {
1060 reg = <3>;
1061
1062 adx2_out3_ep: endpoint {
1063 remote-endpoint = <&xbar_adx2_out3_ep>;
1064 };
1065 };
1066
1067 adx2_out4_port: port@4 {
1068 reg = <4>;
1069
1070 adx2_out4_ep: endpoint {
1071 remote-endpoint = <&xbar_adx2_out4_ep>;
1072 };
1073 };
1074 };
1075 };
1076
1077 processing-engine@702d8000 {
1078 status = "okay";
1079
1080 ports {
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083
1084 port@0 {
1085 reg = <0x0>;
1086
1087 ope1_cif_in_ep: endpoint {
1088 remote-endpoint = <&xbar_ope1_in_ep>;
1089 };
1090 };
1091
1092 ope1_out_port: port@1 {
1093 reg = <0x1>;
1094
1095 ope1_cif_out_ep: endpoint {
1096 remote-endpoint = <&xbar_ope1_out_ep>;
1097 };
1098 };
1099 };
1100 };
1101
1102 processing-engine@702d8400 {
1103 status = "okay";
1104
1105 ports {
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1108
1109 port@0 {
1110 reg = <0x0>;
1111
1112 ope2_cif_in_ep: endpoint {
1113 remote-endpoint = <&xbar_ope2_in_ep>;
1114 };
1115 };
1116
1117 ope2_out_port: port@1 {
1118 reg = <0x1>;
1119
1120 ope2_cif_out_ep: endpoint {
1121 remote-endpoint = <&xbar_ope2_out_ep>;
1122 };
1123 };
1124 };
1125 };
1126
1127 amixer@702dbb00 {
1128 status = "okay";
1129
1130 ports {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133
1134 port@0 {
1135 reg = <0x0>;
1136
1137 mixer_in1_ep: endpoint {
1138 remote-endpoint = <&xbar_mixer_in1_ep>;
1139 };
1140 };
1141
1142 port@1 {
1143 reg = <0x1>;
1144
1145 mixer_in2_ep: endpoint {
1146 remote-endpoint = <&xbar_mixer_in2_ep>;
1147 };
1148 };
1149
1150 port@2 {
1151 reg = <0x2>;
1152
1153 mixer_in3_ep: endpoint {
1154 remote-endpoint = <&xbar_mixer_in3_ep>;
1155 };
1156 };
1157
1158 port@3 {
1159 reg = <0x3>;
1160
1161 mixer_in4_ep: endpoint {
1162 remote-endpoint = <&xbar_mixer_in4_ep>;
1163 };
1164 };
1165
1166 port@4 {
1167 reg = <0x4>;
1168
1169 mixer_in5_ep: endpoint {
1170 remote-endpoint = <&xbar_mixer_in5_ep>;
1171 };
1172 };
1173
1174 port@5 {
1175 reg = <0x5>;
1176
1177 mixer_in6_ep: endpoint {
1178 remote-endpoint = <&xbar_mixer_in6_ep>;
1179 };
1180 };
1181
1182 port@6 {
1183 reg = <0x6>;
1184
1185 mixer_in7_ep: endpoint {
1186 remote-endpoint = <&xbar_mixer_in7_ep>;
1187 };
1188 };
1189
1190 port@7 {
1191 reg = <0x7>;
1192
1193 mixer_in8_ep: endpoint {
1194 remote-endpoint = <&xbar_mixer_in8_ep>;
1195 };
1196 };
1197
1198 port@8 {
1199 reg = <0x8>;
1200
1201 mixer_in9_ep: endpoint {
1202 remote-endpoint = <&xbar_mixer_in9_ep>;
1203 };
1204 };
1205
1206 port@9 {
1207 reg = <0x9>;
1208
1209 mixer_in10_ep: endpoint {
1210 remote-endpoint = <&xbar_mixer_in10_ep>;
1211 };
1212 };
1213
1214 mixer_out1_port: port@a {
1215 reg = <0xa>;
1216
1217 mixer_out1_ep: endpoint {
1218 remote-endpoint = <&xbar_mixer_out1_ep>;
1219 };
1220 };
1221
1222 mixer_out2_port: port@b {
1223 reg = <0xb>;
1224
1225 mixer_out2_ep: endpoint {
1226 remote-endpoint = <&xbar_mixer_out2_ep>;
1227 };
1228 };
1229
1230 mixer_out3_port: port@c {
1231 reg = <0xc>;
1232
1233 mixer_out3_ep: endpoint {
1234 remote-endpoint = <&xbar_mixer_out3_ep>;
1235 };
1236 };
1237
1238 mixer_out4_port: port@d {
1239 reg = <0xd>;
1240
1241 mixer_out4_ep: endpoint {
1242 remote-endpoint = <&xbar_mixer_out4_ep>;
1243 };
1244 };
1245
1246 mixer_out5_port: port@e {
1247 reg = <0xe>;
1248
1249 mixer_out5_ep: endpoint {
1250 remote-endpoint = <&xbar_mixer_out5_ep>;
1251 };
1252 };
1253 };
1254 };
1255
1256 ports {
1257 xbar_i2s3_port: port@c {
1258 reg = <0xc>;
1259
1260 xbar_i2s3_ep: endpoint {
1261 remote-endpoint = <&i2s3_cif_ep>;
1262 };
1263 };
1264
1265 xbar_i2s4_port: port@d {
1266 reg = <0xd>;
1267
1268 xbar_i2s4_ep: endpoint {
1269 remote-endpoint = <&i2s4_cif_ep>;
1270 };
1271 };
1272
1273 xbar_dmic1_port: port@f {
1274 reg = <0xf>;
1275
1276 xbar_dmic1_ep: endpoint {
1277 remote-endpoint = <&dmic1_cif_ep>;
1278 };
1279 };
1280
1281 xbar_dmic2_port: port@10 {
1282 reg = <0x10>;
1283
1284 xbar_dmic2_ep: endpoint {
1285 remote-endpoint = <&dmic2_cif_ep>;
1286 };
1287 };
1288
1289 xbar_sfc1_in_port: port@12 {
1290 reg = <0x12>;
1291
1292 xbar_sfc1_in_ep: endpoint {
1293 remote-endpoint = <&sfc1_cif_in_ep>;
1294 };
1295 };
1296
1297 port@13 {
1298 reg = <0x13>;
1299
1300 xbar_sfc1_out_ep: endpoint {
1301 remote-endpoint = <&sfc1_cif_out_ep>;
1302 };
1303 };
1304
1305 xbar_sfc2_in_port: port@14 {
1306 reg = <0x14>;
1307
1308 xbar_sfc2_in_ep: endpoint {
1309 remote-endpoint = <&sfc2_cif_in_ep>;
1310 };
1311 };
1312
1313 port@15 {
1314 reg = <0x15>;
1315
1316 xbar_sfc2_out_ep: endpoint {
1317 remote-endpoint = <&sfc2_cif_out_ep>;
1318 };
1319 };
1320
1321 xbar_sfc3_in_port: port@16 {
1322 reg = <0x16>;
1323
1324 xbar_sfc3_in_ep: endpoint {
1325 remote-endpoint = <&sfc3_cif_in_ep>;
1326 };
1327 };
1328
1329 port@17 {
1330 reg = <0x17>;
1331
1332 xbar_sfc3_out_ep: endpoint {
1333 remote-endpoint = <&sfc3_cif_out_ep>;
1334 };
1335 };
1336
1337 xbar_sfc4_in_port: port@18 {
1338 reg = <0x18>;
1339
1340 xbar_sfc4_in_ep: endpoint {
1341 remote-endpoint = <&sfc4_cif_in_ep>;
1342 };
1343 };
1344
1345 port@19 {
1346 reg = <0x19>;
1347
1348 xbar_sfc4_out_ep: endpoint {
1349 remote-endpoint = <&sfc4_cif_out_ep>;
1350 };
1351 };
1352
1353 xbar_mvc1_in_port: port@1a {
1354 reg = <0x1a>;
1355
1356 xbar_mvc1_in_ep: endpoint {
1357 remote-endpoint = <&mvc1_cif_in_ep>;
1358 };
1359 };
1360
1361 port@1b {
1362 reg = <0x1b>;
1363
1364 xbar_mvc1_out_ep: endpoint {
1365 remote-endpoint = <&mvc1_cif_out_ep>;
1366 };
1367 };
1368
1369 xbar_mvc2_in_port: port@1c {
1370 reg = <0x1c>;
1371
1372 xbar_mvc2_in_ep: endpoint {
1373 remote-endpoint = <&mvc2_cif_in_ep>;
1374 };
1375 };
1376
1377 port@1d {
1378 reg = <0x1d>;
1379
1380 xbar_mvc2_out_ep: endpoint {
1381 remote-endpoint = <&mvc2_cif_out_ep>;
1382 };
1383 };
1384
1385 xbar_amx1_in1_port: port@1e {
1386 reg = <0x1e>;
1387
1388 xbar_amx1_in1_ep: endpoint {
1389 remote-endpoint = <&amx1_in1_ep>;
1390 };
1391 };
1392
1393 xbar_amx1_in2_port: port@1f {
1394 reg = <0x1f>;
1395
1396 xbar_amx1_in2_ep: endpoint {
1397 remote-endpoint = <&amx1_in2_ep>;
1398 };
1399 };
1400
1401 xbar_amx1_in3_port: port@20 {
1402 reg = <0x20>;
1403
1404 xbar_amx1_in3_ep: endpoint {
1405 remote-endpoint = <&amx1_in3_ep>;
1406 };
1407 };
1408
1409 xbar_amx1_in4_port: port@21 {
1410 reg = <0x21>;
1411
1412 xbar_amx1_in4_ep: endpoint {
1413 remote-endpoint = <&amx1_in4_ep>;
1414 };
1415 };
1416
1417 port@22 {
1418 reg = <0x22>;
1419
1420 xbar_amx1_out_ep: endpoint {
1421 remote-endpoint = <&amx1_out_ep>;
1422 };
1423 };
1424
1425 xbar_amx2_in1_port: port@23 {
1426 reg = <0x23>;
1427
1428 xbar_amx2_in1_ep: endpoint {
1429 remote-endpoint = <&amx2_in1_ep>;
1430 };
1431 };
1432
1433 xbar_amx2_in2_port: port@24 {
1434 reg = <0x24>;
1435
1436 xbar_amx2_in2_ep: endpoint {
1437 remote-endpoint = <&amx2_in2_ep>;
1438 };
1439 };
1440
1441 xbar_amx2_in3_port: port@25 {
1442 reg = <0x25>;
1443
1444 xbar_amx2_in3_ep: endpoint {
1445 remote-endpoint = <&amx2_in3_ep>;
1446 };
1447 };
1448
1449 xbar_amx2_in4_port: port@26 {
1450 reg = <0x26>;
1451
1452 xbar_amx2_in4_ep: endpoint {
1453 remote-endpoint = <&amx2_in4_ep>;
1454 };
1455 };
1456
1457 port@27 {
1458 reg = <0x27>;
1459
1460 xbar_amx2_out_ep: endpoint {
1461 remote-endpoint = <&amx2_out_ep>;
1462 };
1463 };
1464
1465 xbar_adx1_in_port: port@28 {
1466 reg = <0x28>;
1467
1468 xbar_adx1_in_ep: endpoint {
1469 remote-endpoint = <&adx1_in_ep>;
1470 };
1471 };
1472
1473 port@29 {
1474 reg = <0x29>;
1475
1476 xbar_adx1_out1_ep: endpoint {
1477 remote-endpoint = <&adx1_out1_ep>;
1478 };
1479 };
1480
1481 port@2a {
1482 reg = <0x2a>;
1483
1484 xbar_adx1_out2_ep: endpoint {
1485 remote-endpoint = <&adx1_out2_ep>;
1486 };
1487 };
1488
1489 port@2b {
1490 reg = <0x2b>;
1491
1492 xbar_adx1_out3_ep: endpoint {
1493 remote-endpoint = <&adx1_out3_ep>;
1494 };
1495 };
1496
1497 port@2c {
1498 reg = <0x2c>;
1499
1500 xbar_adx1_out4_ep: endpoint {
1501 remote-endpoint = <&adx1_out4_ep>;
1502 };
1503 };
1504
1505 xbar_adx2_in_port: port@2d {
1506 reg = <0x2d>;
1507
1508 xbar_adx2_in_ep: endpoint {
1509 remote-endpoint = <&adx2_in_ep>;
1510 };
1511 };
1512
1513 port@2e {
1514 reg = <0x2e>;
1515
1516 xbar_adx2_out1_ep: endpoint {
1517 remote-endpoint = <&adx2_out1_ep>;
1518 };
1519 };
1520
1521 port@2f {
1522 reg = <0x2f>;
1523
1524 xbar_adx2_out2_ep: endpoint {
1525 remote-endpoint = <&adx2_out2_ep>;
1526 };
1527 };
1528
1529 port@30 {
1530 reg = <0x30>;
1531
1532 xbar_adx2_out3_ep: endpoint {
1533 remote-endpoint = <&adx2_out3_ep>;
1534 };
1535 };
1536
1537 port@31 {
1538 reg = <0x31>;
1539
1540 xbar_adx2_out4_ep: endpoint {
1541 remote-endpoint = <&adx2_out4_ep>;
1542 };
1543 };
1544
1545 xbar_mixer_in1_port: port@32 {
1546 reg = <0x32>;
1547
1548 xbar_mixer_in1_ep: endpoint {
1549 remote-endpoint = <&mixer_in1_ep>;
1550 };
1551 };
1552
1553 xbar_mixer_in2_port: port@33 {
1554 reg = <0x33>;
1555
1556 xbar_mixer_in2_ep: endpoint {
1557 remote-endpoint = <&mixer_in2_ep>;
1558 };
1559 };
1560
1561 xbar_mixer_in3_port: port@34 {
1562 reg = <0x34>;
1563
1564 xbar_mixer_in3_ep: endpoint {
1565 remote-endpoint = <&mixer_in3_ep>;
1566 };
1567 };
1568
1569 xbar_mixer_in4_port: port@35 {
1570 reg = <0x35>;
1571
1572 xbar_mixer_in4_ep: endpoint {
1573 remote-endpoint = <&mixer_in4_ep>;
1574 };
1575 };
1576
1577 xbar_mixer_in5_port: port@36 {
1578 reg = <0x36>;
1579
1580 xbar_mixer_in5_ep: endpoint {
1581 remote-endpoint = <&mixer_in5_ep>;
1582 };
1583 };
1584
1585 xbar_mixer_in6_port: port@37 {
1586 reg = <0x37>;
1587
1588 xbar_mixer_in6_ep: endpoint {
1589 remote-endpoint = <&mixer_in6_ep>;
1590 };
1591 };
1592
1593 xbar_mixer_in7_port: port@38 {
1594 reg = <0x38>;
1595
1596 xbar_mixer_in7_ep: endpoint {
1597 remote-endpoint = <&mixer_in7_ep>;
1598 };
1599 };
1600
1601 xbar_mixer_in8_port: port@39 {
1602 reg = <0x39>;
1603
1604 xbar_mixer_in8_ep: endpoint {
1605 remote-endpoint = <&mixer_in8_ep>;
1606 };
1607 };
1608
1609 xbar_mixer_in9_port: port@3a {
1610 reg = <0x3a>;
1611
1612 xbar_mixer_in9_ep: endpoint {
1613 remote-endpoint = <&mixer_in9_ep>;
1614 };
1615 };
1616
1617 xbar_mixer_in10_port: port@3b {
1618 reg = <0x3b>;
1619
1620 xbar_mixer_in10_ep: endpoint {
1621 remote-endpoint = <&mixer_in10_ep>;
1622 };
1623 };
1624
1625 port@3c {
1626 reg = <0x3c>;
1627
1628 xbar_mixer_out1_ep: endpoint {
1629 remote-endpoint = <&mixer_out1_ep>;
1630 };
1631 };
1632
1633 port@3d {
1634 reg = <0x3d>;
1635
1636 xbar_mixer_out2_ep: endpoint {
1637 remote-endpoint = <&mixer_out2_ep>;
1638 };
1639 };
1640
1641 port@3e {
1642 reg = <0x3e>;
1643
1644 xbar_mixer_out3_ep: endpoint {
1645 remote-endpoint = <&mixer_out3_ep>;
1646 };
1647 };
1648
1649 port@3f {
1650 reg = <0x3f>;
1651
1652 xbar_mixer_out4_ep: endpoint {
1653 remote-endpoint = <&mixer_out4_ep>;
1654 };
1655 };
1656
1657 port@40 {
1658 reg = <0x40>;
1659
1660 xbar_mixer_out5_ep: endpoint {
1661 remote-endpoint = <&mixer_out5_ep>;
1662 };
1663 };
1664
1665 xbar_ope1_in_port: port@41 {
1666 reg = <0x41>;
1667
1668 xbar_ope1_in_ep: endpoint {
1669 remote-endpoint = <&ope1_cif_in_ep>;
1670 };
1671 };
1672
1673 port@42 {
1674 reg = <0x42>;
1675
1676 xbar_ope1_out_ep: endpoint {
1677 remote-endpoint = <&ope1_cif_out_ep>;
1678 };
1679 };
1680
1681 xbar_ope2_in_port: port@43 {
1682 reg = <0x43>;
1683
1684 xbar_ope2_in_ep: endpoint {
1685 remote-endpoint = <&ope2_cif_in_ep>;
1686 };
1687 };
1688
1689 port@44 {
1690 reg = <0x44>;
1691
1692 xbar_ope2_out_ep: endpoint {
1693 remote-endpoint = <&ope2_cif_out_ep>;
1694 };
1695 };
1696 };
1697 };
1698 };
1699
1700 spi@70410000 {
1701 status = "okay";
1702
1703 flash@0 {
1704 compatible = "jedec,spi-nor";
1705 reg = <0>;
1706 spi-max-frequency = <104000000>;
1707 spi-tx-bus-width = <2>;
1708 spi-rx-bus-width = <2>;
1709 };
1710 };
1711
1712 clk32k_in: clock-32k {
1713 compatible = "fixed-clock";
1714 clock-frequency = <32768>;
1715 #clock-cells = <0>;
1716 };
1717
1718 cpus {
1719 cpu@0 {
1720 enable-method = "psci";
1721 };
1722
1723 cpu@1 {
1724 enable-method = "psci";
1725 };
1726
1727 cpu@2 {
1728 enable-method = "psci";
1729 };
1730
1731 cpu@3 {
1732 enable-method = "psci";
1733 };
1734
1735 idle-states {
1736 cpu-sleep {
1737 status = "okay";
1738 };
1739 };
1740 };
1741
1742 fan: pwm-fan {
1743 compatible = "pwm-fan";
1744 pwms = <&pwm 3 45334>;
1745
1746 cooling-levels = <0 64 128 255>;
1747 #cooling-cells = <2>;
1748 };
1749
1750 thermal-zones {
1751 cpu-thermal {
1752 trips {
1753 cpu_trip_critical: critical {
1754 temperature = <96500>;
1755 hysteresis = <0>;
1756 type = "critical";
1757 };
1758
1759 cpu_trip_hot: hot {
1760 temperature = <70000>;
1761 hysteresis = <2000>;
1762 type = "hot";
1763 };
1764
1765 cpu_trip_active: active {
1766 temperature = <50000>;
1767 hysteresis = <2000>;
1768 type = "active";
1769 };
1770
1771 cpu_trip_passive: passive {
1772 temperature = <30000>;
1773 hysteresis = <2000>;
1774 type = "passive";
1775 };
1776 };
1777
1778 cooling-maps {
1779 cpu-critical {
1780 cooling-device = <&fan 3 3>;
1781 trip = <&cpu_trip_critical>;
1782 };
1783
1784 cpu-hot {
1785 cooling-device = <&fan 2 2>;
1786 trip = <&cpu_trip_hot>;
1787 };
1788
1789 cpu-active {
1790 cooling-device = <&fan 1 1>;
1791 trip = <&cpu_trip_active>;
1792 };
1793
1794 cpu-passive {
1795 cooling-device = <&fan 0 0>;
1796 trip = <&cpu_trip_passive>;
1797 };
1798 };
1799 };
1800 };
1801
1802 gpio-keys {
1803 compatible = "gpio-keys";
1804
1805 key-power {
1806 label = "Power";
1807 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1808 linux,input-type = <EV_KEY>;
1809 linux,code = <KEY_POWER>;
1810 debounce-interval = <30>;
1811 wakeup-event-action = <EV_ACT_ASSERTED>;
1812 wakeup-source;
1813 };
1814
1815 key-force-recovery {
1816 label = "Force Recovery";
1817 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
1818 linux,input-type = <EV_KEY>;
1819 linux,code = <BTN_1>;
1820 debounce-interval = <30>;
1821 };
1822 };
1823
1824 psci {
1825 compatible = "arm,psci-1.0";
1826 method = "smc";
1827 };
1828
1829 vdd_5v0_sys: regulator-vdd-5v0-sys {
1830 compatible = "regulator-fixed";
1831
1832 regulator-name = "VDD_5V0_SYS";
1833 regulator-min-microvolt = <5000000>;
1834 regulator-max-microvolt = <5000000>;
1835 regulator-always-on;
1836 regulator-boot-on;
1837 };
1838
1839 vdd_3v3_sys: regulator-vdd-3v3-sys {
1840 compatible = "regulator-fixed";
1841
1842 regulator-name = "VDD_3V3_SYS";
1843 regulator-min-microvolt = <3300000>;
1844 regulator-max-microvolt = <3300000>;
1845 regulator-enable-ramp-delay = <240>;
1846 regulator-always-on;
1847 regulator-boot-on;
1848
1849 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1850 enable-active-high;
1851
1852 vin-supply = <&vdd_5v0_sys>;
1853 };
1854
1855 vdd_3v3_sd: regulator-vdd-3v3-sd {
1856 compatible = "regulator-fixed";
1857
1858 regulator-name = "VDD_3V3_SD";
1859 regulator-min-microvolt = <3300000>;
1860 regulator-max-microvolt = <3300000>;
1861
1862 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1863 enable-active-high;
1864
1865 vin-supply = <&vdd_3v3_sys>;
1866 };
1867
1868 vdd_hdmi: regulator-vdd-hdmi-5v0 {
1869 compatible = "regulator-fixed";
1870
1871 regulator-name = "VDD_HDMI_5V0";
1872 regulator-min-microvolt = <5000000>;
1873 regulator-max-microvolt = <5000000>;
1874
1875 vin-supply = <&vdd_5v0_sys>;
1876 };
1877
1878 vdd_hub_3v3: regulator-vdd-hub-3v3 {
1879 compatible = "regulator-fixed";
1880
1881 regulator-name = "VDD_HUB_3V3";
1882 regulator-min-microvolt = <3300000>;
1883 regulator-max-microvolt = <3300000>;
1884
1885 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1886 enable-active-high;
1887
1888 vin-supply = <&vdd_5v0_sys>;
1889 };
1890
1891 vdd_cpu: regulator-vdd-cpu {
1892 compatible = "regulator-fixed";
1893
1894 regulator-name = "VDD_CPU";
1895 regulator-min-microvolt = <5000000>;
1896 regulator-max-microvolt = <5000000>;
1897 regulator-always-on;
1898 regulator-boot-on;
1899
1900 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1901 enable-active-high;
1902
1903 vin-supply = <&vdd_5v0_sys>;
1904 };
1905
1906 vdd_gpu: regulator-vdd-gpu {
1907 compatible = "pwm-regulator";
1908 pwms = <&pwm 1 8000>;
1909
1910 regulator-name = "VDD_GPU";
1911 regulator-min-microvolt = <710000>;
1912 regulator-max-microvolt = <1320000>;
1913 regulator-ramp-delay = <80>;
1914 regulator-enable-ramp-delay = <2000>;
1915 regulator-settling-time-us = <160>;
1916
1917 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
1918 vin-supply = <&vdd_5v0_sys>;
1919 };
1920
1921 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {
1922 compatible = "regulator-fixed";
1923
1924 regulator-name = "AVDD_IO_EDP_1V05";
1925 regulator-min-microvolt = <1050000>;
1926 regulator-max-microvolt = <1050000>;
1927
1928 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1929 enable-active-high;
1930
1931 vin-supply = <&avdd_1v05_pll>;
1932 };
1933
1934 vdd_5v0_usb: regulator-vdd-5v-usb {
1935 compatible = "regulator-fixed";
1936
1937 regulator-name = "VDD_5V_USB";
1938 regulator-min-microvolt = <50000000>;
1939 regulator-max-microvolt = <50000000>;
1940
1941 vin-supply = <&vdd_5v0_sys>;
1942 };
1943
1944 sound {
1945 compatible = "nvidia,tegra210-audio-graph-card";
1946 status = "okay";
1947
1948 dais = /* FE */
1949 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1950 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1951 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1952 <&admaif10_port>,
1953 /* Router */
1954 <&xbar_i2s3_port>, <&xbar_i2s4_port>,
1955 <&xbar_dmic1_port>, <&xbar_dmic2_port>,
1956 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1957 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1958 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1959 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1960 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1961 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1962 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1963 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1964 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1965 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1966 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1967 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1968 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1969 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
1970 /* HW accelerators */
1971 <&sfc1_out_port>, <&sfc2_out_port>,
1972 <&sfc3_out_port>, <&sfc4_out_port>,
1973 <&mvc1_out_port>, <&mvc2_out_port>,
1974 <&amx1_out_port>, <&amx2_out_port>,
1975 <&adx1_out1_port>, <&adx1_out2_port>,
1976 <&adx1_out3_port>, <&adx1_out4_port>,
1977 <&adx2_out1_port>, <&adx2_out2_port>,
1978 <&adx2_out3_port>, <&adx2_out4_port>,
1979 <&mixer_out1_port>, <&mixer_out2_port>,
1980 <&mixer_out3_port>, <&mixer_out4_port>,
1981 <&mixer_out5_port>,
1982 <&ope1_out_port>, <&ope2_out_port>,
1983 /* I/O DAP Ports */
1984 <&i2s3_port>, <&i2s4_port>,
1985 <&dmic1_port>, <&dmic2_port>;
1986
1987 label = "NVIDIA Jetson Nano APE";
1988 };
1989 };
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