OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include "tegra210-p2180.dtsi"
0005 #include "tegra210-p2597.dtsi"
0006
0007 / {
0008 model = "NVIDIA Jetson TX1 Developer Kit";
0009 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
0010
0011 pcie@1003000 {
0012 status = "okay";
0013
0014 hvddio-pex-supply = <&vdd_1v8>;
0015 dvddio-pex-supply = <&vdd_pex_1v05>;
0016 vddio-pex-ctl-supply = <&vdd_1v8>;
0017
0018 pci@1,0 {
0019 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
0020 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
0021 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
0022 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
0023 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
0024 status = "okay";
0025 };
0026
0027 pci@2,0 {
0028 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
0029 phy-names = "pcie-0";
0030 status = "okay";
0031 };
0032 };
0033
0034 host1x@50000000 {
0035 dsi@54300000 {
0036 status = "okay";
0037
0038 avdd-dsi-csi-supply = <&vdd_dsi_csi>;
0039
0040 panel@0 {
0041 compatible = "auo,b080uan01";
0042 reg = <0>;
0043
0044 enable-gpios = <&gpio TEGRA_GPIO(V, 2)
0045 GPIO_ACTIVE_HIGH>;
0046 power-supply = <&vdd_5v0_io>;
0047 backlight = <&backlight>;
0048 };
0049 };
0050 };
0051
0052 i2c@7000c400 {
0053 backlight: backlight@2c {
0054 compatible = "ti,lp8557";
0055 reg = <0x2c>;
0056 power-supply = <&vdd_3v3_sys>;
0057
0058 dev-ctrl = /bits/ 8 <0x80>;
0059 init-brt = /bits/ 8 <0xff>;
0060
0061 pwm-period = <29334>;
0062
0063 pwms = <&pwm 0 29334>;
0064 pwm-names = "lp8557";
0065
0066 /* 3 LED string */
0067 rom_14h {
0068 rom-addr = /bits/ 8 <0x14>;
0069 rom-val = /bits/ 8 <0x87>;
0070 };
0071
0072 /* boost frequency 1 MHz */
0073 rom_13h {
0074 rom-addr = /bits/ 8 <0x13>;
0075 rom-val = /bits/ 8 <0x01>;
0076 };
0077 };
0078 };
0079
0080 i2c@7000c500 {
0081 /* carrier board ID EEPROM */
0082 eeprom@57 {
0083 compatible = "atmel,24c02";
0084 reg = <0x57>;
0085
0086 label = "system";
0087 vcc-supply = <&vdd_1v8>;
0088 address-width = <8>;
0089 pagesize = <8>;
0090 size = <256>;
0091 read-only;
0092 };
0093 };
0094
0095 clock@70110000 {
0096 status = "okay";
0097
0098 nvidia,cf = <6>;
0099 nvidia,ci = <0>;
0100 nvidia,cg = <2>;
0101 nvidia,droop-ctrl = <0x00000f00>;
0102 nvidia,force-mode = <1>;
0103 nvidia,sample-rate = <25000>;
0104
0105 nvidia,pwm-min-microvolts = <708000>;
0106 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
0107 nvidia,pwm-to-pmic;
0108 nvidia,pwm-tristate-microvolts = <1000000>;
0109 nvidia,pwm-voltage-step-microvolts = <19200>;
0110
0111 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
0112 pinctrl-0 = <&dvfs_pwm_active_state>;
0113 pinctrl-1 = <&dvfs_pwm_inactive_state>;
0114 };
0115
0116 aconnect@702c0000 {
0117 status = "okay";
0118
0119 dma-controller@702e2000 {
0120 status = "okay";
0121 };
0122
0123 interrupt-controller@702f9000 {
0124 status = "okay";
0125 };
0126
0127 ahub@702d0800 {
0128 status = "okay";
0129
0130 admaif@702d0000 {
0131 status = "okay";
0132 };
0133
0134 i2s@702d1000 {
0135 status = "okay";
0136
0137 ports {
0138 #address-cells = <1>;
0139 #size-cells = <0>;
0140
0141 port@0 {
0142 reg = <0>;
0143
0144 i2s1_cif_ep: endpoint {
0145 remote-endpoint = <&xbar_i2s1_ep>;
0146 };
0147 };
0148
0149 i2s1_port: port@1 {
0150 reg = <1>;
0151
0152 i2s1_dap_ep: endpoint {
0153 dai-format = "i2s";
0154 /* Placeholder for external Codec */
0155 };
0156 };
0157 };
0158 };
0159
0160 i2s@702d1100 {
0161 status = "okay";
0162
0163 ports {
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166
0167 port@0 {
0168 reg = <0>;
0169
0170 i2s2_cif_ep: endpoint {
0171 remote-endpoint = <&xbar_i2s2_ep>;
0172 };
0173 };
0174
0175 i2s2_port: port@1 {
0176 reg = <1>;
0177
0178 i2s2_dap_ep: endpoint {
0179 dai-format = "i2s";
0180 /* Placeholder for external Codec */
0181 };
0182 };
0183 };
0184 };
0185
0186 i2s@702d1200 {
0187 status = "okay";
0188
0189 ports {
0190 #address-cells = <1>;
0191 #size-cells = <0>;
0192
0193 port@0 {
0194 reg = <0>;
0195
0196 i2s3_cif_ep: endpoint {
0197 remote-endpoint = <&xbar_i2s3_ep>;
0198 };
0199 };
0200
0201 i2s3_port: port@1 {
0202 reg = <1>;
0203
0204 i2s3_dap_ep: endpoint {
0205 dai-format = "i2s";
0206 /* Placeholder for external Codec */
0207 };
0208 };
0209 };
0210 };
0211
0212 i2s@702d1300 {
0213 status = "okay";
0214
0215 ports {
0216 #address-cells = <1>;
0217 #size-cells = <0>;
0218
0219 port@0 {
0220 reg = <0>;
0221
0222 i2s4_cif_ep: endpoint {
0223 remote-endpoint = <&xbar_i2s4_ep>;
0224 };
0225 };
0226
0227 i2s4_port: port@1 {
0228 reg = <1>;
0229
0230 i2s4_dap_ep: endpoint {
0231 dai-format = "i2s";
0232 /* Placeholder for external Codec */
0233 };
0234 };
0235 };
0236 };
0237
0238 i2s@702d1400 {
0239 status = "okay";
0240
0241 ports {
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244
0245 port@0 {
0246 reg = <0>;
0247
0248 i2s5_cif_ep: endpoint {
0249 remote-endpoint = <&xbar_i2s5_ep>;
0250 };
0251 };
0252
0253 i2s5_port: port@1 {
0254 reg = <1>;
0255
0256 i2s5_dap_ep: endpoint {
0257 dai-format = "i2s";
0258 /* Placeholder for external Codec */
0259 };
0260 };
0261 };
0262 };
0263
0264 dmic@702d4000 {
0265 status = "okay";
0266
0267 ports {
0268 #address-cells = <1>;
0269 #size-cells = <0>;
0270
0271 port@0 {
0272 reg = <0>;
0273
0274 dmic1_cif_ep: endpoint {
0275 remote-endpoint = <&xbar_dmic1_ep>;
0276 };
0277 };
0278
0279 dmic1_port: port@1 {
0280 reg = <1>;
0281
0282 dmic1_dap_ep: endpoint {
0283 /* Placeholder for external Codec */
0284 };
0285 };
0286 };
0287 };
0288
0289 dmic@702d4100 {
0290 status = "okay";
0291
0292 ports {
0293 #address-cells = <1>;
0294 #size-cells = <0>;
0295
0296 port@0 {
0297 reg = <0>;
0298
0299 dmic2_cif_ep: endpoint {
0300 remote-endpoint = <&xbar_dmic2_ep>;
0301 };
0302 };
0303
0304 dmic2_port: port@1 {
0305 reg = <1>;
0306
0307 dmic2_dap_ep: endpoint {
0308 /* Placeholder for external Codec */
0309 };
0310 };
0311 };
0312 };
0313
0314 dmic@702d4200 {
0315 status = "okay";
0316
0317 ports {
0318 #address-cells = <1>;
0319 #size-cells = <0>;
0320
0321 port@0 {
0322 reg = <0>;
0323
0324 dmic3_cif_ep: endpoint {
0325 remote-endpoint = <&xbar_dmic3_ep>;
0326 };
0327 };
0328
0329 dmic3_port: port@1 {
0330 reg = <1>;
0331
0332 dmic3_dap_ep: endpoint {
0333 /* Placeholder for external Codec */
0334 };
0335 };
0336 };
0337 };
0338
0339 sfc@702d2000 {
0340 status = "okay";
0341
0342 ports {
0343 #address-cells = <1>;
0344 #size-cells = <0>;
0345
0346 port@0 {
0347 reg = <0>;
0348
0349 sfc1_cif_in_ep: endpoint {
0350 remote-endpoint = <&xbar_sfc1_in_ep>;
0351 };
0352 };
0353
0354 sfc1_out_port: port@1 {
0355 reg = <1>;
0356
0357 sfc1_cif_out_ep: endpoint {
0358 remote-endpoint = <&xbar_sfc1_out_ep>;
0359 };
0360 };
0361 };
0362 };
0363
0364 sfc@702d2200 {
0365 status = "okay";
0366
0367 ports {
0368 #address-cells = <1>;
0369 #size-cells = <0>;
0370
0371 port@0 {
0372 reg = <0>;
0373
0374 sfc2_cif_in_ep: endpoint {
0375 remote-endpoint = <&xbar_sfc2_in_ep>;
0376 };
0377 };
0378
0379 sfc2_out_port: port@1 {
0380 reg = <1>;
0381
0382 sfc2_cif_out_ep: endpoint {
0383 remote-endpoint = <&xbar_sfc2_out_ep>;
0384 };
0385 };
0386 };
0387 };
0388
0389 sfc@702d2400 {
0390 status = "okay";
0391
0392 ports {
0393 #address-cells = <1>;
0394 #size-cells = <0>;
0395
0396 port@0 {
0397 reg = <0>;
0398
0399 sfc3_cif_in_ep: endpoint {
0400 remote-endpoint = <&xbar_sfc3_in_ep>;
0401 };
0402 };
0403
0404 sfc3_out_port: port@1 {
0405 reg = <1>;
0406
0407 sfc3_cif_out_ep: endpoint {
0408 remote-endpoint = <&xbar_sfc3_out_ep>;
0409 };
0410 };
0411 };
0412 };
0413
0414 sfc@702d2600 {
0415 status = "okay";
0416
0417 ports {
0418 #address-cells = <1>;
0419 #size-cells = <0>;
0420
0421 port@0 {
0422 reg = <0>;
0423
0424 sfc4_cif_in_ep: endpoint {
0425 remote-endpoint = <&xbar_sfc4_in_ep>;
0426 };
0427 };
0428
0429 sfc4_out_port: port@1 {
0430 reg = <1>;
0431
0432 sfc4_cif_out_ep: endpoint {
0433 remote-endpoint = <&xbar_sfc4_out_ep>;
0434 };
0435 };
0436 };
0437 };
0438
0439 mvc@702da000 {
0440 status = "okay";
0441
0442 ports {
0443 #address-cells = <1>;
0444 #size-cells = <0>;
0445
0446 port@0 {
0447 reg = <0>;
0448
0449 mvc1_cif_in_ep: endpoint {
0450 remote-endpoint = <&xbar_mvc1_in_ep>;
0451 };
0452 };
0453
0454 mvc1_out_port: port@1 {
0455 reg = <1>;
0456
0457 mvc1_cif_out_ep: endpoint {
0458 remote-endpoint = <&xbar_mvc1_out_ep>;
0459 };
0460 };
0461 };
0462 };
0463
0464 mvc@702da200 {
0465 status = "okay";
0466
0467 ports {
0468 #address-cells = <1>;
0469 #size-cells = <0>;
0470
0471 port@0 {
0472 reg = <0>;
0473
0474 mvc2_cif_in_ep: endpoint {
0475 remote-endpoint = <&xbar_mvc2_in_ep>;
0476 };
0477 };
0478
0479 mvc2_out_port: port@1 {
0480 reg = <1>;
0481
0482 mvc2_cif_out_ep: endpoint {
0483 remote-endpoint = <&xbar_mvc2_out_ep>;
0484 };
0485 };
0486 };
0487 };
0488
0489 amx@702d3000 {
0490 status = "okay";
0491
0492 ports {
0493 #address-cells = <1>;
0494 #size-cells = <0>;
0495
0496 port@0 {
0497 reg = <0>;
0498
0499 amx1_in1_ep: endpoint {
0500 remote-endpoint = <&xbar_amx1_in1_ep>;
0501 };
0502 };
0503
0504 port@1 {
0505 reg = <1>;
0506
0507 amx1_in2_ep: endpoint {
0508 remote-endpoint = <&xbar_amx1_in2_ep>;
0509 };
0510 };
0511
0512 port@2 {
0513 reg = <2>;
0514
0515 amx1_in3_ep: endpoint {
0516 remote-endpoint = <&xbar_amx1_in3_ep>;
0517 };
0518 };
0519
0520 port@3 {
0521 reg = <3>;
0522
0523 amx1_in4_ep: endpoint {
0524 remote-endpoint = <&xbar_amx1_in4_ep>;
0525 };
0526 };
0527
0528 amx1_out_port: port@4 {
0529 reg = <4>;
0530
0531 amx1_out_ep: endpoint {
0532 remote-endpoint = <&xbar_amx1_out_ep>;
0533 };
0534 };
0535 };
0536 };
0537
0538 amx@702d3100 {
0539 status = "okay";
0540
0541 ports {
0542 #address-cells = <1>;
0543 #size-cells = <0>;
0544
0545 port@0 {
0546 reg = <0>;
0547
0548 amx2_in1_ep: endpoint {
0549 remote-endpoint = <&xbar_amx2_in1_ep>;
0550 };
0551 };
0552
0553 port@1 {
0554 reg = <1>;
0555
0556 amx2_in2_ep: endpoint {
0557 remote-endpoint = <&xbar_amx2_in2_ep>;
0558 };
0559 };
0560
0561 amx2_in3_port: port@2 {
0562 reg = <2>;
0563
0564 amx2_in3_ep: endpoint {
0565 remote-endpoint = <&xbar_amx2_in3_ep>;
0566 };
0567 };
0568
0569 amx2_in4_port: port@3 {
0570 reg = <3>;
0571
0572 amx2_in4_ep: endpoint {
0573 remote-endpoint = <&xbar_amx2_in4_ep>;
0574 };
0575 };
0576
0577 amx2_out_port: port@4 {
0578 reg = <4>;
0579
0580 amx2_out_ep: endpoint {
0581 remote-endpoint = <&xbar_amx2_out_ep>;
0582 };
0583 };
0584 };
0585 };
0586
0587 adx@702d3800 {
0588 status = "okay";
0589
0590 ports {
0591 #address-cells = <1>;
0592 #size-cells = <0>;
0593
0594 port@0 {
0595 reg = <0>;
0596
0597 adx1_in_ep: endpoint {
0598 remote-endpoint = <&xbar_adx1_in_ep>;
0599 };
0600 };
0601
0602 adx1_out1_port: port@1 {
0603 reg = <1>;
0604
0605 adx1_out1_ep: endpoint {
0606 remote-endpoint = <&xbar_adx1_out1_ep>;
0607 };
0608 };
0609
0610 adx1_out2_port: port@2 {
0611 reg = <2>;
0612
0613 adx1_out2_ep: endpoint {
0614 remote-endpoint = <&xbar_adx1_out2_ep>;
0615 };
0616 };
0617
0618 adx1_out3_port: port@3 {
0619 reg = <3>;
0620
0621 adx1_out3_ep: endpoint {
0622 remote-endpoint = <&xbar_adx1_out3_ep>;
0623 };
0624 };
0625
0626 adx1_out4_port: port@4 {
0627 reg = <4>;
0628
0629 adx1_out4_ep: endpoint {
0630 remote-endpoint = <&xbar_adx1_out4_ep>;
0631 };
0632 };
0633 };
0634 };
0635
0636 adx@702d3900 {
0637 status = "okay";
0638
0639 ports {
0640 #address-cells = <1>;
0641 #size-cells = <0>;
0642
0643 port@0 {
0644 reg = <0>;
0645
0646 adx2_in_ep: endpoint {
0647 remote-endpoint = <&xbar_adx2_in_ep>;
0648 };
0649 };
0650
0651 adx2_out1_port: port@1 {
0652 reg = <1>;
0653
0654 adx2_out1_ep: endpoint {
0655 remote-endpoint = <&xbar_adx2_out1_ep>;
0656 };
0657 };
0658
0659 adx2_out2_port: port@2 {
0660 reg = <2>;
0661
0662 adx2_out2_ep: endpoint {
0663 remote-endpoint = <&xbar_adx2_out2_ep>;
0664 };
0665 };
0666
0667 adx2_out3_port: port@3 {
0668 reg = <3>;
0669
0670 adx2_out3_ep: endpoint {
0671 remote-endpoint = <&xbar_adx2_out3_ep>;
0672 };
0673 };
0674
0675 adx2_out4_port: port@4 {
0676 reg = <4>;
0677
0678 adx2_out4_ep: endpoint {
0679 remote-endpoint = <&xbar_adx2_out4_ep>;
0680 };
0681 };
0682 };
0683 };
0684
0685 processing-engine@702d8000 {
0686 status = "okay";
0687
0688 ports {
0689 #address-cells = <1>;
0690 #size-cells = <0>;
0691
0692 port@0 {
0693 reg = <0x0>;
0694
0695 ope1_cif_in_ep: endpoint {
0696 remote-endpoint = <&xbar_ope1_in_ep>;
0697 };
0698 };
0699
0700 ope1_out_port: port@1 {
0701 reg = <0x1>;
0702
0703 ope1_cif_out_ep: endpoint {
0704 remote-endpoint = <&xbar_ope1_out_ep>;
0705 };
0706 };
0707 };
0708 };
0709
0710 processing-engine@702d8400 {
0711 status = "okay";
0712
0713 ports {
0714 #address-cells = <1>;
0715 #size-cells = <0>;
0716
0717 port@0 {
0718 reg = <0x0>;
0719
0720 ope2_cif_in_ep: endpoint {
0721 remote-endpoint = <&xbar_ope2_in_ep>;
0722 };
0723 };
0724
0725 ope2_out_port: port@1 {
0726 reg = <0x1>;
0727
0728 ope2_cif_out_ep: endpoint {
0729 remote-endpoint = <&xbar_ope2_out_ep>;
0730 };
0731 };
0732 };
0733 };
0734
0735 amixer@702dbb00 {
0736 status = "okay";
0737
0738 ports {
0739 #address-cells = <1>;
0740 #size-cells = <0>;
0741
0742 port@0 {
0743 reg = <0x0>;
0744
0745 mixer_in1_ep: endpoint {
0746 remote-endpoint = <&xbar_mixer_in1_ep>;
0747 };
0748 };
0749
0750 port@1 {
0751 reg = <0x1>;
0752
0753 mixer_in2_ep: endpoint {
0754 remote-endpoint = <&xbar_mixer_in2_ep>;
0755 };
0756 };
0757
0758 port@2 {
0759 reg = <0x2>;
0760
0761 mixer_in3_ep: endpoint {
0762 remote-endpoint = <&xbar_mixer_in3_ep>;
0763 };
0764 };
0765
0766 port@3 {
0767 reg = <0x3>;
0768
0769 mixer_in4_ep: endpoint {
0770 remote-endpoint = <&xbar_mixer_in4_ep>;
0771 };
0772 };
0773
0774 port@4 {
0775 reg = <0x4>;
0776
0777 mixer_in5_ep: endpoint {
0778 remote-endpoint = <&xbar_mixer_in5_ep>;
0779 };
0780 };
0781
0782 port@5 {
0783 reg = <0x5>;
0784
0785 mixer_in6_ep: endpoint {
0786 remote-endpoint = <&xbar_mixer_in6_ep>;
0787 };
0788 };
0789
0790 port@6 {
0791 reg = <0x6>;
0792
0793 mixer_in7_ep: endpoint {
0794 remote-endpoint = <&xbar_mixer_in7_ep>;
0795 };
0796 };
0797
0798 port@7 {
0799 reg = <0x7>;
0800
0801 mixer_in8_ep: endpoint {
0802 remote-endpoint = <&xbar_mixer_in8_ep>;
0803 };
0804 };
0805
0806 port@8 {
0807 reg = <0x8>;
0808
0809 mixer_in9_ep: endpoint {
0810 remote-endpoint = <&xbar_mixer_in9_ep>;
0811 };
0812 };
0813
0814 port@9 {
0815 reg = <0x9>;
0816
0817 mixer_in10_ep: endpoint {
0818 remote-endpoint = <&xbar_mixer_in10_ep>;
0819 };
0820 };
0821
0822 mixer_out1_port: port@a {
0823 reg = <0xa>;
0824
0825 mixer_out1_ep: endpoint {
0826 remote-endpoint = <&xbar_mixer_out1_ep>;
0827 };
0828 };
0829
0830 mixer_out2_port: port@b {
0831 reg = <0xb>;
0832
0833 mixer_out2_ep: endpoint {
0834 remote-endpoint = <&xbar_mixer_out2_ep>;
0835 };
0836 };
0837
0838 mixer_out3_port: port@c {
0839 reg = <0xc>;
0840
0841 mixer_out3_ep: endpoint {
0842 remote-endpoint = <&xbar_mixer_out3_ep>;
0843 };
0844 };
0845
0846 mixer_out4_port: port@d {
0847 reg = <0xd>;
0848
0849 mixer_out4_ep: endpoint {
0850 remote-endpoint = <&xbar_mixer_out4_ep>;
0851 };
0852 };
0853
0854 mixer_out5_port: port@e {
0855 reg = <0xe>;
0856
0857 mixer_out5_ep: endpoint {
0858 remote-endpoint = <&xbar_mixer_out5_ep>;
0859 };
0860 };
0861 };
0862 };
0863
0864 ports {
0865 xbar_i2s1_port: port@a {
0866 reg = <0xa>;
0867
0868 xbar_i2s1_ep: endpoint {
0869 remote-endpoint = <&i2s1_cif_ep>;
0870 };
0871 };
0872
0873 xbar_i2s2_port: port@b {
0874 reg = <0xb>;
0875
0876 xbar_i2s2_ep: endpoint {
0877 remote-endpoint = <&i2s2_cif_ep>;
0878 };
0879 };
0880
0881 xbar_i2s3_port: port@c {
0882 reg = <0xc>;
0883
0884 xbar_i2s3_ep: endpoint {
0885 remote-endpoint = <&i2s3_cif_ep>;
0886 };
0887 };
0888
0889 xbar_i2s4_port: port@d {
0890 reg = <0xd>;
0891
0892 xbar_i2s4_ep: endpoint {
0893 remote-endpoint = <&i2s4_cif_ep>;
0894 };
0895 };
0896
0897 xbar_i2s5_port: port@e {
0898 reg = <0xe>;
0899
0900 xbar_i2s5_ep: endpoint {
0901 remote-endpoint = <&i2s5_cif_ep>;
0902 };
0903 };
0904
0905 xbar_dmic1_port: port@f {
0906 reg = <0xf>;
0907
0908 xbar_dmic1_ep: endpoint {
0909 remote-endpoint = <&dmic1_cif_ep>;
0910 };
0911 };
0912
0913 xbar_dmic2_port: port@10 {
0914 reg = <0x10>;
0915
0916 xbar_dmic2_ep: endpoint {
0917 remote-endpoint = <&dmic2_cif_ep>;
0918 };
0919 };
0920
0921 xbar_dmic3_port: port@11 {
0922 reg = <0x11>;
0923
0924 xbar_dmic3_ep: endpoint {
0925 remote-endpoint = <&dmic3_cif_ep>;
0926 };
0927 };
0928
0929 xbar_sfc1_in_port: port@12 {
0930 reg = <0x12>;
0931
0932 xbar_sfc1_in_ep: endpoint {
0933 remote-endpoint = <&sfc1_cif_in_ep>;
0934 };
0935 };
0936
0937 port@13 {
0938 reg = <0x13>;
0939
0940 xbar_sfc1_out_ep: endpoint {
0941 remote-endpoint = <&sfc1_cif_out_ep>;
0942 };
0943 };
0944
0945 xbar_sfc2_in_port: port@14 {
0946 reg = <0x14>;
0947
0948 xbar_sfc2_in_ep: endpoint {
0949 remote-endpoint = <&sfc2_cif_in_ep>;
0950 };
0951 };
0952
0953 port@15 {
0954 reg = <0x15>;
0955
0956 xbar_sfc2_out_ep: endpoint {
0957 remote-endpoint = <&sfc2_cif_out_ep>;
0958 };
0959 };
0960
0961 xbar_sfc3_in_port: port@16 {
0962 reg = <0x16>;
0963
0964 xbar_sfc3_in_ep: endpoint {
0965 remote-endpoint = <&sfc3_cif_in_ep>;
0966 };
0967 };
0968
0969 port@17 {
0970 reg = <0x17>;
0971
0972 xbar_sfc3_out_ep: endpoint {
0973 remote-endpoint = <&sfc3_cif_out_ep>;
0974 };
0975 };
0976
0977 xbar_sfc4_in_port: port@18 {
0978 reg = <0x18>;
0979
0980 xbar_sfc4_in_ep: endpoint {
0981 remote-endpoint = <&sfc4_cif_in_ep>;
0982 };
0983 };
0984
0985 port@19 {
0986 reg = <0x19>;
0987
0988 xbar_sfc4_out_ep: endpoint {
0989 remote-endpoint = <&sfc4_cif_out_ep>;
0990 };
0991 };
0992
0993 xbar_mvc1_in_port: port@1a {
0994 reg = <0x1a>;
0995
0996 xbar_mvc1_in_ep: endpoint {
0997 remote-endpoint = <&mvc1_cif_in_ep>;
0998 };
0999 };
1000
1001 port@1b {
1002 reg = <0x1b>;
1003
1004 xbar_mvc1_out_ep: endpoint {
1005 remote-endpoint = <&mvc1_cif_out_ep>;
1006 };
1007 };
1008
1009 xbar_mvc2_in_port: port@1c {
1010 reg = <0x1c>;
1011
1012 xbar_mvc2_in_ep: endpoint {
1013 remote-endpoint = <&mvc2_cif_in_ep>;
1014 };
1015 };
1016
1017 port@1d {
1018 reg = <0x1d>;
1019
1020 xbar_mvc2_out_ep: endpoint {
1021 remote-endpoint = <&mvc2_cif_out_ep>;
1022 };
1023 };
1024
1025 xbar_amx1_in1_port: port@1e {
1026 reg = <0x1e>;
1027
1028 xbar_amx1_in1_ep: endpoint {
1029 remote-endpoint = <&amx1_in1_ep>;
1030 };
1031 };
1032
1033 xbar_amx1_in2_port: port@1f {
1034 reg = <0x1f>;
1035
1036 xbar_amx1_in2_ep: endpoint {
1037 remote-endpoint = <&amx1_in2_ep>;
1038 };
1039 };
1040
1041 xbar_amx1_in3_port: port@20 {
1042 reg = <0x20>;
1043
1044 xbar_amx1_in3_ep: endpoint {
1045 remote-endpoint = <&amx1_in3_ep>;
1046 };
1047 };
1048
1049 xbar_amx1_in4_port: port@21 {
1050 reg = <0x21>;
1051
1052 xbar_amx1_in4_ep: endpoint {
1053 remote-endpoint = <&amx1_in4_ep>;
1054 };
1055 };
1056
1057 port@22 {
1058 reg = <0x22>;
1059
1060 xbar_amx1_out_ep: endpoint {
1061 remote-endpoint = <&amx1_out_ep>;
1062 };
1063 };
1064
1065 xbar_amx2_in1_port: port@23 {
1066 reg = <0x23>;
1067
1068 xbar_amx2_in1_ep: endpoint {
1069 remote-endpoint = <&amx2_in1_ep>;
1070 };
1071 };
1072
1073 xbar_amx2_in2_port: port@24 {
1074 reg = <0x24>;
1075
1076 xbar_amx2_in2_ep: endpoint {
1077 remote-endpoint = <&amx2_in2_ep>;
1078 };
1079 };
1080
1081 xbar_amx2_in3_port: port@25 {
1082 reg = <0x25>;
1083
1084 xbar_amx2_in3_ep: endpoint {
1085 remote-endpoint = <&amx2_in3_ep>;
1086 };
1087 };
1088
1089 xbar_amx2_in4_port: port@26 {
1090 reg = <0x26>;
1091
1092 xbar_amx2_in4_ep: endpoint {
1093 remote-endpoint = <&amx2_in4_ep>;
1094 };
1095 };
1096
1097 port@27 {
1098 reg = <0x27>;
1099
1100 xbar_amx2_out_ep: endpoint {
1101 remote-endpoint = <&amx2_out_ep>;
1102 };
1103 };
1104
1105 xbar_adx1_in_port: port@28 {
1106 reg = <0x28>;
1107
1108 xbar_adx1_in_ep: endpoint {
1109 remote-endpoint = <&adx1_in_ep>;
1110 };
1111 };
1112
1113 port@29 {
1114 reg = <0x29>;
1115
1116 xbar_adx1_out1_ep: endpoint {
1117 remote-endpoint = <&adx1_out1_ep>;
1118 };
1119 };
1120
1121 port@2a {
1122 reg = <0x2a>;
1123
1124 xbar_adx1_out2_ep: endpoint {
1125 remote-endpoint = <&adx1_out2_ep>;
1126 };
1127 };
1128
1129 port@2b {
1130 reg = <0x2b>;
1131
1132 xbar_adx1_out3_ep: endpoint {
1133 remote-endpoint = <&adx1_out3_ep>;
1134 };
1135 };
1136
1137 port@2c {
1138 reg = <0x2c>;
1139
1140 xbar_adx1_out4_ep: endpoint {
1141 remote-endpoint = <&adx1_out4_ep>;
1142 };
1143 };
1144
1145 xbar_adx2_in_port: port@2d {
1146 reg = <0x2d>;
1147
1148 xbar_adx2_in_ep: endpoint {
1149 remote-endpoint = <&adx2_in_ep>;
1150 };
1151 };
1152
1153 port@2e {
1154 reg = <0x2e>;
1155
1156 xbar_adx2_out1_ep: endpoint {
1157 remote-endpoint = <&adx2_out1_ep>;
1158 };
1159 };
1160
1161 port@2f {
1162 reg = <0x2f>;
1163
1164 xbar_adx2_out2_ep: endpoint {
1165 remote-endpoint = <&adx2_out2_ep>;
1166 };
1167 };
1168
1169 port@30 {
1170 reg = <0x30>;
1171
1172 xbar_adx2_out3_ep: endpoint {
1173 remote-endpoint = <&adx2_out3_ep>;
1174 };
1175 };
1176
1177 port@31 {
1178 reg = <0x31>;
1179
1180 xbar_adx2_out4_ep: endpoint {
1181 remote-endpoint = <&adx2_out4_ep>;
1182 };
1183 };
1184
1185 xbar_mixer_in1_port: port@32 {
1186 reg = <0x32>;
1187
1188 xbar_mixer_in1_ep: endpoint {
1189 remote-endpoint = <&mixer_in1_ep>;
1190 };
1191 };
1192
1193 xbar_mixer_in2_port: port@33 {
1194 reg = <0x33>;
1195
1196 xbar_mixer_in2_ep: endpoint {
1197 remote-endpoint = <&mixer_in2_ep>;
1198 };
1199 };
1200
1201 xbar_mixer_in3_port: port@34 {
1202 reg = <0x34>;
1203
1204 xbar_mixer_in3_ep: endpoint {
1205 remote-endpoint = <&mixer_in3_ep>;
1206 };
1207 };
1208
1209 xbar_mixer_in4_port: port@35 {
1210 reg = <0x35>;
1211
1212 xbar_mixer_in4_ep: endpoint {
1213 remote-endpoint = <&mixer_in4_ep>;
1214 };
1215 };
1216
1217 xbar_mixer_in5_port: port@36 {
1218 reg = <0x36>;
1219
1220 xbar_mixer_in5_ep: endpoint {
1221 remote-endpoint = <&mixer_in5_ep>;
1222 };
1223 };
1224
1225 xbar_mixer_in6_port: port@37 {
1226 reg = <0x37>;
1227
1228 xbar_mixer_in6_ep: endpoint {
1229 remote-endpoint = <&mixer_in6_ep>;
1230 };
1231 };
1232
1233 xbar_mixer_in7_port: port@38 {
1234 reg = <0x38>;
1235
1236 xbar_mixer_in7_ep: endpoint {
1237 remote-endpoint = <&mixer_in7_ep>;
1238 };
1239 };
1240
1241 xbar_mixer_in8_port: port@39 {
1242 reg = <0x39>;
1243
1244 xbar_mixer_in8_ep: endpoint {
1245 remote-endpoint = <&mixer_in8_ep>;
1246 };
1247 };
1248
1249 xbar_mixer_in9_port: port@3a {
1250 reg = <0x3a>;
1251
1252 xbar_mixer_in9_ep: endpoint {
1253 remote-endpoint = <&mixer_in9_ep>;
1254 };
1255 };
1256
1257 xbar_mixer_in10_port: port@3b {
1258 reg = <0x3b>;
1259
1260 xbar_mixer_in10_ep: endpoint {
1261 remote-endpoint = <&mixer_in10_ep>;
1262 };
1263 };
1264
1265 port@3c {
1266 reg = <0x3c>;
1267
1268 xbar_mixer_out1_ep: endpoint {
1269 remote-endpoint = <&mixer_out1_ep>;
1270 };
1271 };
1272
1273 port@3d {
1274 reg = <0x3d>;
1275
1276 xbar_mixer_out2_ep: endpoint {
1277 remote-endpoint = <&mixer_out2_ep>;
1278 };
1279 };
1280
1281 port@3e {
1282 reg = <0x3e>;
1283
1284 xbar_mixer_out3_ep: endpoint {
1285 remote-endpoint = <&mixer_out3_ep>;
1286 };
1287 };
1288
1289 port@3f {
1290 reg = <0x3f>;
1291
1292 xbar_mixer_out4_ep: endpoint {
1293 remote-endpoint = <&mixer_out4_ep>;
1294 };
1295 };
1296
1297 port@40 {
1298 reg = <0x40>;
1299
1300 xbar_mixer_out5_ep: endpoint {
1301 remote-endpoint = <&mixer_out5_ep>;
1302 };
1303 };
1304
1305 xbar_ope1_in_port: port@41 {
1306 reg = <0x41>;
1307
1308 xbar_ope1_in_ep: endpoint {
1309 remote-endpoint = <&ope1_cif_in_ep>;
1310 };
1311 };
1312
1313 port@42 {
1314 reg = <0x42>;
1315
1316 xbar_ope1_out_ep: endpoint {
1317 remote-endpoint = <&ope1_cif_out_ep>;
1318 };
1319 };
1320
1321 xbar_ope2_in_port: port@43 {
1322 reg = <0x43>;
1323
1324 xbar_ope2_in_ep: endpoint {
1325 remote-endpoint = <&ope2_cif_in_ep>;
1326 };
1327 };
1328
1329 port@44 {
1330 reg = <0x44>;
1331
1332 xbar_ope2_out_ep: endpoint {
1333 remote-endpoint = <&ope2_cif_out_ep>;
1334 };
1335 };
1336 };
1337 };
1338 };
1339
1340 sound {
1341 compatible = "nvidia,tegra210-audio-graph-card";
1342 status = "okay";
1343
1344 dais = /* FE */
1345 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1346 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1347 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1348 <&admaif10_port>,
1349 /* Router */
1350 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
1351 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>,
1352 <&xbar_dmic2_port>, <&xbar_dmic3_port>,
1353 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1354 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1355 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1356 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1357 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1358 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1359 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1360 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1361 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1362 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1363 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1364 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1365 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1366 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
1367 /* HW accelerators */
1368 <&sfc1_out_port>, <&sfc2_out_port>,
1369 <&sfc3_out_port>, <&sfc4_out_port>,
1370 <&mvc1_out_port>, <&mvc2_out_port>,
1371 <&amx1_out_port>, <&amx2_out_port>,
1372 <&adx1_out1_port>, <&adx1_out2_port>,
1373 <&adx1_out3_port>, <&adx1_out4_port>,
1374 <&adx2_out1_port>, <&adx2_out2_port>,
1375 <&adx2_out3_port>, <&adx2_out4_port>,
1376 <&mixer_out1_port>, <&mixer_out2_port>,
1377 <&mixer_out3_port>, <&mixer_out4_port>,
1378 <&mixer_out5_port>,
1379 <&ope1_out_port>, <&ope2_out_port>,
1380 /* I/O DAP Ports */
1381 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
1382 <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
1383
1384 label = "NVIDIA Jetson TX1 APE";
1385 };
1386 };
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