0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra194-clock.h>
0003 #include <dt-bindings/gpio/tegra194-gpio.h>
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/mailbox/tegra186-hsp.h>
0006 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
0007 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0008 #include <dt-bindings/power/tegra194-powergate.h>
0009 #include <dt-bindings/reset/tegra194-reset.h>
0010 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
0011 #include <dt-bindings/memory/tegra194-mc.h>
0012
0013 / {
0014 compatible = "nvidia,tegra194";
0015 interrupt-parent = <&gic>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 /* control backbone */
0020 bus@0 {
0021 compatible = "simple-bus";
0022 #address-cells = <1>;
0023 #size-cells = <1>;
0024 ranges = <0x0 0x0 0x0 0x40000000>;
0025
0026 apbmisc: misc@100000 {
0027 compatible = "nvidia,tegra194-misc";
0028 reg = <0x00100000 0xf000>,
0029 <0x0010f000 0x1000>;
0030 };
0031
0032 gpio: gpio@2200000 {
0033 compatible = "nvidia,tegra194-gpio";
0034 reg-names = "security", "gpio";
0035 reg = <0x2200000 0x10000>,
0036 <0x2210000 0x10000>;
0037 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
0038 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
0039 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
0040 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
0041 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
0042 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
0043 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
0044 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
0045 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
0046 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
0047 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
0048 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
0049 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
0050 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
0051 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
0052 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
0053 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
0054 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
0055 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
0056 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
0057 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
0058 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
0059 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
0060 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
0061 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
0062 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
0063 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
0064 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
0065 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
0066 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
0067 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
0070 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
0072 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
0073 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
0074 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
0075 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
0076 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
0077 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
0078 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
0079 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
0080 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
0085 #interrupt-cells = <2>;
0086 interrupt-controller;
0087 #gpio-cells = <2>;
0088 gpio-controller;
0089 };
0090
0091 cbb-noc@2300000 {
0092 compatible = "nvidia,tegra194-cbb-noc";
0093 reg = <0x02300000 0x1000>;
0094 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
0096 nvidia,axi2apb = <&axi2apb>;
0097 nvidia,apbmisc = <&apbmisc>;
0098 status = "okay";
0099 };
0100
0101 axi2apb: axi2apb@2390000 {
0102 compatible = "nvidia,tegra194-axi2apb";
0103 reg = <0x2390000 0x1000>,
0104 <0x23a0000 0x1000>,
0105 <0x23b0000 0x1000>,
0106 <0x23c0000 0x1000>,
0107 <0x23d0000 0x1000>,
0108 <0x23e0000 0x1000>;
0109 status = "okay";
0110 };
0111
0112 ethernet@2490000 {
0113 compatible = "nvidia,tegra194-eqos",
0114 "nvidia,tegra186-eqos",
0115 "snps,dwc-qos-ethernet-4.10";
0116 reg = <0x02490000 0x10000>;
0117 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0118 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
0119 <&bpmp TEGRA194_CLK_EQOS_AXI>,
0120 <&bpmp TEGRA194_CLK_EQOS_RX>,
0121 <&bpmp TEGRA194_CLK_EQOS_TX>,
0122 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
0123 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
0124 resets = <&bpmp TEGRA194_RESET_EQOS>;
0125 reset-names = "eqos";
0126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
0127 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
0128 interconnect-names = "dma-mem", "write";
0129 iommus = <&smmu TEGRA194_SID_EQOS>;
0130 status = "disabled";
0131
0132 snps,write-requests = <1>;
0133 snps,read-requests = <3>;
0134 snps,burst-map = <0x7>;
0135 snps,txpbl = <16>;
0136 snps,rxpbl = <8>;
0137 };
0138
0139 gpcdma: dma-controller@2600000 {
0140 compatible = "nvidia,tegra194-gpcdma",
0141 "nvidia,tegra186-gpcdma";
0142 reg = <0x2600000 0x210000>;
0143 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
0144 reset-names = "gpcdma";
0145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0159 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0160 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
0162 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
0163 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
0164 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0166 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0167 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0168 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0169 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0170 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0173 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0175 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0176 #dma-cells = <1>;
0177 iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
0178 dma-coherent;
0179 status = "okay";
0180 };
0181
0182 aconnect@2900000 {
0183 compatible = "nvidia,tegra194-aconnect",
0184 "nvidia,tegra210-aconnect";
0185 clocks = <&bpmp TEGRA194_CLK_APE>,
0186 <&bpmp TEGRA194_CLK_APB2APE>;
0187 clock-names = "ape", "apb2ape";
0188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
0189 #address-cells = <1>;
0190 #size-cells = <1>;
0191 ranges = <0x02900000 0x02900000 0x200000>;
0192 status = "disabled";
0193
0194 adma: dma-controller@2930000 {
0195 compatible = "nvidia,tegra194-adma",
0196 "nvidia,tegra186-adma";
0197 reg = <0x02930000 0x20000>;
0198 interrupt-parent = <&agic>;
0199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0200 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0201 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0202 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0203 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0204 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0206 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0208 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0209 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0213 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0214 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0217 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0219 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0221 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0222 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0223 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0224 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0226 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0227 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0228 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0229 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0230 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0231 #dma-cells = <1>;
0232 clocks = <&bpmp TEGRA194_CLK_AHUB>;
0233 clock-names = "d_audio";
0234 status = "disabled";
0235 };
0236
0237 agic: interrupt-controller@2a40000 {
0238 compatible = "nvidia,tegra194-agic",
0239 "nvidia,tegra210-agic";
0240 #interrupt-cells = <3>;
0241 interrupt-controller;
0242 reg = <0x02a41000 0x1000>,
0243 <0x02a42000 0x2000>;
0244 interrupts = <GIC_SPI 145
0245 (GIC_CPU_MASK_SIMPLE(4) |
0246 IRQ_TYPE_LEVEL_HIGH)>;
0247 clocks = <&bpmp TEGRA194_CLK_APE>;
0248 clock-names = "clk";
0249 status = "disabled";
0250 };
0251
0252 tegra_ahub: ahub@2900800 {
0253 compatible = "nvidia,tegra194-ahub",
0254 "nvidia,tegra186-ahub";
0255 reg = <0x02900800 0x800>;
0256 clocks = <&bpmp TEGRA194_CLK_AHUB>;
0257 clock-names = "ahub";
0258 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
0259 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0260 #address-cells = <1>;
0261 #size-cells = <1>;
0262 ranges = <0x02900800 0x02900800 0x11800>;
0263 status = "disabled";
0264
0265 tegra_admaif: admaif@290f000 {
0266 compatible = "nvidia,tegra194-admaif",
0267 "nvidia,tegra186-admaif";
0268 reg = <0x0290f000 0x1000>;
0269 dmas = <&adma 1>, <&adma 1>,
0270 <&adma 2>, <&adma 2>,
0271 <&adma 3>, <&adma 3>,
0272 <&adma 4>, <&adma 4>,
0273 <&adma 5>, <&adma 5>,
0274 <&adma 6>, <&adma 6>,
0275 <&adma 7>, <&adma 7>,
0276 <&adma 8>, <&adma 8>,
0277 <&adma 9>, <&adma 9>,
0278 <&adma 10>, <&adma 10>,
0279 <&adma 11>, <&adma 11>,
0280 <&adma 12>, <&adma 12>,
0281 <&adma 13>, <&adma 13>,
0282 <&adma 14>, <&adma 14>,
0283 <&adma 15>, <&adma 15>,
0284 <&adma 16>, <&adma 16>,
0285 <&adma 17>, <&adma 17>,
0286 <&adma 18>, <&adma 18>,
0287 <&adma 19>, <&adma 19>,
0288 <&adma 20>, <&adma 20>;
0289 dma-names = "rx1", "tx1",
0290 "rx2", "tx2",
0291 "rx3", "tx3",
0292 "rx4", "tx4",
0293 "rx5", "tx5",
0294 "rx6", "tx6",
0295 "rx7", "tx7",
0296 "rx8", "tx8",
0297 "rx9", "tx9",
0298 "rx10", "tx10",
0299 "rx11", "tx11",
0300 "rx12", "tx12",
0301 "rx13", "tx13",
0302 "rx14", "tx14",
0303 "rx15", "tx15",
0304 "rx16", "tx16",
0305 "rx17", "tx17",
0306 "rx18", "tx18",
0307 "rx19", "tx19",
0308 "rx20", "tx20";
0309 status = "disabled";
0310 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
0311 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
0312 interconnect-names = "dma-mem", "write";
0313 iommus = <&smmu TEGRA194_SID_APE>;
0314 };
0315
0316 tegra_i2s1: i2s@2901000 {
0317 compatible = "nvidia,tegra194-i2s",
0318 "nvidia,tegra210-i2s";
0319 reg = <0x2901000 0x100>;
0320 clocks = <&bpmp TEGRA194_CLK_I2S1>,
0321 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
0322 clock-names = "i2s", "sync_input";
0323 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
0324 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0325 assigned-clock-rates = <1536000>;
0326 sound-name-prefix = "I2S1";
0327 status = "disabled";
0328 };
0329
0330 tegra_i2s2: i2s@2901100 {
0331 compatible = "nvidia,tegra194-i2s",
0332 "nvidia,tegra210-i2s";
0333 reg = <0x2901100 0x100>;
0334 clocks = <&bpmp TEGRA194_CLK_I2S2>,
0335 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
0336 clock-names = "i2s", "sync_input";
0337 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
0338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0339 assigned-clock-rates = <1536000>;
0340 sound-name-prefix = "I2S2";
0341 status = "disabled";
0342 };
0343
0344 tegra_i2s3: i2s@2901200 {
0345 compatible = "nvidia,tegra194-i2s",
0346 "nvidia,tegra210-i2s";
0347 reg = <0x2901200 0x100>;
0348 clocks = <&bpmp TEGRA194_CLK_I2S3>,
0349 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
0350 clock-names = "i2s", "sync_input";
0351 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
0352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0353 assigned-clock-rates = <1536000>;
0354 sound-name-prefix = "I2S3";
0355 status = "disabled";
0356 };
0357
0358 tegra_i2s4: i2s@2901300 {
0359 compatible = "nvidia,tegra194-i2s",
0360 "nvidia,tegra210-i2s";
0361 reg = <0x2901300 0x100>;
0362 clocks = <&bpmp TEGRA194_CLK_I2S4>,
0363 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
0364 clock-names = "i2s", "sync_input";
0365 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
0366 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0367 assigned-clock-rates = <1536000>;
0368 sound-name-prefix = "I2S4";
0369 status = "disabled";
0370 };
0371
0372 tegra_i2s5: i2s@2901400 {
0373 compatible = "nvidia,tegra194-i2s",
0374 "nvidia,tegra210-i2s";
0375 reg = <0x2901400 0x100>;
0376 clocks = <&bpmp TEGRA194_CLK_I2S5>,
0377 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
0378 clock-names = "i2s", "sync_input";
0379 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
0380 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0381 assigned-clock-rates = <1536000>;
0382 sound-name-prefix = "I2S5";
0383 status = "disabled";
0384 };
0385
0386 tegra_i2s6: i2s@2901500 {
0387 compatible = "nvidia,tegra194-i2s",
0388 "nvidia,tegra210-i2s";
0389 reg = <0x2901500 0x100>;
0390 clocks = <&bpmp TEGRA194_CLK_I2S6>,
0391 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
0392 clock-names = "i2s", "sync_input";
0393 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
0394 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0395 assigned-clock-rates = <1536000>;
0396 sound-name-prefix = "I2S6";
0397 status = "disabled";
0398 };
0399
0400 tegra_dmic1: dmic@2904000 {
0401 compatible = "nvidia,tegra194-dmic",
0402 "nvidia,tegra210-dmic";
0403 reg = <0x2904000 0x100>;
0404 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
0405 clock-names = "dmic";
0406 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
0407 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0408 assigned-clock-rates = <3072000>;
0409 sound-name-prefix = "DMIC1";
0410 status = "disabled";
0411 };
0412
0413 tegra_dmic2: dmic@2904100 {
0414 compatible = "nvidia,tegra194-dmic",
0415 "nvidia,tegra210-dmic";
0416 reg = <0x2904100 0x100>;
0417 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
0418 clock-names = "dmic";
0419 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
0420 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0421 assigned-clock-rates = <3072000>;
0422 sound-name-prefix = "DMIC2";
0423 status = "disabled";
0424 };
0425
0426 tegra_dmic3: dmic@2904200 {
0427 compatible = "nvidia,tegra194-dmic",
0428 "nvidia,tegra210-dmic";
0429 reg = <0x2904200 0x100>;
0430 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
0431 clock-names = "dmic";
0432 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
0433 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0434 assigned-clock-rates = <3072000>;
0435 sound-name-prefix = "DMIC3";
0436 status = "disabled";
0437 };
0438
0439 tegra_dmic4: dmic@2904300 {
0440 compatible = "nvidia,tegra194-dmic",
0441 "nvidia,tegra210-dmic";
0442 reg = <0x2904300 0x100>;
0443 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
0444 clock-names = "dmic";
0445 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
0446 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0447 assigned-clock-rates = <3072000>;
0448 sound-name-prefix = "DMIC4";
0449 status = "disabled";
0450 };
0451
0452 tegra_dspk1: dspk@2905000 {
0453 compatible = "nvidia,tegra194-dspk",
0454 "nvidia,tegra186-dspk";
0455 reg = <0x2905000 0x100>;
0456 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
0457 clock-names = "dspk";
0458 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
0459 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0460 assigned-clock-rates = <12288000>;
0461 sound-name-prefix = "DSPK1";
0462 status = "disabled";
0463 };
0464
0465 tegra_dspk2: dspk@2905100 {
0466 compatible = "nvidia,tegra194-dspk",
0467 "nvidia,tegra186-dspk";
0468 reg = <0x2905100 0x100>;
0469 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
0470 clock-names = "dspk";
0471 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
0472 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
0473 assigned-clock-rates = <12288000>;
0474 sound-name-prefix = "DSPK2";
0475 status = "disabled";
0476 };
0477
0478 tegra_sfc1: sfc@2902000 {
0479 compatible = "nvidia,tegra194-sfc",
0480 "nvidia,tegra210-sfc";
0481 reg = <0x2902000 0x200>;
0482 sound-name-prefix = "SFC1";
0483 status = "disabled";
0484 };
0485
0486 tegra_sfc2: sfc@2902200 {
0487 compatible = "nvidia,tegra194-sfc",
0488 "nvidia,tegra210-sfc";
0489 reg = <0x2902200 0x200>;
0490 sound-name-prefix = "SFC2";
0491 status = "disabled";
0492 };
0493
0494 tegra_sfc3: sfc@2902400 {
0495 compatible = "nvidia,tegra194-sfc",
0496 "nvidia,tegra210-sfc";
0497 reg = <0x2902400 0x200>;
0498 sound-name-prefix = "SFC3";
0499 status = "disabled";
0500 };
0501
0502 tegra_sfc4: sfc@2902600 {
0503 compatible = "nvidia,tegra194-sfc",
0504 "nvidia,tegra210-sfc";
0505 reg = <0x2902600 0x200>;
0506 sound-name-prefix = "SFC4";
0507 status = "disabled";
0508 };
0509
0510 tegra_mvc1: mvc@290a000 {
0511 compatible = "nvidia,tegra194-mvc",
0512 "nvidia,tegra210-mvc";
0513 reg = <0x290a000 0x200>;
0514 sound-name-prefix = "MVC1";
0515 status = "disabled";
0516 };
0517
0518 tegra_mvc2: mvc@290a200 {
0519 compatible = "nvidia,tegra194-mvc",
0520 "nvidia,tegra210-mvc";
0521 reg = <0x290a200 0x200>;
0522 sound-name-prefix = "MVC2";
0523 status = "disabled";
0524 };
0525
0526 tegra_amx1: amx@2903000 {
0527 compatible = "nvidia,tegra194-amx";
0528 reg = <0x2903000 0x100>;
0529 sound-name-prefix = "AMX1";
0530 status = "disabled";
0531 };
0532
0533 tegra_amx2: amx@2903100 {
0534 compatible = "nvidia,tegra194-amx";
0535 reg = <0x2903100 0x100>;
0536 sound-name-prefix = "AMX2";
0537 status = "disabled";
0538 };
0539
0540 tegra_amx3: amx@2903200 {
0541 compatible = "nvidia,tegra194-amx";
0542 reg = <0x2903200 0x100>;
0543 sound-name-prefix = "AMX3";
0544 status = "disabled";
0545 };
0546
0547 tegra_amx4: amx@2903300 {
0548 compatible = "nvidia,tegra194-amx";
0549 reg = <0x2903300 0x100>;
0550 sound-name-prefix = "AMX4";
0551 status = "disabled";
0552 };
0553
0554 tegra_adx1: adx@2903800 {
0555 compatible = "nvidia,tegra194-adx",
0556 "nvidia,tegra210-adx";
0557 reg = <0x2903800 0x100>;
0558 sound-name-prefix = "ADX1";
0559 status = "disabled";
0560 };
0561
0562 tegra_adx2: adx@2903900 {
0563 compatible = "nvidia,tegra194-adx",
0564 "nvidia,tegra210-adx";
0565 reg = <0x2903900 0x100>;
0566 sound-name-prefix = "ADX2";
0567 status = "disabled";
0568 };
0569
0570 tegra_adx3: adx@2903a00 {
0571 compatible = "nvidia,tegra194-adx",
0572 "nvidia,tegra210-adx";
0573 reg = <0x2903a00 0x100>;
0574 sound-name-prefix = "ADX3";
0575 status = "disabled";
0576 };
0577
0578 tegra_adx4: adx@2903b00 {
0579 compatible = "nvidia,tegra194-adx",
0580 "nvidia,tegra210-adx";
0581 reg = <0x2903b00 0x100>;
0582 sound-name-prefix = "ADX4";
0583 status = "disabled";
0584 };
0585
0586 tegra_ope1: processing-engine@2908000 {
0587 compatible = "nvidia,tegra194-ope",
0588 "nvidia,tegra210-ope";
0589 reg = <0x2908000 0x100>;
0590 #address-cells = <1>;
0591 #size-cells = <1>;
0592 ranges;
0593 sound-name-prefix = "OPE1";
0594 status = "disabled";
0595
0596 equalizer@2908100 {
0597 compatible = "nvidia,tegra194-peq",
0598 "nvidia,tegra210-peq";
0599 reg = <0x2908100 0x100>;
0600 };
0601
0602 dynamic-range-compressor@2908200 {
0603 compatible = "nvidia,tegra194-mbdrc",
0604 "nvidia,tegra210-mbdrc";
0605 reg = <0x2908200 0x200>;
0606 };
0607 };
0608
0609 tegra_amixer: amixer@290bb00 {
0610 compatible = "nvidia,tegra194-amixer",
0611 "nvidia,tegra210-amixer";
0612 reg = <0x290bb00 0x800>;
0613 sound-name-prefix = "MIXER1";
0614 status = "disabled";
0615 };
0616
0617 tegra_asrc: asrc@2910000 {
0618 compatible = "nvidia,tegra194-asrc",
0619 "nvidia,tegra186-asrc";
0620 reg = <0x2910000 0x2000>;
0621 sound-name-prefix = "ASRC1";
0622 status = "disabled";
0623 };
0624 };
0625 };
0626
0627 pinmux: pinmux@2430000 {
0628 compatible = "nvidia,tegra194-pinmux";
0629 reg = <0x2430000 0x17000>,
0630 <0xc300000 0x4000>;
0631
0632 status = "okay";
0633
0634 pex_rst_c5_out_state: pex_rst_c5_out {
0635 pex_rst {
0636 nvidia,pins = "pex_l5_rst_n_pgg1";
0637 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
0638 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0639 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
0640 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0641 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0642 };
0643 };
0644
0645 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
0646 clkreq {
0647 nvidia,pins = "pex_l5_clkreq_n_pgg0";
0648 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
0649 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0650 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
0651 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0652 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0653 };
0654 };
0655 };
0656
0657 mc: memory-controller@2c00000 {
0658 compatible = "nvidia,tegra194-mc";
0659 reg = <0x02c00000 0x10000>, /* MC-SID */
0660 <0x02c10000 0x10000>, /* MC Broadcast*/
0661 <0x02c20000 0x10000>, /* MC0 */
0662 <0x02c30000 0x10000>, /* MC1 */
0663 <0x02c40000 0x10000>, /* MC2 */
0664 <0x02c50000 0x10000>, /* MC3 */
0665 <0x02b80000 0x10000>, /* MC4 */
0666 <0x02b90000 0x10000>, /* MC5 */
0667 <0x02ba0000 0x10000>, /* MC6 */
0668 <0x02bb0000 0x10000>, /* MC7 */
0669 <0x01700000 0x10000>, /* MC8 */
0670 <0x01710000 0x10000>, /* MC9 */
0671 <0x01720000 0x10000>, /* MC10 */
0672 <0x01730000 0x10000>, /* MC11 */
0673 <0x01740000 0x10000>, /* MC12 */
0674 <0x01750000 0x10000>, /* MC13 */
0675 <0x01760000 0x10000>, /* MC14 */
0676 <0x01770000 0x10000>; /* MC15 */
0677 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
0678 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
0679 "ch11", "ch12", "ch13", "ch14", "ch15";
0680 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
0681 #interconnect-cells = <1>;
0682 status = "disabled";
0683
0684 #address-cells = <2>;
0685 #size-cells = <2>;
0686
0687 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
0688 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
0689 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
0690
0691 /*
0692 * Bit 39 of addresses passing through the memory
0693 * controller selects the XBAR format used when memory
0694 * is accessed. This is used to transparently access
0695 * memory in the XBAR format used by the discrete GPU
0696 * (bit 39 set) or Tegra (bit 39 clear).
0697 *
0698 * As a consequence, the operating system must ensure
0699 * that bit 39 is never used implicitly, for example
0700 * via an I/O virtual address mapping of an IOMMU. If
0701 * devices require access to the XBAR switch, their
0702 * drivers must set this bit explicitly.
0703 *
0704 * Limit the DMA range for memory clients to [38:0].
0705 */
0706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
0707
0708 emc: external-memory-controller@2c60000 {
0709 compatible = "nvidia,tegra194-emc";
0710 reg = <0x0 0x02c60000 0x0 0x90000>,
0711 <0x0 0x01780000 0x0 0x80000>;
0712 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
0713 clocks = <&bpmp TEGRA194_CLK_EMC>;
0714 clock-names = "emc";
0715
0716 #interconnect-cells = <0>;
0717
0718 nvidia,bpmp = <&bpmp>;
0719 };
0720 };
0721
0722 timer@3010000 {
0723 compatible = "nvidia,tegra186-timer";
0724 reg = <0x03010000 0x000e0000>;
0725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0727 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0728 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0729 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0730 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0731 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0732 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0733 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0734 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0735 status = "okay";
0736 };
0737
0738 uarta: serial@3100000 {
0739 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
0740 reg = <0x03100000 0x40>;
0741 reg-shift = <2>;
0742 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0743 clocks = <&bpmp TEGRA194_CLK_UARTA>;
0744 clock-names = "serial";
0745 resets = <&bpmp TEGRA194_RESET_UARTA>;
0746 reset-names = "serial";
0747 status = "disabled";
0748 };
0749
0750 uartb: serial@3110000 {
0751 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
0752 reg = <0x03110000 0x40>;
0753 reg-shift = <2>;
0754 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0755 clocks = <&bpmp TEGRA194_CLK_UARTB>;
0756 clock-names = "serial";
0757 resets = <&bpmp TEGRA194_RESET_UARTB>;
0758 reset-names = "serial";
0759 status = "disabled";
0760 };
0761
0762 uartd: serial@3130000 {
0763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
0764 reg = <0x03130000 0x40>;
0765 reg-shift = <2>;
0766 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0767 clocks = <&bpmp TEGRA194_CLK_UARTD>;
0768 clock-names = "serial";
0769 resets = <&bpmp TEGRA194_RESET_UARTD>;
0770 reset-names = "serial";
0771 status = "disabled";
0772 };
0773
0774 uarte: serial@3140000 {
0775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
0776 reg = <0x03140000 0x40>;
0777 reg-shift = <2>;
0778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0779 clocks = <&bpmp TEGRA194_CLK_UARTE>;
0780 clock-names = "serial";
0781 resets = <&bpmp TEGRA194_RESET_UARTE>;
0782 reset-names = "serial";
0783 status = "disabled";
0784 };
0785
0786 uartf: serial@3150000 {
0787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
0788 reg = <0x03150000 0x40>;
0789 reg-shift = <2>;
0790 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0791 clocks = <&bpmp TEGRA194_CLK_UARTF>;
0792 clock-names = "serial";
0793 resets = <&bpmp TEGRA194_RESET_UARTF>;
0794 reset-names = "serial";
0795 status = "disabled";
0796 };
0797
0798 gen1_i2c: i2c@3160000 {
0799 compatible = "nvidia,tegra194-i2c";
0800 reg = <0x03160000 0x10000>;
0801 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0802 #address-cells = <1>;
0803 #size-cells = <0>;
0804 clocks = <&bpmp TEGRA194_CLK_I2C1>;
0805 clock-names = "div-clk";
0806 resets = <&bpmp TEGRA194_RESET_I2C1>;
0807 reset-names = "i2c";
0808 status = "disabled";
0809 };
0810
0811 uarth: serial@3170000 {
0812 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
0813 reg = <0x03170000 0x40>;
0814 reg-shift = <2>;
0815 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
0816 clocks = <&bpmp TEGRA194_CLK_UARTH>;
0817 clock-names = "serial";
0818 resets = <&bpmp TEGRA194_RESET_UARTH>;
0819 reset-names = "serial";
0820 status = "disabled";
0821 };
0822
0823 cam_i2c: i2c@3180000 {
0824 compatible = "nvidia,tegra194-i2c";
0825 reg = <0x03180000 0x10000>;
0826 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0827 #address-cells = <1>;
0828 #size-cells = <0>;
0829 clocks = <&bpmp TEGRA194_CLK_I2C3>;
0830 clock-names = "div-clk";
0831 resets = <&bpmp TEGRA194_RESET_I2C3>;
0832 reset-names = "i2c";
0833 status = "disabled";
0834 };
0835
0836 /* shares pads with dpaux1 */
0837 dp_aux_ch1_i2c: i2c@3190000 {
0838 compatible = "nvidia,tegra194-i2c";
0839 reg = <0x03190000 0x10000>;
0840 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0841 #address-cells = <1>;
0842 #size-cells = <0>;
0843 clocks = <&bpmp TEGRA194_CLK_I2C4>;
0844 clock-names = "div-clk";
0845 resets = <&bpmp TEGRA194_RESET_I2C4>;
0846 reset-names = "i2c";
0847 pinctrl-0 = <&state_dpaux1_i2c>;
0848 pinctrl-1 = <&state_dpaux1_off>;
0849 pinctrl-names = "default", "idle";
0850 status = "disabled";
0851 };
0852
0853 /* shares pads with dpaux0 */
0854 dp_aux_ch0_i2c: i2c@31b0000 {
0855 compatible = "nvidia,tegra194-i2c";
0856 reg = <0x031b0000 0x10000>;
0857 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0858 #address-cells = <1>;
0859 #size-cells = <0>;
0860 clocks = <&bpmp TEGRA194_CLK_I2C6>;
0861 clock-names = "div-clk";
0862 resets = <&bpmp TEGRA194_RESET_I2C6>;
0863 reset-names = "i2c";
0864 pinctrl-0 = <&state_dpaux0_i2c>;
0865 pinctrl-1 = <&state_dpaux0_off>;
0866 pinctrl-names = "default", "idle";
0867 status = "disabled";
0868 };
0869
0870 /* shares pads with dpaux2 */
0871 dp_aux_ch2_i2c: i2c@31c0000 {
0872 compatible = "nvidia,tegra194-i2c";
0873 reg = <0x031c0000 0x10000>;
0874 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0875 #address-cells = <1>;
0876 #size-cells = <0>;
0877 clocks = <&bpmp TEGRA194_CLK_I2C7>;
0878 clock-names = "div-clk";
0879 resets = <&bpmp TEGRA194_RESET_I2C7>;
0880 reset-names = "i2c";
0881 pinctrl-0 = <&state_dpaux2_i2c>;
0882 pinctrl-1 = <&state_dpaux2_off>;
0883 pinctrl-names = "default", "idle";
0884 status = "disabled";
0885 };
0886
0887 /* shares pads with dpaux3 */
0888 dp_aux_ch3_i2c: i2c@31e0000 {
0889 compatible = "nvidia,tegra194-i2c";
0890 reg = <0x031e0000 0x10000>;
0891 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0892 #address-cells = <1>;
0893 #size-cells = <0>;
0894 clocks = <&bpmp TEGRA194_CLK_I2C9>;
0895 clock-names = "div-clk";
0896 resets = <&bpmp TEGRA194_RESET_I2C9>;
0897 reset-names = "i2c";
0898 pinctrl-0 = <&state_dpaux3_i2c>;
0899 pinctrl-1 = <&state_dpaux3_off>;
0900 pinctrl-names = "default", "idle";
0901 status = "disabled";
0902 };
0903
0904 spi@3270000 {
0905 compatible = "nvidia,tegra194-qspi";
0906 reg = <0x3270000 0x1000>;
0907 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0908 #address-cells = <1>;
0909 #size-cells = <0>;
0910 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
0911 <&bpmp TEGRA194_CLK_QSPI0_PM>;
0912 clock-names = "qspi", "qspi_out";
0913 resets = <&bpmp TEGRA194_RESET_QSPI0>;
0914 reset-names = "qspi";
0915 status = "disabled";
0916 };
0917
0918 spi@3300000 {
0919 compatible = "nvidia,tegra194-qspi";
0920 reg = <0x3300000 0x1000>;
0921 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0922 #address-cells = <1>;
0923 #size-cells = <0>;
0924 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
0925 <&bpmp TEGRA194_CLK_QSPI1_PM>;
0926 clock-names = "qspi", "qspi_out";
0927 resets = <&bpmp TEGRA194_RESET_QSPI1>;
0928 reset-names = "qspi";
0929 status = "disabled";
0930 };
0931
0932 pwm1: pwm@3280000 {
0933 compatible = "nvidia,tegra194-pwm",
0934 "nvidia,tegra186-pwm";
0935 reg = <0x3280000 0x10000>;
0936 clocks = <&bpmp TEGRA194_CLK_PWM1>;
0937 clock-names = "pwm";
0938 resets = <&bpmp TEGRA194_RESET_PWM1>;
0939 reset-names = "pwm";
0940 status = "disabled";
0941 #pwm-cells = <2>;
0942 };
0943
0944 pwm2: pwm@3290000 {
0945 compatible = "nvidia,tegra194-pwm",
0946 "nvidia,tegra186-pwm";
0947 reg = <0x3290000 0x10000>;
0948 clocks = <&bpmp TEGRA194_CLK_PWM2>;
0949 clock-names = "pwm";
0950 resets = <&bpmp TEGRA194_RESET_PWM2>;
0951 reset-names = "pwm";
0952 status = "disabled";
0953 #pwm-cells = <2>;
0954 };
0955
0956 pwm3: pwm@32a0000 {
0957 compatible = "nvidia,tegra194-pwm",
0958 "nvidia,tegra186-pwm";
0959 reg = <0x32a0000 0x10000>;
0960 clocks = <&bpmp TEGRA194_CLK_PWM3>;
0961 clock-names = "pwm";
0962 resets = <&bpmp TEGRA194_RESET_PWM3>;
0963 reset-names = "pwm";
0964 status = "disabled";
0965 #pwm-cells = <2>;
0966 };
0967
0968 pwm5: pwm@32c0000 {
0969 compatible = "nvidia,tegra194-pwm",
0970 "nvidia,tegra186-pwm";
0971 reg = <0x32c0000 0x10000>;
0972 clocks = <&bpmp TEGRA194_CLK_PWM5>;
0973 clock-names = "pwm";
0974 resets = <&bpmp TEGRA194_RESET_PWM5>;
0975 reset-names = "pwm";
0976 status = "disabled";
0977 #pwm-cells = <2>;
0978 };
0979
0980 pwm6: pwm@32d0000 {
0981 compatible = "nvidia,tegra194-pwm",
0982 "nvidia,tegra186-pwm";
0983 reg = <0x32d0000 0x10000>;
0984 clocks = <&bpmp TEGRA194_CLK_PWM6>;
0985 clock-names = "pwm";
0986 resets = <&bpmp TEGRA194_RESET_PWM6>;
0987 reset-names = "pwm";
0988 status = "disabled";
0989 #pwm-cells = <2>;
0990 };
0991
0992 pwm7: pwm@32e0000 {
0993 compatible = "nvidia,tegra194-pwm",
0994 "nvidia,tegra186-pwm";
0995 reg = <0x32e0000 0x10000>;
0996 clocks = <&bpmp TEGRA194_CLK_PWM7>;
0997 clock-names = "pwm";
0998 resets = <&bpmp TEGRA194_RESET_PWM7>;
0999 reset-names = "pwm";
1000 status = "disabled";
1001 #pwm-cells = <2>;
1002 };
1003
1004 pwm8: pwm@32f0000 {
1005 compatible = "nvidia,tegra194-pwm",
1006 "nvidia,tegra186-pwm";
1007 reg = <0x32f0000 0x10000>;
1008 clocks = <&bpmp TEGRA194_CLK_PWM8>;
1009 clock-names = "pwm";
1010 resets = <&bpmp TEGRA194_RESET_PWM8>;
1011 reset-names = "pwm";
1012 status = "disabled";
1013 #pwm-cells = <2>;
1014 };
1015
1016 sdmmc1: mmc@3400000 {
1017 compatible = "nvidia,tegra194-sdhci";
1018 reg = <0x03400000 0x10000>;
1019 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1021 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1022 clock-names = "sdhci", "tmclk";
1023 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1024 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1025 assigned-clock-parents =
1026 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1027 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1028 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1029 reset-names = "sdhci";
1030 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1031 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1032 interconnect-names = "dma-mem", "write";
1033 iommus = <&smmu TEGRA194_SID_SDMMC1>;
1034 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1035 pinctrl-0 = <&sdmmc1_3v3>;
1036 pinctrl-1 = <&sdmmc1_1v8>;
1037 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1038 <0x07>;
1039 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1040 <0x07>;
1041 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1042 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1043 <0x07>;
1044 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1045 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1046 nvidia,default-tap = <0x9>;
1047 nvidia,default-trim = <0x5>;
1048 sd-uhs-sdr25;
1049 sd-uhs-sdr50;
1050 sd-uhs-ddr50;
1051 sd-uhs-sdr104;
1052 status = "disabled";
1053 };
1054
1055 sdmmc3: mmc@3440000 {
1056 compatible = "nvidia,tegra194-sdhci";
1057 reg = <0x03440000 0x10000>;
1058 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1060 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1061 clock-names = "sdhci", "tmclk";
1062 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1063 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1064 assigned-clock-parents =
1065 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1066 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1067 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1068 reset-names = "sdhci";
1069 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1070 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1071 interconnect-names = "dma-mem", "write";
1072 iommus = <&smmu TEGRA194_SID_SDMMC3>;
1073 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1074 pinctrl-0 = <&sdmmc3_3v3>;
1075 pinctrl-1 = <&sdmmc3_1v8>;
1076 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1077 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1078 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1079 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1080 <0x07>;
1081 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1082 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1083 <0x07>;
1084 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1085 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1086 nvidia,default-tap = <0x9>;
1087 nvidia,default-trim = <0x5>;
1088 sd-uhs-sdr25;
1089 sd-uhs-sdr50;
1090 sd-uhs-ddr50;
1091 sd-uhs-sdr104;
1092 status = "disabled";
1093 };
1094
1095 sdmmc4: mmc@3460000 {
1096 compatible = "nvidia,tegra194-sdhci";
1097 reg = <0x03460000 0x10000>;
1098 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1100 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1101 clock-names = "sdhci", "tmclk";
1102 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1103 <&bpmp TEGRA194_CLK_PLLC4>;
1104 assigned-clock-parents =
1105 <&bpmp TEGRA194_CLK_PLLC4>;
1106 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1107 reset-names = "sdhci";
1108 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1109 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1110 interconnect-names = "dma-mem", "write";
1111 iommus = <&smmu TEGRA194_SID_SDMMC4>;
1112 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1113 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1114 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1115 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1116 <0x0a>;
1117 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1118 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1119 <0x0a>;
1120 nvidia,default-tap = <0x8>;
1121 nvidia,default-trim = <0x14>;
1122 nvidia,dqs-trim = <40>;
1123 cap-mmc-highspeed;
1124 mmc-ddr-1_8v;
1125 mmc-hs200-1_8v;
1126 mmc-hs400-1_8v;
1127 mmc-hs400-enhanced-strobe;
1128 supports-cqe;
1129 status = "disabled";
1130 };
1131
1132 hda@3510000 {
1133 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
1134 reg = <0x3510000 0x10000>;
1135 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&bpmp TEGRA194_CLK_HDA>,
1137 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1138 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1139 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1140 resets = <&bpmp TEGRA194_RESET_HDA>,
1141 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1142 reset-names = "hda", "hda2hdmi";
1143 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1144 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1145 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1146 interconnect-names = "dma-mem", "write";
1147 iommus = <&smmu TEGRA194_SID_HDA>;
1148 status = "disabled";
1149 };
1150
1151 xusb_padctl: padctl@3520000 {
1152 compatible = "nvidia,tegra194-xusb-padctl";
1153 reg = <0x03520000 0x1000>,
1154 <0x03540000 0x1000>;
1155 reg-names = "padctl", "ao";
1156 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1157
1158 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1159 reset-names = "padctl";
1160
1161 status = "disabled";
1162
1163 pads {
1164 usb2 {
1165 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1166 clock-names = "trk";
1167
1168 lanes {
1169 usb2-0 {
1170 nvidia,function = "xusb";
1171 status = "disabled";
1172 #phy-cells = <0>;
1173 };
1174
1175 usb2-1 {
1176 nvidia,function = "xusb";
1177 status = "disabled";
1178 #phy-cells = <0>;
1179 };
1180
1181 usb2-2 {
1182 nvidia,function = "xusb";
1183 status = "disabled";
1184 #phy-cells = <0>;
1185 };
1186
1187 usb2-3 {
1188 nvidia,function = "xusb";
1189 status = "disabled";
1190 #phy-cells = <0>;
1191 };
1192 };
1193 };
1194
1195 usb3 {
1196 lanes {
1197 usb3-0 {
1198 nvidia,function = "xusb";
1199 status = "disabled";
1200 #phy-cells = <0>;
1201 };
1202
1203 usb3-1 {
1204 nvidia,function = "xusb";
1205 status = "disabled";
1206 #phy-cells = <0>;
1207 };
1208
1209 usb3-2 {
1210 nvidia,function = "xusb";
1211 status = "disabled";
1212 #phy-cells = <0>;
1213 };
1214
1215 usb3-3 {
1216 nvidia,function = "xusb";
1217 status = "disabled";
1218 #phy-cells = <0>;
1219 };
1220 };
1221 };
1222 };
1223
1224 ports {
1225 usb2-0 {
1226 status = "disabled";
1227 };
1228
1229 usb2-1 {
1230 status = "disabled";
1231 };
1232
1233 usb2-2 {
1234 status = "disabled";
1235 };
1236
1237 usb2-3 {
1238 status = "disabled";
1239 };
1240
1241 usb3-0 {
1242 status = "disabled";
1243 };
1244
1245 usb3-1 {
1246 status = "disabled";
1247 };
1248
1249 usb3-2 {
1250 status = "disabled";
1251 };
1252
1253 usb3-3 {
1254 status = "disabled";
1255 };
1256 };
1257 };
1258
1259 usb@3550000 {
1260 compatible = "nvidia,tegra194-xudc";
1261 reg = <0x03550000 0x8000>,
1262 <0x03558000 0x1000>;
1263 reg-names = "base", "fpci";
1264 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1266 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1267 <&bpmp TEGRA194_CLK_XUSB_SS>,
1268 <&bpmp TEGRA194_CLK_XUSB_FS>;
1269 clock-names = "dev", "ss", "ss_src", "fs_src";
1270 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1271 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1272 interconnect-names = "dma-mem", "write";
1273 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1274 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1275 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1276 power-domain-names = "dev", "ss";
1277 nvidia,xusb-padctl = <&xusb_padctl>;
1278 status = "disabled";
1279 };
1280
1281 usb@3610000 {
1282 compatible = "nvidia,tegra194-xusb";
1283 reg = <0x03610000 0x40000>,
1284 <0x03600000 0x10000>;
1285 reg-names = "hcd", "fpci";
1286
1287 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1289
1290 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1291 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1292 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1293 <&bpmp TEGRA194_CLK_XUSB_SS>,
1294 <&bpmp TEGRA194_CLK_CLK_M>,
1295 <&bpmp TEGRA194_CLK_XUSB_FS>,
1296 <&bpmp TEGRA194_CLK_UTMIPLL>,
1297 <&bpmp TEGRA194_CLK_CLK_M>,
1298 <&bpmp TEGRA194_CLK_PLLE>;
1299 clock-names = "xusb_host", "xusb_falcon_src",
1300 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1301 "xusb_fs_src", "pll_u_480m", "clk_m",
1302 "pll_e";
1303 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1304 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1305 interconnect-names = "dma-mem", "write";
1306 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1307
1308 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1309 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1310 power-domain-names = "xusb_host", "xusb_ss";
1311
1312 nvidia,xusb-padctl = <&xusb_padctl>;
1313 status = "disabled";
1314 };
1315
1316 fuse@3820000 {
1317 compatible = "nvidia,tegra194-efuse";
1318 reg = <0x03820000 0x10000>;
1319 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1320 clock-names = "fuse";
1321 };
1322
1323 gic: interrupt-controller@3881000 {
1324 compatible = "arm,gic-400";
1325 #interrupt-cells = <3>;
1326 interrupt-controller;
1327 reg = <0x03881000 0x1000>,
1328 <0x03882000 0x2000>,
1329 <0x03884000 0x2000>,
1330 <0x03886000 0x2000>;
1331 interrupts = <GIC_PPI 9
1332 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1333 interrupt-parent = <&gic>;
1334 };
1335
1336 cec@3960000 {
1337 compatible = "nvidia,tegra194-cec";
1338 reg = <0x03960000 0x10000>;
1339 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&bpmp TEGRA194_CLK_CEC>;
1341 clock-names = "cec";
1342 status = "disabled";
1343 };
1344
1345 hsp_top0: hsp@3c00000 {
1346 compatible = "nvidia,tegra194-hsp";
1347 reg = <0x03c00000 0xa0000>;
1348 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1357 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1358 "shared3", "shared4", "shared5", "shared6",
1359 "shared7";
1360 #mbox-cells = <2>;
1361 };
1362
1363 p2u_hsio_0: phy@3e10000 {
1364 compatible = "nvidia,tegra194-p2u";
1365 reg = <0x03e10000 0x10000>;
1366 reg-names = "ctl";
1367
1368 #phy-cells = <0>;
1369 };
1370
1371 p2u_hsio_1: phy@3e20000 {
1372 compatible = "nvidia,tegra194-p2u";
1373 reg = <0x03e20000 0x10000>;
1374 reg-names = "ctl";
1375
1376 #phy-cells = <0>;
1377 };
1378
1379 p2u_hsio_2: phy@3e30000 {
1380 compatible = "nvidia,tegra194-p2u";
1381 reg = <0x03e30000 0x10000>;
1382 reg-names = "ctl";
1383
1384 #phy-cells = <0>;
1385 };
1386
1387 p2u_hsio_3: phy@3e40000 {
1388 compatible = "nvidia,tegra194-p2u";
1389 reg = <0x03e40000 0x10000>;
1390 reg-names = "ctl";
1391
1392 #phy-cells = <0>;
1393 };
1394
1395 p2u_hsio_4: phy@3e50000 {
1396 compatible = "nvidia,tegra194-p2u";
1397 reg = <0x03e50000 0x10000>;
1398 reg-names = "ctl";
1399
1400 #phy-cells = <0>;
1401 };
1402
1403 p2u_hsio_5: phy@3e60000 {
1404 compatible = "nvidia,tegra194-p2u";
1405 reg = <0x03e60000 0x10000>;
1406 reg-names = "ctl";
1407
1408 #phy-cells = <0>;
1409 };
1410
1411 p2u_hsio_6: phy@3e70000 {
1412 compatible = "nvidia,tegra194-p2u";
1413 reg = <0x03e70000 0x10000>;
1414 reg-names = "ctl";
1415
1416 #phy-cells = <0>;
1417 };
1418
1419 p2u_hsio_7: phy@3e80000 {
1420 compatible = "nvidia,tegra194-p2u";
1421 reg = <0x03e80000 0x10000>;
1422 reg-names = "ctl";
1423
1424 #phy-cells = <0>;
1425 };
1426
1427 p2u_hsio_8: phy@3e90000 {
1428 compatible = "nvidia,tegra194-p2u";
1429 reg = <0x03e90000 0x10000>;
1430 reg-names = "ctl";
1431
1432 #phy-cells = <0>;
1433 };
1434
1435 p2u_hsio_9: phy@3ea0000 {
1436 compatible = "nvidia,tegra194-p2u";
1437 reg = <0x03ea0000 0x10000>;
1438 reg-names = "ctl";
1439
1440 #phy-cells = <0>;
1441 };
1442
1443 p2u_nvhs_0: phy@3eb0000 {
1444 compatible = "nvidia,tegra194-p2u";
1445 reg = <0x03eb0000 0x10000>;
1446 reg-names = "ctl";
1447
1448 #phy-cells = <0>;
1449 };
1450
1451 p2u_nvhs_1: phy@3ec0000 {
1452 compatible = "nvidia,tegra194-p2u";
1453 reg = <0x03ec0000 0x10000>;
1454 reg-names = "ctl";
1455
1456 #phy-cells = <0>;
1457 };
1458
1459 p2u_nvhs_2: phy@3ed0000 {
1460 compatible = "nvidia,tegra194-p2u";
1461 reg = <0x03ed0000 0x10000>;
1462 reg-names = "ctl";
1463
1464 #phy-cells = <0>;
1465 };
1466
1467 p2u_nvhs_3: phy@3ee0000 {
1468 compatible = "nvidia,tegra194-p2u";
1469 reg = <0x03ee0000 0x10000>;
1470 reg-names = "ctl";
1471
1472 #phy-cells = <0>;
1473 };
1474
1475 p2u_nvhs_4: phy@3ef0000 {
1476 compatible = "nvidia,tegra194-p2u";
1477 reg = <0x03ef0000 0x10000>;
1478 reg-names = "ctl";
1479
1480 #phy-cells = <0>;
1481 };
1482
1483 p2u_nvhs_5: phy@3f00000 {
1484 compatible = "nvidia,tegra194-p2u";
1485 reg = <0x03f00000 0x10000>;
1486 reg-names = "ctl";
1487
1488 #phy-cells = <0>;
1489 };
1490
1491 p2u_nvhs_6: phy@3f10000 {
1492 compatible = "nvidia,tegra194-p2u";
1493 reg = <0x03f10000 0x10000>;
1494 reg-names = "ctl";
1495
1496 #phy-cells = <0>;
1497 };
1498
1499 p2u_nvhs_7: phy@3f20000 {
1500 compatible = "nvidia,tegra194-p2u";
1501 reg = <0x03f20000 0x10000>;
1502 reg-names = "ctl";
1503
1504 #phy-cells = <0>;
1505 };
1506
1507 p2u_hsio_10: phy@3f30000 {
1508 compatible = "nvidia,tegra194-p2u";
1509 reg = <0x03f30000 0x10000>;
1510 reg-names = "ctl";
1511
1512 #phy-cells = <0>;
1513 };
1514
1515 p2u_hsio_11: phy@3f40000 {
1516 compatible = "nvidia,tegra194-p2u";
1517 reg = <0x03f40000 0x10000>;
1518 reg-names = "ctl";
1519
1520 #phy-cells = <0>;
1521 };
1522
1523 sce-noc@b600000 {
1524 compatible = "nvidia,tegra194-sce-noc";
1525 reg = <0xb600000 0x1000>;
1526 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1528 nvidia,axi2apb = <&axi2apb>;
1529 nvidia,apbmisc = <&apbmisc>;
1530 status = "okay";
1531 };
1532
1533 rce-noc@be00000 {
1534 compatible = "nvidia,tegra194-rce-noc";
1535 reg = <0xbe00000 0x1000>;
1536 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1538 nvidia,axi2apb = <&axi2apb>;
1539 nvidia,apbmisc = <&apbmisc>;
1540 status = "okay";
1541 };
1542
1543 hsp_aon: hsp@c150000 {
1544 compatible = "nvidia,tegra194-hsp";
1545 reg = <0x0c150000 0x90000>;
1546 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1550 /*
1551 * Shared interrupt 0 is routed only to AON/SPE, so
1552 * we only have 4 shared interrupts for the CCPLEX.
1553 */
1554 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1555 #mbox-cells = <2>;
1556 };
1557
1558 gen2_i2c: i2c@c240000 {
1559 compatible = "nvidia,tegra194-i2c";
1560 reg = <0x0c240000 0x10000>;
1561 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1564 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1565 clock-names = "div-clk";
1566 resets = <&bpmp TEGRA194_RESET_I2C2>;
1567 reset-names = "i2c";
1568 status = "disabled";
1569 };
1570
1571 gen8_i2c: i2c@c250000 {
1572 compatible = "nvidia,tegra194-i2c";
1573 reg = <0x0c250000 0x10000>;
1574 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1577 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1578 clock-names = "div-clk";
1579 resets = <&bpmp TEGRA194_RESET_I2C8>;
1580 reset-names = "i2c";
1581 status = "disabled";
1582 };
1583
1584 uartc: serial@c280000 {
1585 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1586 reg = <0x0c280000 0x40>;
1587 reg-shift = <2>;
1588 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1589 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1590 clock-names = "serial";
1591 resets = <&bpmp TEGRA194_RESET_UARTC>;
1592 reset-names = "serial";
1593 status = "disabled";
1594 };
1595
1596 uartg: serial@c290000 {
1597 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1598 reg = <0x0c290000 0x40>;
1599 reg-shift = <2>;
1600 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1601 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1602 clock-names = "serial";
1603 resets = <&bpmp TEGRA194_RESET_UARTG>;
1604 reset-names = "serial";
1605 status = "disabled";
1606 };
1607
1608 rtc: rtc@c2a0000 {
1609 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1610 reg = <0x0c2a0000 0x10000>;
1611 interrupt-parent = <&pmc>;
1612 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1613 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1614 clock-names = "rtc";
1615 status = "disabled";
1616 };
1617
1618 gpio_aon: gpio@c2f0000 {
1619 compatible = "nvidia,tegra194-gpio-aon";
1620 reg-names = "security", "gpio";
1621 reg = <0xc2f0000 0x1000>,
1622 <0xc2f1000 0x1000>;
1623 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1624 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1625 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1626 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1627 gpio-controller;
1628 #gpio-cells = <2>;
1629 interrupt-controller;
1630 #interrupt-cells = <2>;
1631 };
1632
1633 pwm4: pwm@c340000 {
1634 compatible = "nvidia,tegra194-pwm",
1635 "nvidia,tegra186-pwm";
1636 reg = <0xc340000 0x10000>;
1637 clocks = <&bpmp TEGRA194_CLK_PWM4>;
1638 clock-names = "pwm";
1639 resets = <&bpmp TEGRA194_RESET_PWM4>;
1640 reset-names = "pwm";
1641 status = "disabled";
1642 #pwm-cells = <2>;
1643 };
1644
1645 pmc: pmc@c360000 {
1646 compatible = "nvidia,tegra194-pmc";
1647 reg = <0x0c360000 0x10000>,
1648 <0x0c370000 0x10000>,
1649 <0x0c380000 0x10000>,
1650 <0x0c390000 0x10000>,
1651 <0x0c3a0000 0x10000>;
1652 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1653
1654 #interrupt-cells = <2>;
1655 interrupt-controller;
1656 sdmmc1_3v3: sdmmc1-3v3 {
1657 pins = "sdmmc1-hv";
1658 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1659 };
1660
1661 sdmmc1_1v8: sdmmc1-1v8 {
1662 pins = "sdmmc1-hv";
1663 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1664 };
1665 sdmmc3_3v3: sdmmc3-3v3 {
1666 pins = "sdmmc3-hv";
1667 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1668 };
1669
1670 sdmmc3_1v8: sdmmc3-1v8 {
1671 pins = "sdmmc3-hv";
1672 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1673 };
1674
1675 };
1676
1677 aon-noc@c600000 {
1678 compatible = "nvidia,tegra194-aon-noc";
1679 reg = <0xc600000 0x1000>;
1680 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1681 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1682 nvidia,apbmisc = <&apbmisc>;
1683 status = "okay";
1684 };
1685
1686 bpmp-noc@d600000 {
1687 compatible = "nvidia,tegra194-bpmp-noc";
1688 reg = <0xd600000 0x1000>;
1689 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1690 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1691 nvidia,axi2apb = <&axi2apb>;
1692 nvidia,apbmisc = <&apbmisc>;
1693 status = "okay";
1694 };
1695
1696 iommu@10000000 {
1697 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1698 reg = <0x10000000 0x800000>;
1699 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1714 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1715 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1716 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1717 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1718 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1719 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1722 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1725 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1729 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1764 stream-match-mask = <0x7f80>;
1765 #global-interrupts = <1>;
1766 #iommu-cells = <1>;
1767
1768 nvidia,memory-controller = <&mc>;
1769 status = "disabled";
1770 };
1771
1772 smmu: iommu@12000000 {
1773 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1774 reg = <0x12000000 0x800000>,
1775 <0x11000000 0x800000>;
1776 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1777 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1779 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1780 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1783 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1801 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1842 stream-match-mask = <0x7f80>;
1843 #global-interrupts = <2>;
1844 #iommu-cells = <1>;
1845
1846 nvidia,memory-controller = <&mc>;
1847 status = "okay";
1848 };
1849
1850 host1x@13e00000 {
1851 compatible = "nvidia,tegra194-host1x";
1852 reg = <0x13e00000 0x10000>,
1853 <0x13e10000 0x10000>;
1854 reg-names = "hypervisor", "vm";
1855 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1857 interrupt-names = "syncpt", "host1x";
1858 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1859 clock-names = "host1x";
1860 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1861 reset-names = "host1x";
1862
1863 #address-cells = <1>;
1864 #size-cells = <1>;
1865
1866 ranges = <0x15000000 0x15000000 0x01000000>;
1867 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1868 interconnect-names = "dma-mem";
1869 iommus = <&smmu TEGRA194_SID_HOST1X>;
1870
1871 /* Context isolation domains */
1872 iommu-map = <
1873 0 &smmu TEGRA194_SID_HOST1X_CTX0 1
1874 1 &smmu TEGRA194_SID_HOST1X_CTX1 1
1875 2 &smmu TEGRA194_SID_HOST1X_CTX2 1
1876 3 &smmu TEGRA194_SID_HOST1X_CTX3 1
1877 4 &smmu TEGRA194_SID_HOST1X_CTX4 1
1878 5 &smmu TEGRA194_SID_HOST1X_CTX5 1
1879 6 &smmu TEGRA194_SID_HOST1X_CTX6 1
1880 7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
1881
1882 nvdec@15140000 {
1883 compatible = "nvidia,tegra194-nvdec";
1884 reg = <0x15140000 0x00040000>;
1885 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1886 clock-names = "nvdec";
1887 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1888 reset-names = "nvdec";
1889
1890 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1891 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
1892 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
1893 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
1894 interconnect-names = "dma-mem", "read-1", "write";
1895 iommus = <&smmu TEGRA194_SID_NVDEC1>;
1896 dma-coherent;
1897
1898 nvidia,host1x-class = <0xf5>;
1899 };
1900
1901 display-hub@15200000 {
1902 compatible = "nvidia,tegra194-display";
1903 reg = <0x15200000 0x00040000>;
1904 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1905 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1906 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1907 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1908 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1909 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1910 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1911 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1912 "wgrp3", "wgrp4", "wgrp5";
1913 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1914 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1915 clock-names = "disp", "hub";
1916 status = "disabled";
1917
1918 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1919
1920 #address-cells = <1>;
1921 #size-cells = <1>;
1922
1923 ranges = <0x15200000 0x15200000 0x40000>;
1924
1925 display@15200000 {
1926 compatible = "nvidia,tegra194-dc";
1927 reg = <0x15200000 0x10000>;
1928 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1929 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1930 clock-names = "dc";
1931 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1932 reset-names = "dc";
1933
1934 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1935 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1936 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1937 interconnect-names = "dma-mem", "read-1";
1938
1939 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1940 nvidia,head = <0>;
1941 };
1942
1943 display@15210000 {
1944 compatible = "nvidia,tegra194-dc";
1945 reg = <0x15210000 0x10000>;
1946 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1947 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1948 clock-names = "dc";
1949 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1950 reset-names = "dc";
1951
1952 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1953 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1954 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1955 interconnect-names = "dma-mem", "read-1";
1956
1957 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1958 nvidia,head = <1>;
1959 };
1960
1961 display@15220000 {
1962 compatible = "nvidia,tegra194-dc";
1963 reg = <0x15220000 0x10000>;
1964 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1965 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1966 clock-names = "dc";
1967 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1968 reset-names = "dc";
1969
1970 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1971 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973 interconnect-names = "dma-mem", "read-1";
1974
1975 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976 nvidia,head = <2>;
1977 };
1978
1979 display@15230000 {
1980 compatible = "nvidia,tegra194-dc";
1981 reg = <0x15230000 0x10000>;
1982 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1983 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1984 clock-names = "dc";
1985 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1986 reset-names = "dc";
1987
1988 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1989 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991 interconnect-names = "dma-mem", "read-1";
1992
1993 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994 nvidia,head = <3>;
1995 };
1996 };
1997
1998 vic@15340000 {
1999 compatible = "nvidia,tegra194-vic";
2000 reg = <0x15340000 0x00040000>;
2001 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2002 clocks = <&bpmp TEGRA194_CLK_VIC>;
2003 clock-names = "vic";
2004 resets = <&bpmp TEGRA194_RESET_VIC>;
2005 reset-names = "vic";
2006
2007 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2008 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2009 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2010 interconnect-names = "dma-mem", "write";
2011 iommus = <&smmu TEGRA194_SID_VIC>;
2012 dma-coherent;
2013 };
2014
2015 nvjpg@15380000 {
2016 compatible = "nvidia,tegra194-nvjpg";
2017 reg = <0x15380000 0x40000>;
2018 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2019 clock-names = "nvjpg";
2020 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2021 reset-names = "nvjpg";
2022
2023 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2024 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
2025 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
2026 interconnect-names = "dma-mem", "write";
2027 iommus = <&smmu TEGRA194_SID_NVJPG>;
2028 dma-coherent;
2029 };
2030
2031 nvdec@15480000 {
2032 compatible = "nvidia,tegra194-nvdec";
2033 reg = <0x15480000 0x00040000>;
2034 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2035 clock-names = "nvdec";
2036 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2037 reset-names = "nvdec";
2038
2039 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2040 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
2041 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
2042 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
2043 interconnect-names = "dma-mem", "read-1", "write";
2044 iommus = <&smmu TEGRA194_SID_NVDEC>;
2045 dma-coherent;
2046
2047 nvidia,host1x-class = <0xf0>;
2048 };
2049
2050 nvenc@154c0000 {
2051 compatible = "nvidia,tegra194-nvenc";
2052 reg = <0x154c0000 0x40000>;
2053 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2054 clock-names = "nvenc";
2055 resets = <&bpmp TEGRA194_RESET_NVENC>;
2056 reset-names = "nvenc";
2057
2058 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2059 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
2060 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
2061 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
2062 interconnect-names = "dma-mem", "read-1", "write";
2063 iommus = <&smmu TEGRA194_SID_NVENC>;
2064 dma-coherent;
2065
2066 nvidia,host1x-class = <0x21>;
2067 };
2068
2069 dpaux0: dpaux@155c0000 {
2070 compatible = "nvidia,tegra194-dpaux";
2071 reg = <0x155c0000 0x10000>;
2072 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2073 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2074 <&bpmp TEGRA194_CLK_PLLDP>;
2075 clock-names = "dpaux", "parent";
2076 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2077 reset-names = "dpaux";
2078 status = "disabled";
2079
2080 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2081
2082 state_dpaux0_aux: pinmux-aux {
2083 groups = "dpaux-io";
2084 function = "aux";
2085 };
2086
2087 state_dpaux0_i2c: pinmux-i2c {
2088 groups = "dpaux-io";
2089 function = "i2c";
2090 };
2091
2092 state_dpaux0_off: pinmux-off {
2093 groups = "dpaux-io";
2094 function = "off";
2095 };
2096
2097 i2c-bus {
2098 #address-cells = <1>;
2099 #size-cells = <0>;
2100 };
2101 };
2102
2103 dpaux1: dpaux@155d0000 {
2104 compatible = "nvidia,tegra194-dpaux";
2105 reg = <0x155d0000 0x10000>;
2106 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2107 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2108 <&bpmp TEGRA194_CLK_PLLDP>;
2109 clock-names = "dpaux", "parent";
2110 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2111 reset-names = "dpaux";
2112 status = "disabled";
2113
2114 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2115
2116 state_dpaux1_aux: pinmux-aux {
2117 groups = "dpaux-io";
2118 function = "aux";
2119 };
2120
2121 state_dpaux1_i2c: pinmux-i2c {
2122 groups = "dpaux-io";
2123 function = "i2c";
2124 };
2125
2126 state_dpaux1_off: pinmux-off {
2127 groups = "dpaux-io";
2128 function = "off";
2129 };
2130
2131 i2c-bus {
2132 #address-cells = <1>;
2133 #size-cells = <0>;
2134 };
2135 };
2136
2137 dpaux2: dpaux@155e0000 {
2138 compatible = "nvidia,tegra194-dpaux";
2139 reg = <0x155e0000 0x10000>;
2140 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2141 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2142 <&bpmp TEGRA194_CLK_PLLDP>;
2143 clock-names = "dpaux", "parent";
2144 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2145 reset-names = "dpaux";
2146 status = "disabled";
2147
2148 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2149
2150 state_dpaux2_aux: pinmux-aux {
2151 groups = "dpaux-io";
2152 function = "aux";
2153 };
2154
2155 state_dpaux2_i2c: pinmux-i2c {
2156 groups = "dpaux-io";
2157 function = "i2c";
2158 };
2159
2160 state_dpaux2_off: pinmux-off {
2161 groups = "dpaux-io";
2162 function = "off";
2163 };
2164
2165 i2c-bus {
2166 #address-cells = <1>;
2167 #size-cells = <0>;
2168 };
2169 };
2170
2171 dpaux3: dpaux@155f0000 {
2172 compatible = "nvidia,tegra194-dpaux";
2173 reg = <0x155f0000 0x10000>;
2174 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2175 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2176 <&bpmp TEGRA194_CLK_PLLDP>;
2177 clock-names = "dpaux", "parent";
2178 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2179 reset-names = "dpaux";
2180 status = "disabled";
2181
2182 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2183
2184 state_dpaux3_aux: pinmux-aux {
2185 groups = "dpaux-io";
2186 function = "aux";
2187 };
2188
2189 state_dpaux3_i2c: pinmux-i2c {
2190 groups = "dpaux-io";
2191 function = "i2c";
2192 };
2193
2194 state_dpaux3_off: pinmux-off {
2195 groups = "dpaux-io";
2196 function = "off";
2197 };
2198
2199 i2c-bus {
2200 #address-cells = <1>;
2201 #size-cells = <0>;
2202 };
2203 };
2204
2205 nvenc@15a80000 {
2206 compatible = "nvidia,tegra194-nvenc";
2207 reg = <0x15a80000 0x00040000>;
2208 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2209 clock-names = "nvenc";
2210 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2211 reset-names = "nvenc";
2212
2213 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2214 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
2215 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
2216 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
2217 interconnect-names = "dma-mem", "read-1", "write";
2218 iommus = <&smmu TEGRA194_SID_NVENC1>;
2219 dma-coherent;
2220
2221 nvidia,host1x-class = <0x22>;
2222 };
2223
2224 sor0: sor@15b00000 {
2225 compatible = "nvidia,tegra194-sor";
2226 reg = <0x15b00000 0x40000>;
2227 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2228 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2229 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2230 <&bpmp TEGRA194_CLK_PLLD>,
2231 <&bpmp TEGRA194_CLK_PLLDP>,
2232 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2233 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2234 clock-names = "sor", "out", "parent", "dp", "safe",
2235 "pad";
2236 resets = <&bpmp TEGRA194_RESET_SOR0>;
2237 reset-names = "sor";
2238 pinctrl-0 = <&state_dpaux0_aux>;
2239 pinctrl-1 = <&state_dpaux0_i2c>;
2240 pinctrl-2 = <&state_dpaux0_off>;
2241 pinctrl-names = "aux", "i2c", "off";
2242 status = "disabled";
2243
2244 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2245 nvidia,interface = <0>;
2246 };
2247
2248 sor1: sor@15b40000 {
2249 compatible = "nvidia,tegra194-sor";
2250 reg = <0x15b40000 0x40000>;
2251 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2252 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2253 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2254 <&bpmp TEGRA194_CLK_PLLD2>,
2255 <&bpmp TEGRA194_CLK_PLLDP>,
2256 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2257 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2258 clock-names = "sor", "out", "parent", "dp", "safe",
2259 "pad";
2260 resets = <&bpmp TEGRA194_RESET_SOR1>;
2261 reset-names = "sor";
2262 pinctrl-0 = <&state_dpaux1_aux>;
2263 pinctrl-1 = <&state_dpaux1_i2c>;
2264 pinctrl-2 = <&state_dpaux1_off>;
2265 pinctrl-names = "aux", "i2c", "off";
2266 status = "disabled";
2267
2268 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2269 nvidia,interface = <1>;
2270 };
2271
2272 sor2: sor@15b80000 {
2273 compatible = "nvidia,tegra194-sor";
2274 reg = <0x15b80000 0x40000>;
2275 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2276 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2277 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2278 <&bpmp TEGRA194_CLK_PLLD3>,
2279 <&bpmp TEGRA194_CLK_PLLDP>,
2280 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2281 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2282 clock-names = "sor", "out", "parent", "dp", "safe",
2283 "pad";
2284 resets = <&bpmp TEGRA194_RESET_SOR2>;
2285 reset-names = "sor";
2286 pinctrl-0 = <&state_dpaux2_aux>;
2287 pinctrl-1 = <&state_dpaux2_i2c>;
2288 pinctrl-2 = <&state_dpaux2_off>;
2289 pinctrl-names = "aux", "i2c", "off";
2290 status = "disabled";
2291
2292 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2293 nvidia,interface = <2>;
2294 };
2295
2296 sor3: sor@15bc0000 {
2297 compatible = "nvidia,tegra194-sor";
2298 reg = <0x15bc0000 0x40000>;
2299 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2300 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2301 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2302 <&bpmp TEGRA194_CLK_PLLD4>,
2303 <&bpmp TEGRA194_CLK_PLLDP>,
2304 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2305 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2306 clock-names = "sor", "out", "parent", "dp", "safe",
2307 "pad";
2308 resets = <&bpmp TEGRA194_RESET_SOR3>;
2309 reset-names = "sor";
2310 pinctrl-0 = <&state_dpaux3_aux>;
2311 pinctrl-1 = <&state_dpaux3_i2c>;
2312 pinctrl-2 = <&state_dpaux3_off>;
2313 pinctrl-names = "aux", "i2c", "off";
2314 status = "disabled";
2315
2316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2317 nvidia,interface = <3>;
2318 };
2319 };
2320
2321 gpu@17000000 {
2322 compatible = "nvidia,gv11b";
2323 reg = <0x17000000 0x1000000>,
2324 <0x18000000 0x1000000>;
2325 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2326 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2327 interrupt-names = "stall", "nonstall";
2328 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2329 <&bpmp TEGRA194_CLK_GPU_PWR>,
2330 <&bpmp TEGRA194_CLK_FUSE>;
2331 clock-names = "gpu", "pwr", "fuse";
2332 resets = <&bpmp TEGRA194_RESET_GPU>;
2333 reset-names = "gpu";
2334 dma-coherent;
2335
2336 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2337 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2338 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2339 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2340 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2341 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2342 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2343 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2344 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2345 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2346 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2347 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2348 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2349 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2350 "read-1", "read-1-hp", "write-1",
2351 "read-2", "read-2-hp", "write-2",
2352 "read-3", "read-3-hp", "write-3";
2353 };
2354 };
2355
2356 pcie@14100000 {
2357 compatible = "nvidia,tegra194-pcie";
2358 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2359 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2360 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2361 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2362 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2363 reg-names = "appl", "config", "atu_dma", "dbi";
2364
2365 status = "disabled";
2366
2367 #address-cells = <3>;
2368 #size-cells = <2>;
2369 device_type = "pci";
2370 num-lanes = <1>;
2371 linux,pci-domain = <1>;
2372
2373 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2374 clock-names = "core";
2375
2376 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2377 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2378 reset-names = "apb", "core";
2379
2380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2381 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2382 interrupt-names = "intr", "msi";
2383
2384 #interrupt-cells = <1>;
2385 interrupt-map-mask = <0 0 0 0>;
2386 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2387
2388 nvidia,bpmp = <&bpmp 1>;
2389
2390 nvidia,aspm-cmrt-us = <60>;
2391 nvidia,aspm-pwr-on-t-us = <20>;
2392 nvidia,aspm-l0s-entrance-latency-us = <3>;
2393
2394 bus-range = <0x0 0xff>;
2395
2396 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2397 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2398 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2399
2400 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
2401 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
2402 interconnect-names = "dma-mem", "write";
2403 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2404 iommu-map-mask = <0x0>;
2405 dma-coherent;
2406 };
2407
2408 pcie@14120000 {
2409 compatible = "nvidia,tegra194-pcie";
2410 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2411 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2412 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2413 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2414 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
2415 reg-names = "appl", "config", "atu_dma", "dbi";
2416
2417 status = "disabled";
2418
2419 #address-cells = <3>;
2420 #size-cells = <2>;
2421 device_type = "pci";
2422 num-lanes = <1>;
2423 linux,pci-domain = <2>;
2424
2425 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2426 clock-names = "core";
2427
2428 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2429 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2430 reset-names = "apb", "core";
2431
2432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2433 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2434 interrupt-names = "intr", "msi";
2435
2436 #interrupt-cells = <1>;
2437 interrupt-map-mask = <0 0 0 0>;
2438 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2439
2440 nvidia,bpmp = <&bpmp 2>;
2441
2442 nvidia,aspm-cmrt-us = <60>;
2443 nvidia,aspm-pwr-on-t-us = <20>;
2444 nvidia,aspm-l0s-entrance-latency-us = <3>;
2445
2446 bus-range = <0x0 0xff>;
2447
2448 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2449 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2450 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2451
2452 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
2453 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
2454 interconnect-names = "dma-mem", "write";
2455 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2456 iommu-map-mask = <0x0>;
2457 dma-coherent;
2458 };
2459
2460 pcie@14140000 {
2461 compatible = "nvidia,tegra194-pcie";
2462 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2463 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2464 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2465 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2466 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
2467 reg-names = "appl", "config", "atu_dma", "dbi";
2468
2469 status = "disabled";
2470
2471 #address-cells = <3>;
2472 #size-cells = <2>;
2473 device_type = "pci";
2474 num-lanes = <1>;
2475 linux,pci-domain = <3>;
2476
2477 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2478 clock-names = "core";
2479
2480 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2481 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2482 reset-names = "apb", "core";
2483
2484 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2485 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2486 interrupt-names = "intr", "msi";
2487
2488 #interrupt-cells = <1>;
2489 interrupt-map-mask = <0 0 0 0>;
2490 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2491
2492 nvidia,bpmp = <&bpmp 3>;
2493
2494 nvidia,aspm-cmrt-us = <60>;
2495 nvidia,aspm-pwr-on-t-us = <20>;
2496 nvidia,aspm-l0s-entrance-latency-us = <3>;
2497
2498 bus-range = <0x0 0xff>;
2499
2500 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2501 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
2502 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2503
2504 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
2505 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
2506 interconnect-names = "dma-mem", "write";
2507 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2508 iommu-map-mask = <0x0>;
2509 dma-coherent;
2510 };
2511
2512 pcie@14160000 {
2513 compatible = "nvidia,tegra194-pcie";
2514 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2515 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2516 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2517 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2518 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
2519 reg-names = "appl", "config", "atu_dma", "dbi";
2520
2521 status = "disabled";
2522
2523 #address-cells = <3>;
2524 #size-cells = <2>;
2525 device_type = "pci";
2526 num-lanes = <4>;
2527 linux,pci-domain = <4>;
2528
2529 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2530 clock-names = "core";
2531
2532 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2533 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2534 reset-names = "apb", "core";
2535
2536 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2537 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2538 interrupt-names = "intr", "msi";
2539
2540 #interrupt-cells = <1>;
2541 interrupt-map-mask = <0 0 0 0>;
2542 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2543
2544 nvidia,bpmp = <&bpmp 4>;
2545
2546 nvidia,aspm-cmrt-us = <60>;
2547 nvidia,aspm-pwr-on-t-us = <20>;
2548 nvidia,aspm-l0s-entrance-latency-us = <3>;
2549
2550 bus-range = <0x0 0xff>;
2551
2552 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2553 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2554 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2555
2556 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2557 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2558 interconnect-names = "dma-mem", "write";
2559 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2560 iommu-map-mask = <0x0>;
2561 dma-coherent;
2562 };
2563
2564 pcie@14180000 {
2565 compatible = "nvidia,tegra194-pcie";
2566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2567 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2568 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2569 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2570 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2571 reg-names = "appl", "config", "atu_dma", "dbi";
2572
2573 status = "disabled";
2574
2575 #address-cells = <3>;
2576 #size-cells = <2>;
2577 device_type = "pci";
2578 num-lanes = <8>;
2579 linux,pci-domain = <0>;
2580
2581 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2582 clock-names = "core";
2583
2584 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2585 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2586 reset-names = "apb", "core";
2587
2588 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2589 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2590 interrupt-names = "intr", "msi";
2591
2592 #interrupt-cells = <1>;
2593 interrupt-map-mask = <0 0 0 0>;
2594 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2595
2596 nvidia,bpmp = <&bpmp 0>;
2597
2598 nvidia,aspm-cmrt-us = <60>;
2599 nvidia,aspm-pwr-on-t-us = <20>;
2600 nvidia,aspm-l0s-entrance-latency-us = <3>;
2601
2602 bus-range = <0x0 0xff>;
2603
2604 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2605 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2606 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2607
2608 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2609 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2610 interconnect-names = "dma-mem", "write";
2611 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2612 iommu-map-mask = <0x0>;
2613 dma-coherent;
2614 };
2615
2616 pcie@141a0000 {
2617 compatible = "nvidia,tegra194-pcie";
2618 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2619 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2620 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2621 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2622 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2623 reg-names = "appl", "config", "atu_dma", "dbi";
2624
2625 status = "disabled";
2626
2627 #address-cells = <3>;
2628 #size-cells = <2>;
2629 device_type = "pci";
2630 num-lanes = <8>;
2631 linux,pci-domain = <5>;
2632
2633 pinctrl-names = "default";
2634 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2635
2636 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2637 clock-names = "core";
2638
2639 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2640 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2641 reset-names = "apb", "core";
2642
2643 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2644 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2645 interrupt-names = "intr", "msi";
2646
2647 nvidia,bpmp = <&bpmp 5>;
2648
2649 #interrupt-cells = <1>;
2650 interrupt-map-mask = <0 0 0 0>;
2651 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2652
2653 nvidia,aspm-cmrt-us = <60>;
2654 nvidia,aspm-pwr-on-t-us = <20>;
2655 nvidia,aspm-l0s-entrance-latency-us = <3>;
2656
2657 bus-range = <0x0 0xff>;
2658
2659 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2660 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2661 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2662
2663 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2664 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2665 interconnect-names = "dma-mem", "write";
2666 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2667 iommu-map-mask = <0x0>;
2668 dma-coherent;
2669 };
2670
2671 pcie-ep@14160000 {
2672 compatible = "nvidia,tegra194-pcie-ep";
2673 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2674 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2675 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2676 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2677 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2678 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2679
2680 status = "disabled";
2681
2682 num-lanes = <4>;
2683 num-ib-windows = <2>;
2684 num-ob-windows = <8>;
2685
2686 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2687 clock-names = "core";
2688
2689 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2690 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2691 reset-names = "apb", "core";
2692
2693 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2694 interrupt-names = "intr";
2695
2696 nvidia,bpmp = <&bpmp 4>;
2697
2698 nvidia,aspm-cmrt-us = <60>;
2699 nvidia,aspm-pwr-on-t-us = <20>;
2700 nvidia,aspm-l0s-entrance-latency-us = <3>;
2701
2702 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2703 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2704 interconnect-names = "dma-mem", "write";
2705 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2706 iommu-map-mask = <0x0>;
2707 dma-coherent;
2708 };
2709
2710 pcie-ep@14180000 {
2711 compatible = "nvidia,tegra194-pcie-ep";
2712 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2713 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2714 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2715 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2716 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2717 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2718
2719 status = "disabled";
2720
2721 num-lanes = <8>;
2722 num-ib-windows = <2>;
2723 num-ob-windows = <8>;
2724
2725 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2726 clock-names = "core";
2727
2728 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2729 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2730 reset-names = "apb", "core";
2731
2732 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2733 interrupt-names = "intr";
2734
2735 nvidia,bpmp = <&bpmp 0>;
2736
2737 nvidia,aspm-cmrt-us = <60>;
2738 nvidia,aspm-pwr-on-t-us = <20>;
2739 nvidia,aspm-l0s-entrance-latency-us = <3>;
2740
2741 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2742 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2743 interconnect-names = "dma-mem", "write";
2744 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2745 iommu-map-mask = <0x0>;
2746 dma-coherent;
2747 };
2748
2749 pcie-ep@141a0000 {
2750 compatible = "nvidia,tegra194-pcie-ep";
2751 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2752 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2753 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2754 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2755 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2756 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2757
2758 status = "disabled";
2759
2760 num-lanes = <8>;
2761 num-ib-windows = <2>;
2762 num-ob-windows = <8>;
2763
2764 pinctrl-names = "default";
2765 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2766
2767 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2768 clock-names = "core";
2769
2770 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2771 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2772 reset-names = "apb", "core";
2773
2774 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2775 interrupt-names = "intr";
2776
2777 nvidia,bpmp = <&bpmp 5>;
2778
2779 nvidia,aspm-cmrt-us = <60>;
2780 nvidia,aspm-pwr-on-t-us = <20>;
2781 nvidia,aspm-l0s-entrance-latency-us = <3>;
2782
2783 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2784 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2785 interconnect-names = "dma-mem", "write";
2786 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2787 iommu-map-mask = <0x0>;
2788 dma-coherent;
2789 };
2790
2791 sram@40000000 {
2792 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2793 reg = <0x0 0x40000000 0x0 0x50000>;
2794 #address-cells = <1>;
2795 #size-cells = <1>;
2796 ranges = <0x0 0x0 0x40000000 0x50000>;
2797 no-memory-wc;
2798
2799 cpu_bpmp_tx: sram@4e000 {
2800 reg = <0x4e000 0x1000>;
2801 label = "cpu-bpmp-tx";
2802 pool;
2803 };
2804
2805 cpu_bpmp_rx: sram@4f000 {
2806 reg = <0x4f000 0x1000>;
2807 label = "cpu-bpmp-rx";
2808 pool;
2809 };
2810 };
2811
2812 bpmp: bpmp {
2813 compatible = "nvidia,tegra186-bpmp";
2814 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2815 TEGRA_HSP_DB_MASTER_BPMP>;
2816 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2817 #clock-cells = <1>;
2818 #reset-cells = <1>;
2819 #power-domain-cells = <1>;
2820 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2821 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2822 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2823 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2824 interconnect-names = "read", "write", "dma-mem", "dma-write";
2825 iommus = <&smmu TEGRA194_SID_BPMP>;
2826
2827 bpmp_i2c: i2c {
2828 compatible = "nvidia,tegra186-bpmp-i2c";
2829 nvidia,bpmp-bus-id = <5>;
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2832 };
2833
2834 bpmp_thermal: thermal {
2835 compatible = "nvidia,tegra186-bpmp-thermal";
2836 #thermal-sensor-cells = <1>;
2837 };
2838 };
2839
2840 cpus {
2841 compatible = "nvidia,tegra194-ccplex";
2842 nvidia,bpmp = <&bpmp>;
2843 #address-cells = <1>;
2844 #size-cells = <0>;
2845
2846 cpu0_0: cpu@0 {
2847 compatible = "nvidia,tegra194-carmel";
2848 device_type = "cpu";
2849 reg = <0x000>;
2850 enable-method = "psci";
2851 i-cache-size = <131072>;
2852 i-cache-line-size = <64>;
2853 i-cache-sets = <512>;
2854 d-cache-size = <65536>;
2855 d-cache-line-size = <64>;
2856 d-cache-sets = <256>;
2857 next-level-cache = <&l2c_0>;
2858 };
2859
2860 cpu0_1: cpu@1 {
2861 compatible = "nvidia,tegra194-carmel";
2862 device_type = "cpu";
2863 reg = <0x001>;
2864 enable-method = "psci";
2865 i-cache-size = <131072>;
2866 i-cache-line-size = <64>;
2867 i-cache-sets = <512>;
2868 d-cache-size = <65536>;
2869 d-cache-line-size = <64>;
2870 d-cache-sets = <256>;
2871 next-level-cache = <&l2c_0>;
2872 };
2873
2874 cpu1_0: cpu@100 {
2875 compatible = "nvidia,tegra194-carmel";
2876 device_type = "cpu";
2877 reg = <0x100>;
2878 enable-method = "psci";
2879 i-cache-size = <131072>;
2880 i-cache-line-size = <64>;
2881 i-cache-sets = <512>;
2882 d-cache-size = <65536>;
2883 d-cache-line-size = <64>;
2884 d-cache-sets = <256>;
2885 next-level-cache = <&l2c_1>;
2886 };
2887
2888 cpu1_1: cpu@101 {
2889 compatible = "nvidia,tegra194-carmel";
2890 device_type = "cpu";
2891 reg = <0x101>;
2892 enable-method = "psci";
2893 i-cache-size = <131072>;
2894 i-cache-line-size = <64>;
2895 i-cache-sets = <512>;
2896 d-cache-size = <65536>;
2897 d-cache-line-size = <64>;
2898 d-cache-sets = <256>;
2899 next-level-cache = <&l2c_1>;
2900 };
2901
2902 cpu2_0: cpu@200 {
2903 compatible = "nvidia,tegra194-carmel";
2904 device_type = "cpu";
2905 reg = <0x200>;
2906 enable-method = "psci";
2907 i-cache-size = <131072>;
2908 i-cache-line-size = <64>;
2909 i-cache-sets = <512>;
2910 d-cache-size = <65536>;
2911 d-cache-line-size = <64>;
2912 d-cache-sets = <256>;
2913 next-level-cache = <&l2c_2>;
2914 };
2915
2916 cpu2_1: cpu@201 {
2917 compatible = "nvidia,tegra194-carmel";
2918 device_type = "cpu";
2919 reg = <0x201>;
2920 enable-method = "psci";
2921 i-cache-size = <131072>;
2922 i-cache-line-size = <64>;
2923 i-cache-sets = <512>;
2924 d-cache-size = <65536>;
2925 d-cache-line-size = <64>;
2926 d-cache-sets = <256>;
2927 next-level-cache = <&l2c_2>;
2928 };
2929
2930 cpu3_0: cpu@300 {
2931 compatible = "nvidia,tegra194-carmel";
2932 device_type = "cpu";
2933 reg = <0x300>;
2934 enable-method = "psci";
2935 i-cache-size = <131072>;
2936 i-cache-line-size = <64>;
2937 i-cache-sets = <512>;
2938 d-cache-size = <65536>;
2939 d-cache-line-size = <64>;
2940 d-cache-sets = <256>;
2941 next-level-cache = <&l2c_3>;
2942 };
2943
2944 cpu3_1: cpu@301 {
2945 compatible = "nvidia,tegra194-carmel";
2946 device_type = "cpu";
2947 reg = <0x301>;
2948 enable-method = "psci";
2949 i-cache-size = <131072>;
2950 i-cache-line-size = <64>;
2951 i-cache-sets = <512>;
2952 d-cache-size = <65536>;
2953 d-cache-line-size = <64>;
2954 d-cache-sets = <256>;
2955 next-level-cache = <&l2c_3>;
2956 };
2957
2958 cpu-map {
2959 cluster0 {
2960 core0 {
2961 cpu = <&cpu0_0>;
2962 };
2963
2964 core1 {
2965 cpu = <&cpu0_1>;
2966 };
2967 };
2968
2969 cluster1 {
2970 core0 {
2971 cpu = <&cpu1_0>;
2972 };
2973
2974 core1 {
2975 cpu = <&cpu1_1>;
2976 };
2977 };
2978
2979 cluster2 {
2980 core0 {
2981 cpu = <&cpu2_0>;
2982 };
2983
2984 core1 {
2985 cpu = <&cpu2_1>;
2986 };
2987 };
2988
2989 cluster3 {
2990 core0 {
2991 cpu = <&cpu3_0>;
2992 };
2993
2994 core1 {
2995 cpu = <&cpu3_1>;
2996 };
2997 };
2998 };
2999
3000 l2c_0: l2-cache0 {
3001 cache-size = <2097152>;
3002 cache-line-size = <64>;
3003 cache-sets = <2048>;
3004 next-level-cache = <&l3c>;
3005 };
3006
3007 l2c_1: l2-cache1 {
3008 cache-size = <2097152>;
3009 cache-line-size = <64>;
3010 cache-sets = <2048>;
3011 next-level-cache = <&l3c>;
3012 };
3013
3014 l2c_2: l2-cache2 {
3015 cache-size = <2097152>;
3016 cache-line-size = <64>;
3017 cache-sets = <2048>;
3018 next-level-cache = <&l3c>;
3019 };
3020
3021 l2c_3: l2-cache3 {
3022 cache-size = <2097152>;
3023 cache-line-size = <64>;
3024 cache-sets = <2048>;
3025 next-level-cache = <&l3c>;
3026 };
3027
3028 l3c: l3-cache {
3029 cache-size = <4194304>;
3030 cache-line-size = <64>;
3031 cache-sets = <4096>;
3032 };
3033 };
3034
3035 pmu {
3036 compatible = "nvidia,carmel-pmu";
3037 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
3038 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
3039 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
3040 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
3041 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
3042 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
3043 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
3044 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
3045 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3046 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
3047 };
3048
3049 psci {
3050 compatible = "arm,psci-1.0";
3051 status = "okay";
3052 method = "smc";
3053 };
3054
3055 sound {
3056 status = "disabled";
3057
3058 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3059 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3060 clock-names = "pll_a", "plla_out0";
3061 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3062 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3063 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3064 assigned-clock-parents = <0>,
3065 <&bpmp TEGRA194_CLK_PLLA>,
3066 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3067 /*
3068 * PLLA supports dynamic ramp. Below initial rate is chosen
3069 * for this to work and oscillate between base rates required
3070 * for 8x and 11.025x sample rate streams.
3071 */
3072 assigned-clock-rates = <258000000>;
3073 };
3074
3075 tcu: serial {
3076 compatible = "nvidia,tegra194-tcu";
3077 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3078 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3079 mbox-names = "rx", "tx";
3080 };
3081
3082 thermal-zones {
3083 cpu-thermal {
3084 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3085 status = "disabled";
3086 };
3087
3088 gpu-thermal {
3089 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3090 status = "disabled";
3091 };
3092
3093 aux-thermal {
3094 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3095 status = "disabled";
3096 };
3097
3098 pllx-thermal {
3099 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3100 status = "disabled";
3101 };
3102
3103 ao-thermal {
3104 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3105 status = "disabled";
3106 };
3107
3108 tj-thermal {
3109 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3110 status = "disabled";
3111 };
3112 };
3113
3114 timer {
3115 compatible = "arm,armv8-timer";
3116 interrupts = <GIC_PPI 13
3117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3118 <GIC_PPI 14
3119 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3120 <GIC_PPI 11
3121 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3122 <GIC_PPI 10
3123 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3124 interrupt-parent = <&gic>;
3125 always-on;
3126 };
3127 };
