0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra186-clock.h>
0003 #include <dt-bindings/gpio/tegra186-gpio.h>
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/mailbox/tegra186-hsp.h>
0006 #include <dt-bindings/memory/tegra186-mc.h>
0007 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
0008 #include <dt-bindings/power/tegra186-powergate.h>
0009 #include <dt-bindings/reset/tegra186-reset.h>
0010 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
0011
0012 / {
0013 compatible = "nvidia,tegra186";
0014 interrupt-parent = <&gic>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 misc@100000 {
0019 compatible = "nvidia,tegra186-misc";
0020 reg = <0x0 0x00100000 0x0 0xf000>,
0021 <0x0 0x0010f000 0x0 0x1000>;
0022 };
0023
0024 gpio: gpio@2200000 {
0025 compatible = "nvidia,tegra186-gpio";
0026 reg-names = "security", "gpio";
0027 reg = <0x0 0x2200000 0x0 0x10000>,
0028 <0x0 0x2210000 0x0 0x10000>;
0029 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
0030 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
0031 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0032 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0033 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0034 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0035 #interrupt-cells = <2>;
0036 interrupt-controller;
0037 #gpio-cells = <2>;
0038 gpio-controller;
0039 };
0040
0041 ethernet@2490000 {
0042 compatible = "nvidia,tegra186-eqos",
0043 "snps,dwc-qos-ethernet-4.10";
0044 reg = <0x0 0x02490000 0x0 0x10000>;
0045 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
0046 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
0047 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
0048 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
0049 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
0050 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
0051 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
0052 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
0053 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
0054 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
0055 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
0056 <&bpmp TEGRA186_CLK_EQOS_AXI>,
0057 <&bpmp TEGRA186_CLK_EQOS_RX>,
0058 <&bpmp TEGRA186_CLK_EQOS_TX>,
0059 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
0060 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
0061 resets = <&bpmp TEGRA186_RESET_EQOS>;
0062 reset-names = "eqos";
0063 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
0064 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
0065 interconnect-names = "dma-mem", "write";
0066 iommus = <&smmu TEGRA186_SID_EQOS>;
0067 status = "disabled";
0068
0069 snps,write-requests = <1>;
0070 snps,read-requests = <3>;
0071 snps,burst-map = <0x7>;
0072 snps,txpbl = <32>;
0073 snps,rxpbl = <8>;
0074 };
0075
0076 gpcdma: dma-controller@2600000 {
0077 compatible = "nvidia,tegra186-gpcdma";
0078 reg = <0x0 0x2600000 0x0 0x210000>;
0079 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
0080 reset-names = "gpcdma";
0081 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
0085 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
0086 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
0087 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0088 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0089 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0090 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0091 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0092 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0093 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0094 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0096 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
0098 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
0099 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
0100 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0112 #dma-cells = <1>;
0113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
0114 dma-coherent;
0115 status = "okay";
0116 };
0117
0118 aconnect@2900000 {
0119 compatible = "nvidia,tegra186-aconnect",
0120 "nvidia,tegra210-aconnect";
0121 clocks = <&bpmp TEGRA186_CLK_APE>,
0122 <&bpmp TEGRA186_CLK_APB2APE>;
0123 clock-names = "ape", "apb2ape";
0124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
0125 #address-cells = <1>;
0126 #size-cells = <1>;
0127 ranges = <0x02900000 0x0 0x02900000 0x200000>;
0128 status = "disabled";
0129
0130 adma: dma-controller@2930000 {
0131 compatible = "nvidia,tegra186-adma";
0132 reg = <0x02930000 0x20000>;
0133 interrupt-parent = <&agic>;
0134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0166 #dma-cells = <1>;
0167 clocks = <&bpmp TEGRA186_CLK_AHUB>;
0168 clock-names = "d_audio";
0169 status = "disabled";
0170 };
0171
0172 agic: interrupt-controller@2a40000 {
0173 compatible = "nvidia,tegra186-agic",
0174 "nvidia,tegra210-agic";
0175 #interrupt-cells = <3>;
0176 interrupt-controller;
0177 reg = <0x02a41000 0x1000>,
0178 <0x02a42000 0x2000>;
0179 interrupts = <GIC_SPI 145
0180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0181 clocks = <&bpmp TEGRA186_CLK_APE>;
0182 clock-names = "clk";
0183 status = "disabled";
0184 };
0185
0186 tegra_ahub: ahub@2900800 {
0187 compatible = "nvidia,tegra186-ahub";
0188 reg = <0x02900800 0x800>;
0189 clocks = <&bpmp TEGRA186_CLK_AHUB>;
0190 clock-names = "ahub";
0191 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
0192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0193 #address-cells = <1>;
0194 #size-cells = <1>;
0195 ranges = <0x02900800 0x02900800 0x11800>;
0196 status = "disabled";
0197
0198 tegra_admaif: admaif@290f000 {
0199 compatible = "nvidia,tegra186-admaif";
0200 reg = <0x0290f000 0x1000>;
0201 dmas = <&adma 1>, <&adma 1>,
0202 <&adma 2>, <&adma 2>,
0203 <&adma 3>, <&adma 3>,
0204 <&adma 4>, <&adma 4>,
0205 <&adma 5>, <&adma 5>,
0206 <&adma 6>, <&adma 6>,
0207 <&adma 7>, <&adma 7>,
0208 <&adma 8>, <&adma 8>,
0209 <&adma 9>, <&adma 9>,
0210 <&adma 10>, <&adma 10>,
0211 <&adma 11>, <&adma 11>,
0212 <&adma 12>, <&adma 12>,
0213 <&adma 13>, <&adma 13>,
0214 <&adma 14>, <&adma 14>,
0215 <&adma 15>, <&adma 15>,
0216 <&adma 16>, <&adma 16>,
0217 <&adma 17>, <&adma 17>,
0218 <&adma 18>, <&adma 18>,
0219 <&adma 19>, <&adma 19>,
0220 <&adma 20>, <&adma 20>;
0221 dma-names = "rx1", "tx1",
0222 "rx2", "tx2",
0223 "rx3", "tx3",
0224 "rx4", "tx4",
0225 "rx5", "tx5",
0226 "rx6", "tx6",
0227 "rx7", "tx7",
0228 "rx8", "tx8",
0229 "rx9", "tx9",
0230 "rx10", "tx10",
0231 "rx11", "tx11",
0232 "rx12", "tx12",
0233 "rx13", "tx13",
0234 "rx14", "tx14",
0235 "rx15", "tx15",
0236 "rx16", "tx16",
0237 "rx17", "tx17",
0238 "rx18", "tx18",
0239 "rx19", "tx19",
0240 "rx20", "tx20";
0241 status = "disabled";
0242 };
0243
0244 tegra_i2s1: i2s@2901000 {
0245 compatible = "nvidia,tegra186-i2s",
0246 "nvidia,tegra210-i2s";
0247 reg = <0x2901000 0x100>;
0248 clocks = <&bpmp TEGRA186_CLK_I2S1>,
0249 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
0250 clock-names = "i2s", "sync_input";
0251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
0252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0253 assigned-clock-rates = <1536000>;
0254 sound-name-prefix = "I2S1";
0255 status = "disabled";
0256 };
0257
0258 tegra_i2s2: i2s@2901100 {
0259 compatible = "nvidia,tegra186-i2s",
0260 "nvidia,tegra210-i2s";
0261 reg = <0x2901100 0x100>;
0262 clocks = <&bpmp TEGRA186_CLK_I2S2>,
0263 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
0264 clock-names = "i2s", "sync_input";
0265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
0266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0267 assigned-clock-rates = <1536000>;
0268 sound-name-prefix = "I2S2";
0269 status = "disabled";
0270 };
0271
0272 tegra_i2s3: i2s@2901200 {
0273 compatible = "nvidia,tegra186-i2s",
0274 "nvidia,tegra210-i2s";
0275 reg = <0x2901200 0x100>;
0276 clocks = <&bpmp TEGRA186_CLK_I2S3>,
0277 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
0278 clock-names = "i2s", "sync_input";
0279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
0280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0281 assigned-clock-rates = <1536000>;
0282 sound-name-prefix = "I2S3";
0283 status = "disabled";
0284 };
0285
0286 tegra_i2s4: i2s@2901300 {
0287 compatible = "nvidia,tegra186-i2s",
0288 "nvidia,tegra210-i2s";
0289 reg = <0x2901300 0x100>;
0290 clocks = <&bpmp TEGRA186_CLK_I2S4>,
0291 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
0292 clock-names = "i2s", "sync_input";
0293 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
0294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0295 assigned-clock-rates = <1536000>;
0296 sound-name-prefix = "I2S4";
0297 status = "disabled";
0298 };
0299
0300 tegra_i2s5: i2s@2901400 {
0301 compatible = "nvidia,tegra186-i2s",
0302 "nvidia,tegra210-i2s";
0303 reg = <0x2901400 0x100>;
0304 clocks = <&bpmp TEGRA186_CLK_I2S5>,
0305 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
0306 clock-names = "i2s", "sync_input";
0307 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
0308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0309 assigned-clock-rates = <1536000>;
0310 sound-name-prefix = "I2S5";
0311 status = "disabled";
0312 };
0313
0314 tegra_i2s6: i2s@2901500 {
0315 compatible = "nvidia,tegra186-i2s",
0316 "nvidia,tegra210-i2s";
0317 reg = <0x2901500 0x100>;
0318 clocks = <&bpmp TEGRA186_CLK_I2S6>,
0319 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
0320 clock-names = "i2s", "sync_input";
0321 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
0322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0323 assigned-clock-rates = <1536000>;
0324 sound-name-prefix = "I2S6";
0325 status = "disabled";
0326 };
0327
0328 tegra_dmic1: dmic@2904000 {
0329 compatible = "nvidia,tegra210-dmic";
0330 reg = <0x2904000 0x100>;
0331 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
0332 clock-names = "dmic";
0333 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
0334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0335 assigned-clock-rates = <3072000>;
0336 sound-name-prefix = "DMIC1";
0337 status = "disabled";
0338 };
0339
0340 tegra_dmic2: dmic@2904100 {
0341 compatible = "nvidia,tegra210-dmic";
0342 reg = <0x2904100 0x100>;
0343 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
0344 clock-names = "dmic";
0345 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
0346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0347 assigned-clock-rates = <3072000>;
0348 sound-name-prefix = "DMIC2";
0349 status = "disabled";
0350 };
0351
0352 tegra_dmic3: dmic@2904200 {
0353 compatible = "nvidia,tegra210-dmic";
0354 reg = <0x2904200 0x100>;
0355 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
0356 clock-names = "dmic";
0357 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
0358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0359 assigned-clock-rates = <3072000>;
0360 sound-name-prefix = "DMIC3";
0361 status = "disabled";
0362 };
0363
0364 tegra_dmic4: dmic@2904300 {
0365 compatible = "nvidia,tegra210-dmic";
0366 reg = <0x2904300 0x100>;
0367 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
0368 clock-names = "dmic";
0369 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
0370 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0371 assigned-clock-rates = <3072000>;
0372 sound-name-prefix = "DMIC4";
0373 status = "disabled";
0374 };
0375
0376 tegra_dspk1: dspk@2905000 {
0377 compatible = "nvidia,tegra186-dspk";
0378 reg = <0x2905000 0x100>;
0379 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
0380 clock-names = "dspk";
0381 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
0382 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0383 assigned-clock-rates = <12288000>;
0384 sound-name-prefix = "DSPK1";
0385 status = "disabled";
0386 };
0387
0388 tegra_dspk2: dspk@2905100 {
0389 compatible = "nvidia,tegra186-dspk";
0390 reg = <0x2905100 0x100>;
0391 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
0392 clock-names = "dspk";
0393 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
0394 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
0395 assigned-clock-rates = <12288000>;
0396 sound-name-prefix = "DSPK2";
0397 status = "disabled";
0398 };
0399
0400 tegra_sfc1: sfc@2902000 {
0401 compatible = "nvidia,tegra186-sfc",
0402 "nvidia,tegra210-sfc";
0403 reg = <0x2902000 0x200>;
0404 sound-name-prefix = "SFC1";
0405 status = "disabled";
0406 };
0407
0408 tegra_sfc2: sfc@2902200 {
0409 compatible = "nvidia,tegra186-sfc",
0410 "nvidia,tegra210-sfc";
0411 reg = <0x2902200 0x200>;
0412 sound-name-prefix = "SFC2";
0413 status = "disabled";
0414 };
0415
0416 tegra_sfc3: sfc@2902400 {
0417 compatible = "nvidia,tegra186-sfc",
0418 "nvidia,tegra210-sfc";
0419 reg = <0x2902400 0x200>;
0420 sound-name-prefix = "SFC3";
0421 status = "disabled";
0422 };
0423
0424 tegra_sfc4: sfc@2902600 {
0425 compatible = "nvidia,tegra186-sfc",
0426 "nvidia,tegra210-sfc";
0427 reg = <0x2902600 0x200>;
0428 sound-name-prefix = "SFC4";
0429 status = "disabled";
0430 };
0431
0432 tegra_mvc1: mvc@290a000 {
0433 compatible = "nvidia,tegra186-mvc",
0434 "nvidia,tegra210-mvc";
0435 reg = <0x290a000 0x200>;
0436 sound-name-prefix = "MVC1";
0437 status = "disabled";
0438 };
0439
0440 tegra_mvc2: mvc@290a200 {
0441 compatible = "nvidia,tegra186-mvc",
0442 "nvidia,tegra210-mvc";
0443 reg = <0x290a200 0x200>;
0444 sound-name-prefix = "MVC2";
0445 status = "disabled";
0446 };
0447
0448 tegra_amx1: amx@2903000 {
0449 compatible = "nvidia,tegra186-amx",
0450 "nvidia,tegra210-amx";
0451 reg = <0x2903000 0x100>;
0452 sound-name-prefix = "AMX1";
0453 status = "disabled";
0454 };
0455
0456 tegra_amx2: amx@2903100 {
0457 compatible = "nvidia,tegra186-amx",
0458 "nvidia,tegra210-amx";
0459 reg = <0x2903100 0x100>;
0460 sound-name-prefix = "AMX2";
0461 status = "disabled";
0462 };
0463
0464 tegra_amx3: amx@2903200 {
0465 compatible = "nvidia,tegra186-amx",
0466 "nvidia,tegra210-amx";
0467 reg = <0x2903200 0x100>;
0468 sound-name-prefix = "AMX3";
0469 status = "disabled";
0470 };
0471
0472 tegra_amx4: amx@2903300 {
0473 compatible = "nvidia,tegra186-amx",
0474 "nvidia,tegra210-amx";
0475 reg = <0x2903300 0x100>;
0476 sound-name-prefix = "AMX4";
0477 status = "disabled";
0478 };
0479
0480 tegra_adx1: adx@2903800 {
0481 compatible = "nvidia,tegra186-adx",
0482 "nvidia,tegra210-adx";
0483 reg = <0x2903800 0x100>;
0484 sound-name-prefix = "ADX1";
0485 status = "disabled";
0486 };
0487
0488 tegra_adx2: adx@2903900 {
0489 compatible = "nvidia,tegra186-adx",
0490 "nvidia,tegra210-adx";
0491 reg = <0x2903900 0x100>;
0492 sound-name-prefix = "ADX2";
0493 status = "disabled";
0494 };
0495
0496 tegra_adx3: adx@2903a00 {
0497 compatible = "nvidia,tegra186-adx",
0498 "nvidia,tegra210-adx";
0499 reg = <0x2903a00 0x100>;
0500 sound-name-prefix = "ADX3";
0501 status = "disabled";
0502 };
0503
0504 tegra_adx4: adx@2903b00 {
0505 compatible = "nvidia,tegra186-adx",
0506 "nvidia,tegra210-adx";
0507 reg = <0x2903b00 0x100>;
0508 sound-name-prefix = "ADX4";
0509 status = "disabled";
0510 };
0511
0512 tegra_ope1: processing-engine@2908000 {
0513 compatible = "nvidia,tegra186-ope",
0514 "nvidia,tegra210-ope";
0515 reg = <0x2908000 0x100>;
0516 #address-cells = <1>;
0517 #size-cells = <1>;
0518 ranges;
0519 sound-name-prefix = "OPE1";
0520 status = "disabled";
0521
0522 equalizer@2908100 {
0523 compatible = "nvidia,tegra186-peq",
0524 "nvidia,tegra210-peq";
0525 reg = <0x2908100 0x100>;
0526 };
0527
0528 dynamic-range-compressor@2908200 {
0529 compatible = "nvidia,tegra186-mbdrc",
0530 "nvidia,tegra210-mbdrc";
0531 reg = <0x2908200 0x200>;
0532 };
0533 };
0534
0535 tegra_amixer: amixer@290bb00 {
0536 compatible = "nvidia,tegra186-amixer",
0537 "nvidia,tegra210-amixer";
0538 reg = <0x290bb00 0x800>;
0539 sound-name-prefix = "MIXER1";
0540 status = "disabled";
0541 };
0542
0543 tegra_asrc: asrc@2910000 {
0544 compatible = "nvidia,tegra186-asrc";
0545 reg = <0x2910000 0x2000>;
0546 sound-name-prefix = "ASRC1";
0547 status = "disabled";
0548 };
0549 };
0550 };
0551
0552 mc: memory-controller@2c00000 {
0553 compatible = "nvidia,tegra186-mc";
0554 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
0555 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
0556 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
0557 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
0558 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
0559 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
0560 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
0561 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
0562 status = "disabled";
0563
0564 #interconnect-cells = <1>;
0565 #address-cells = <2>;
0566 #size-cells = <2>;
0567
0568 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
0569
0570 /*
0571 * Memory clients have access to all 40 bits that the memory
0572 * controller can address.
0573 */
0574 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
0575
0576 emc: external-memory-controller@2c60000 {
0577 compatible = "nvidia,tegra186-emc";
0578 reg = <0x0 0x02c60000 0x0 0x50000>;
0579 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
0580 clocks = <&bpmp TEGRA186_CLK_EMC>;
0581 clock-names = "emc";
0582
0583 #interconnect-cells = <0>;
0584
0585 nvidia,bpmp = <&bpmp>;
0586 };
0587 };
0588
0589 timer@3010000 {
0590 compatible = "nvidia,tegra186-timer";
0591 reg = <0x0 0x03010000 0x0 0x000e0000>;
0592 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0593 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0595 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0596 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0598 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0599 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0600 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0601 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0602 status = "okay";
0603 };
0604
0605 uarta: serial@3100000 {
0606 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
0607 reg = <0x0 0x03100000 0x0 0x40>;
0608 reg-shift = <2>;
0609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0610 clocks = <&bpmp TEGRA186_CLK_UARTA>;
0611 clock-names = "serial";
0612 resets = <&bpmp TEGRA186_RESET_UARTA>;
0613 reset-names = "serial";
0614 status = "disabled";
0615 };
0616
0617 uartb: serial@3110000 {
0618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
0619 reg = <0x0 0x03110000 0x0 0x40>;
0620 reg-shift = <2>;
0621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0622 clocks = <&bpmp TEGRA186_CLK_UARTB>;
0623 clock-names = "serial";
0624 resets = <&bpmp TEGRA186_RESET_UARTB>;
0625 reset-names = "serial";
0626 status = "disabled";
0627 };
0628
0629 uartd: serial@3130000 {
0630 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
0631 reg = <0x0 0x03130000 0x0 0x40>;
0632 reg-shift = <2>;
0633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0634 clocks = <&bpmp TEGRA186_CLK_UARTD>;
0635 clock-names = "serial";
0636 resets = <&bpmp TEGRA186_RESET_UARTD>;
0637 reset-names = "serial";
0638 status = "disabled";
0639 };
0640
0641 uarte: serial@3140000 {
0642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
0643 reg = <0x0 0x03140000 0x0 0x40>;
0644 reg-shift = <2>;
0645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0646 clocks = <&bpmp TEGRA186_CLK_UARTE>;
0647 clock-names = "serial";
0648 resets = <&bpmp TEGRA186_RESET_UARTE>;
0649 reset-names = "serial";
0650 status = "disabled";
0651 };
0652
0653 uartf: serial@3150000 {
0654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
0655 reg = <0x0 0x03150000 0x0 0x40>;
0656 reg-shift = <2>;
0657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0658 clocks = <&bpmp TEGRA186_CLK_UARTF>;
0659 clock-names = "serial";
0660 resets = <&bpmp TEGRA186_RESET_UARTF>;
0661 reset-names = "serial";
0662 status = "disabled";
0663 };
0664
0665 gen1_i2c: i2c@3160000 {
0666 compatible = "nvidia,tegra186-i2c";
0667 reg = <0x0 0x03160000 0x0 0x10000>;
0668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0669 #address-cells = <1>;
0670 #size-cells = <0>;
0671 clocks = <&bpmp TEGRA186_CLK_I2C1>;
0672 clock-names = "div-clk";
0673 resets = <&bpmp TEGRA186_RESET_I2C1>;
0674 reset-names = "i2c";
0675 status = "disabled";
0676 };
0677
0678 cam_i2c: i2c@3180000 {
0679 compatible = "nvidia,tegra186-i2c";
0680 reg = <0x0 0x03180000 0x0 0x10000>;
0681 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0682 #address-cells = <1>;
0683 #size-cells = <0>;
0684 clocks = <&bpmp TEGRA186_CLK_I2C3>;
0685 clock-names = "div-clk";
0686 resets = <&bpmp TEGRA186_RESET_I2C3>;
0687 reset-names = "i2c";
0688 status = "disabled";
0689 };
0690
0691 /* shares pads with dpaux1 */
0692 dp_aux_ch1_i2c: i2c@3190000 {
0693 compatible = "nvidia,tegra186-i2c";
0694 reg = <0x0 0x03190000 0x0 0x10000>;
0695 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0696 #address-cells = <1>;
0697 #size-cells = <0>;
0698 clocks = <&bpmp TEGRA186_CLK_I2C4>;
0699 clock-names = "div-clk";
0700 resets = <&bpmp TEGRA186_RESET_I2C4>;
0701 reset-names = "i2c";
0702 pinctrl-names = "default", "idle";
0703 pinctrl-0 = <&state_dpaux1_i2c>;
0704 pinctrl-1 = <&state_dpaux1_off>;
0705 status = "disabled";
0706 };
0707
0708 /* controlled by BPMP, should not be enabled */
0709 pwr_i2c: i2c@31a0000 {
0710 compatible = "nvidia,tegra186-i2c";
0711 reg = <0x0 0x031a0000 0x0 0x10000>;
0712 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0713 #address-cells = <1>;
0714 #size-cells = <0>;
0715 clocks = <&bpmp TEGRA186_CLK_I2C5>;
0716 clock-names = "div-clk";
0717 resets = <&bpmp TEGRA186_RESET_I2C5>;
0718 reset-names = "i2c";
0719 status = "disabled";
0720 };
0721
0722 /* shares pads with dpaux0 */
0723 dp_aux_ch0_i2c: i2c@31b0000 {
0724 compatible = "nvidia,tegra186-i2c";
0725 reg = <0x0 0x031b0000 0x0 0x10000>;
0726 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0727 #address-cells = <1>;
0728 #size-cells = <0>;
0729 clocks = <&bpmp TEGRA186_CLK_I2C6>;
0730 clock-names = "div-clk";
0731 resets = <&bpmp TEGRA186_RESET_I2C6>;
0732 reset-names = "i2c";
0733 pinctrl-names = "default", "idle";
0734 pinctrl-0 = <&state_dpaux_i2c>;
0735 pinctrl-1 = <&state_dpaux_off>;
0736 status = "disabled";
0737 };
0738
0739 gen7_i2c: i2c@31c0000 {
0740 compatible = "nvidia,tegra186-i2c";
0741 reg = <0x0 0x031c0000 0x0 0x10000>;
0742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0743 #address-cells = <1>;
0744 #size-cells = <0>;
0745 clocks = <&bpmp TEGRA186_CLK_I2C7>;
0746 clock-names = "div-clk";
0747 resets = <&bpmp TEGRA186_RESET_I2C7>;
0748 reset-names = "i2c";
0749 status = "disabled";
0750 };
0751
0752 gen9_i2c: i2c@31e0000 {
0753 compatible = "nvidia,tegra186-i2c";
0754 reg = <0x0 0x031e0000 0x0 0x10000>;
0755 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0756 #address-cells = <1>;
0757 #size-cells = <0>;
0758 clocks = <&bpmp TEGRA186_CLK_I2C9>;
0759 clock-names = "div-clk";
0760 resets = <&bpmp TEGRA186_RESET_I2C9>;
0761 reset-names = "i2c";
0762 status = "disabled";
0763 };
0764
0765 pwm1: pwm@3280000 {
0766 compatible = "nvidia,tegra186-pwm";
0767 reg = <0x0 0x3280000 0x0 0x10000>;
0768 clocks = <&bpmp TEGRA186_CLK_PWM1>;
0769 clock-names = "pwm";
0770 resets = <&bpmp TEGRA186_RESET_PWM1>;
0771 reset-names = "pwm";
0772 status = "disabled";
0773 #pwm-cells = <2>;
0774 };
0775
0776 pwm2: pwm@3290000 {
0777 compatible = "nvidia,tegra186-pwm";
0778 reg = <0x0 0x3290000 0x0 0x10000>;
0779 clocks = <&bpmp TEGRA186_CLK_PWM2>;
0780 clock-names = "pwm";
0781 resets = <&bpmp TEGRA186_RESET_PWM2>;
0782 reset-names = "pwm";
0783 status = "disabled";
0784 #pwm-cells = <2>;
0785 };
0786
0787 pwm3: pwm@32a0000 {
0788 compatible = "nvidia,tegra186-pwm";
0789 reg = <0x0 0x32a0000 0x0 0x10000>;
0790 clocks = <&bpmp TEGRA186_CLK_PWM3>;
0791 clock-names = "pwm";
0792 resets = <&bpmp TEGRA186_RESET_PWM3>;
0793 reset-names = "pwm";
0794 status = "disabled";
0795 #pwm-cells = <2>;
0796 };
0797
0798 pwm5: pwm@32c0000 {
0799 compatible = "nvidia,tegra186-pwm";
0800 reg = <0x0 0x32c0000 0x0 0x10000>;
0801 clocks = <&bpmp TEGRA186_CLK_PWM5>;
0802 clock-names = "pwm";
0803 resets = <&bpmp TEGRA186_RESET_PWM5>;
0804 reset-names = "pwm";
0805 status = "disabled";
0806 #pwm-cells = <2>;
0807 };
0808
0809 pwm6: pwm@32d0000 {
0810 compatible = "nvidia,tegra186-pwm";
0811 reg = <0x0 0x32d0000 0x0 0x10000>;
0812 clocks = <&bpmp TEGRA186_CLK_PWM6>;
0813 clock-names = "pwm";
0814 resets = <&bpmp TEGRA186_RESET_PWM6>;
0815 reset-names = "pwm";
0816 status = "disabled";
0817 #pwm-cells = <2>;
0818 };
0819
0820 pwm7: pwm@32e0000 {
0821 compatible = "nvidia,tegra186-pwm";
0822 reg = <0x0 0x32e0000 0x0 0x10000>;
0823 clocks = <&bpmp TEGRA186_CLK_PWM7>;
0824 clock-names = "pwm";
0825 resets = <&bpmp TEGRA186_RESET_PWM7>;
0826 reset-names = "pwm";
0827 status = "disabled";
0828 #pwm-cells = <2>;
0829 };
0830
0831 pwm8: pwm@32f0000 {
0832 compatible = "nvidia,tegra186-pwm";
0833 reg = <0x0 0x32f0000 0x0 0x10000>;
0834 clocks = <&bpmp TEGRA186_CLK_PWM8>;
0835 clock-names = "pwm";
0836 resets = <&bpmp TEGRA186_RESET_PWM8>;
0837 reset-names = "pwm";
0838 status = "disabled";
0839 #pwm-cells = <2>;
0840 };
0841
0842 sdmmc1: mmc@3400000 {
0843 compatible = "nvidia,tegra186-sdhci";
0844 reg = <0x0 0x03400000 0x0 0x10000>;
0845 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0846 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
0847 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
0848 clock-names = "sdhci", "tmclk";
0849 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
0850 reset-names = "sdhci";
0851 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
0852 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
0853 interconnect-names = "dma-mem", "write";
0854 iommus = <&smmu TEGRA186_SID_SDMMC1>;
0855 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
0856 pinctrl-0 = <&sdmmc1_3v3>;
0857 pinctrl-1 = <&sdmmc1_1v8>;
0858 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
0859 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
0860 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
0861 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
0862 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
0863 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
0864 nvidia,default-tap = <0x5>;
0865 nvidia,default-trim = <0xb>;
0866 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
0867 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
0868 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
0869 status = "disabled";
0870 };
0871
0872 sdmmc2: mmc@3420000 {
0873 compatible = "nvidia,tegra186-sdhci";
0874 reg = <0x0 0x03420000 0x0 0x10000>;
0875 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0876 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
0877 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
0878 clock-names = "sdhci", "tmclk";
0879 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
0880 reset-names = "sdhci";
0881 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
0882 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
0883 interconnect-names = "dma-mem", "write";
0884 iommus = <&smmu TEGRA186_SID_SDMMC2>;
0885 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
0886 pinctrl-0 = <&sdmmc2_3v3>;
0887 pinctrl-1 = <&sdmmc2_1v8>;
0888 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
0889 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
0890 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
0891 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
0892 nvidia,default-tap = <0x5>;
0893 nvidia,default-trim = <0xb>;
0894 status = "disabled";
0895 };
0896
0897 sdmmc3: mmc@3440000 {
0898 compatible = "nvidia,tegra186-sdhci";
0899 reg = <0x0 0x03440000 0x0 0x10000>;
0900 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0901 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
0902 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
0903 clock-names = "sdhci", "tmclk";
0904 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
0905 reset-names = "sdhci";
0906 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
0907 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
0908 interconnect-names = "dma-mem", "write";
0909 iommus = <&smmu TEGRA186_SID_SDMMC3>;
0910 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
0911 pinctrl-0 = <&sdmmc3_3v3>;
0912 pinctrl-1 = <&sdmmc3_1v8>;
0913 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
0914 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
0915 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
0916 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
0917 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
0918 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
0919 nvidia,default-tap = <0x5>;
0920 nvidia,default-trim = <0xb>;
0921 status = "disabled";
0922 };
0923
0924 sdmmc4: mmc@3460000 {
0925 compatible = "nvidia,tegra186-sdhci";
0926 reg = <0x0 0x03460000 0x0 0x10000>;
0927 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0928 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
0929 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
0930 clock-names = "sdhci", "tmclk";
0931 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
0932 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
0933 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
0934 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
0935 reset-names = "sdhci";
0936 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
0937 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
0938 interconnect-names = "dma-mem", "write";
0939 iommus = <&smmu TEGRA186_SID_SDMMC4>;
0940 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
0941 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
0942 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
0943 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
0944 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
0945 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
0946 nvidia,default-tap = <0x9>;
0947 nvidia,default-trim = <0x5>;
0948 nvidia,dqs-trim = <63>;
0949 mmc-hs400-1_8v;
0950 supports-cqe;
0951 status = "disabled";
0952 };
0953
0954 hda@3510000 {
0955 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
0956 reg = <0x0 0x03510000 0x0 0x10000>;
0957 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
0958 clocks = <&bpmp TEGRA186_CLK_HDA>,
0959 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
0960 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
0961 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
0962 resets = <&bpmp TEGRA186_RESET_HDA>,
0963 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
0964 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
0965 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
0966 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
0967 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
0968 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
0969 interconnect-names = "dma-mem", "write";
0970 iommus = <&smmu TEGRA186_SID_HDA>;
0971 status = "disabled";
0972 };
0973
0974 padctl: padctl@3520000 {
0975 compatible = "nvidia,tegra186-xusb-padctl";
0976 reg = <0x0 0x03520000 0x0 0x1000>,
0977 <0x0 0x03540000 0x0 0x1000>;
0978 reg-names = "padctl", "ao";
0979 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
0980
0981 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
0982 reset-names = "padctl";
0983
0984 status = "disabled";
0985
0986 pads {
0987 usb2 {
0988 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
0989 clock-names = "trk";
0990 status = "disabled";
0991
0992 lanes {
0993 usb2-0 {
0994 status = "disabled";
0995 #phy-cells = <0>;
0996 };
0997
0998 usb2-1 {
0999 status = "disabled";
1000 #phy-cells = <0>;
1001 };
1002
1003 usb2-2 {
1004 status = "disabled";
1005 #phy-cells = <0>;
1006 };
1007 };
1008 };
1009
1010 hsic {
1011 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1012 clock-names = "trk";
1013 status = "disabled";
1014
1015 lanes {
1016 hsic-0 {
1017 status = "disabled";
1018 #phy-cells = <0>;
1019 };
1020 };
1021 };
1022
1023 usb3 {
1024 status = "disabled";
1025
1026 lanes {
1027 usb3-0 {
1028 status = "disabled";
1029 #phy-cells = <0>;
1030 };
1031
1032 usb3-1 {
1033 status = "disabled";
1034 #phy-cells = <0>;
1035 };
1036
1037 usb3-2 {
1038 status = "disabled";
1039 #phy-cells = <0>;
1040 };
1041 };
1042 };
1043 };
1044
1045 ports {
1046 usb2-0 {
1047 status = "disabled";
1048 };
1049
1050 usb2-1 {
1051 status = "disabled";
1052 };
1053
1054 usb2-2 {
1055 status = "disabled";
1056 };
1057
1058 hsic-0 {
1059 status = "disabled";
1060 };
1061
1062 usb3-0 {
1063 status = "disabled";
1064 };
1065
1066 usb3-1 {
1067 status = "disabled";
1068 };
1069
1070 usb3-2 {
1071 status = "disabled";
1072 };
1073 };
1074 };
1075
1076 usb@3530000 {
1077 compatible = "nvidia,tegra186-xusb";
1078 reg = <0x0 0x03530000 0x0 0x8000>,
1079 <0x0 0x03538000 0x0 0x1000>;
1080 reg-names = "hcd", "fpci";
1081 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1082 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1084 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1085 <&bpmp TEGRA186_CLK_XUSB_SS>,
1086 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1087 <&bpmp TEGRA186_CLK_CLK_M>,
1088 <&bpmp TEGRA186_CLK_XUSB_FS>,
1089 <&bpmp TEGRA186_CLK_PLLU>,
1090 <&bpmp TEGRA186_CLK_CLK_M>,
1091 <&bpmp TEGRA186_CLK_PLLE>;
1092 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1093 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1094 "pll_u_480m", "clk_m", "pll_e";
1095 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1096 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1097 power-domain-names = "xusb_host", "xusb_ss";
1098 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1099 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1100 interconnect-names = "dma-mem", "write";
1101 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 status = "disabled";
1105
1106 nvidia,xusb-padctl = <&padctl>;
1107 };
1108
1109 usb@3550000 {
1110 compatible = "nvidia,tegra186-xudc";
1111 reg = <0x0 0x03550000 0x0 0x8000>,
1112 <0x0 0x03558000 0x0 0x1000>;
1113 reg-names = "base", "fpci";
1114 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1116 <&bpmp TEGRA186_CLK_XUSB_SS>,
1117 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1118 <&bpmp TEGRA186_CLK_XUSB_FS>;
1119 clock-names = "dev", "ss", "ss_src", "fs_src";
1120 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1121 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1122 interconnect-names = "dma-mem", "write";
1123 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1125 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1126 power-domain-names = "dev", "ss";
1127 nvidia,xusb-padctl = <&padctl>;
1128 status = "disabled";
1129 };
1130
1131 fuse@3820000 {
1132 compatible = "nvidia,tegra186-efuse";
1133 reg = <0x0 0x03820000 0x0 0x10000>;
1134 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1135 clock-names = "fuse";
1136 };
1137
1138 gic: interrupt-controller@3881000 {
1139 compatible = "arm,gic-400";
1140 #interrupt-cells = <3>;
1141 interrupt-controller;
1142 reg = <0x0 0x03881000 0x0 0x1000>,
1143 <0x0 0x03882000 0x0 0x2000>,
1144 <0x0 0x03884000 0x0 0x2000>,
1145 <0x0 0x03886000 0x0 0x2000>;
1146 interrupts = <GIC_PPI 9
1147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1148 interrupt-parent = <&gic>;
1149 };
1150
1151 cec@3960000 {
1152 compatible = "nvidia,tegra186-cec";
1153 reg = <0x0 0x03960000 0x0 0x10000>;
1154 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1155 clocks = <&bpmp TEGRA186_CLK_CEC>;
1156 clock-names = "cec";
1157 status = "disabled";
1158 };
1159
1160 hsp_top0: hsp@3c00000 {
1161 compatible = "nvidia,tegra186-hsp";
1162 reg = <0x0 0x03c00000 0x0 0xa0000>;
1163 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1164 interrupt-names = "doorbell";
1165 #mbox-cells = <2>;
1166 status = "disabled";
1167 };
1168
1169 gen2_i2c: i2c@c240000 {
1170 compatible = "nvidia,tegra186-i2c";
1171 reg = <0x0 0x0c240000 0x0 0x10000>;
1172 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1176 clock-names = "div-clk";
1177 resets = <&bpmp TEGRA186_RESET_I2C2>;
1178 reset-names = "i2c";
1179 status = "disabled";
1180 };
1181
1182 gen8_i2c: i2c@c250000 {
1183 compatible = "nvidia,tegra186-i2c";
1184 reg = <0x0 0x0c250000 0x0 0x10000>;
1185 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1189 clock-names = "div-clk";
1190 resets = <&bpmp TEGRA186_RESET_I2C8>;
1191 reset-names = "i2c";
1192 status = "disabled";
1193 };
1194
1195 uartc: serial@c280000 {
1196 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1197 reg = <0x0 0x0c280000 0x0 0x40>;
1198 reg-shift = <2>;
1199 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1201 clock-names = "serial";
1202 resets = <&bpmp TEGRA186_RESET_UARTC>;
1203 reset-names = "serial";
1204 status = "disabled";
1205 };
1206
1207 uartg: serial@c290000 {
1208 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1209 reg = <0x0 0x0c290000 0x0 0x40>;
1210 reg-shift = <2>;
1211 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1212 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1213 clock-names = "serial";
1214 resets = <&bpmp TEGRA186_RESET_UARTG>;
1215 reset-names = "serial";
1216 status = "disabled";
1217 };
1218
1219 rtc: rtc@c2a0000 {
1220 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1221 reg = <0 0x0c2a0000 0 0x10000>;
1222 interrupt-parent = <&pmc>;
1223 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1225 clock-names = "rtc";
1226 status = "disabled";
1227 };
1228
1229 gpio_aon: gpio@c2f0000 {
1230 compatible = "nvidia,tegra186-gpio-aon";
1231 reg-names = "security", "gpio";
1232 reg = <0x0 0xc2f0000 0x0 0x1000>,
1233 <0x0 0xc2f1000 0x0 0x1000>;
1234 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1235 gpio-controller;
1236 #gpio-cells = <2>;
1237 interrupt-controller;
1238 #interrupt-cells = <2>;
1239 };
1240
1241 pwm4: pwm@c340000 {
1242 compatible = "nvidia,tegra186-pwm";
1243 reg = <0x0 0xc340000 0x0 0x10000>;
1244 clocks = <&bpmp TEGRA186_CLK_PWM4>;
1245 clock-names = "pwm";
1246 resets = <&bpmp TEGRA186_RESET_PWM4>;
1247 reset-names = "pwm";
1248 status = "disabled";
1249 #pwm-cells = <2>;
1250 };
1251
1252 pmc: pmc@c360000 {
1253 compatible = "nvidia,tegra186-pmc";
1254 reg = <0 0x0c360000 0 0x10000>,
1255 <0 0x0c370000 0 0x10000>,
1256 <0 0x0c380000 0 0x10000>,
1257 <0 0x0c390000 0 0x10000>;
1258 reg-names = "pmc", "wake", "aotag", "scratch";
1259
1260 #interrupt-cells = <2>;
1261 interrupt-controller;
1262
1263 sdmmc1_3v3: sdmmc1-3v3 {
1264 pins = "sdmmc1-hv";
1265 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1266 };
1267
1268 sdmmc1_1v8: sdmmc1-1v8 {
1269 pins = "sdmmc1-hv";
1270 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1271 };
1272
1273 sdmmc2_3v3: sdmmc2-3v3 {
1274 pins = "sdmmc2-hv";
1275 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1276 };
1277
1278 sdmmc2_1v8: sdmmc2-1v8 {
1279 pins = "sdmmc2-hv";
1280 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1281 };
1282
1283 sdmmc3_3v3: sdmmc3-3v3 {
1284 pins = "sdmmc3-hv";
1285 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1286 };
1287
1288 sdmmc3_1v8: sdmmc3-1v8 {
1289 pins = "sdmmc3-hv";
1290 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1291 };
1292 };
1293
1294 ccplex@e000000 {
1295 compatible = "nvidia,tegra186-ccplex-cluster";
1296 reg = <0x0 0x0e000000 0x0 0x400000>;
1297
1298 nvidia,bpmp = <&bpmp>;
1299 };
1300
1301 pcie@10003000 {
1302 compatible = "nvidia,tegra186-pcie";
1303 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1304 device_type = "pci";
1305 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1306 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1307 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1308 reg-names = "pads", "afi", "cs";
1309
1310 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1311 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1312 interrupt-names = "intr", "msi";
1313
1314 #interrupt-cells = <1>;
1315 interrupt-map-mask = <0 0 0 0>;
1316 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1317
1318 bus-range = <0x00 0xff>;
1319 #address-cells = <3>;
1320 #size-cells = <2>;
1321
1322 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1323 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1324 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1325 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1326 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1327 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1328
1329 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1330 <&bpmp TEGRA186_CLK_AFI>,
1331 <&bpmp TEGRA186_CLK_PLLE>;
1332 clock-names = "pex", "afi", "pll_e";
1333
1334 resets = <&bpmp TEGRA186_RESET_PCIE>,
1335 <&bpmp TEGRA186_RESET_AFI>,
1336 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1337 reset-names = "pex", "afi", "pcie_x";
1338
1339 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1340 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1341 interconnect-names = "dma-mem", "write";
1342
1343 iommus = <&smmu TEGRA186_SID_AFI>;
1344 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1345 iommu-map-mask = <0x0>;
1346
1347 status = "disabled";
1348
1349 pci@1,0 {
1350 device_type = "pci";
1351 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1352 reg = <0x000800 0 0 0 0>;
1353 status = "disabled";
1354
1355 #address-cells = <3>;
1356 #size-cells = <2>;
1357 ranges;
1358
1359 nvidia,num-lanes = <2>;
1360 };
1361
1362 pci@2,0 {
1363 device_type = "pci";
1364 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1365 reg = <0x001000 0 0 0 0>;
1366 status = "disabled";
1367
1368 #address-cells = <3>;
1369 #size-cells = <2>;
1370 ranges;
1371
1372 nvidia,num-lanes = <1>;
1373 };
1374
1375 pci@3,0 {
1376 device_type = "pci";
1377 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1378 reg = <0x001800 0 0 0 0>;
1379 status = "disabled";
1380
1381 #address-cells = <3>;
1382 #size-cells = <2>;
1383 ranges;
1384
1385 nvidia,num-lanes = <1>;
1386 };
1387 };
1388
1389 smmu: iommu@12000000 {
1390 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1391 reg = <0 0x12000000 0 0x800000>;
1392 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1457 stream-match-mask = <0x7f80>;
1458 #global-interrupts = <1>;
1459 #iommu-cells = <1>;
1460
1461 nvidia,memory-controller = <&mc>;
1462 };
1463
1464 host1x@13e00000 {
1465 compatible = "nvidia,tegra186-host1x";
1466 reg = <0x0 0x13e00000 0x0 0x10000>,
1467 <0x0 0x13e10000 0x0 0x10000>;
1468 reg-names = "hypervisor", "vm";
1469 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1471 interrupt-names = "syncpt", "host1x";
1472 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1473 clock-names = "host1x";
1474 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1475 reset-names = "host1x";
1476
1477 #address-cells = <1>;
1478 #size-cells = <1>;
1479
1480 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1481
1482 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1483 interconnect-names = "dma-mem";
1484
1485 iommus = <&smmu TEGRA186_SID_HOST1X>;
1486
1487 /* Context isolation domains */
1488 iommu-map = <
1489 0 &smmu TEGRA186_SID_HOST1X_CTX0 1
1490 1 &smmu TEGRA186_SID_HOST1X_CTX1 1
1491 2 &smmu TEGRA186_SID_HOST1X_CTX2 1
1492 3 &smmu TEGRA186_SID_HOST1X_CTX3 1
1493 4 &smmu TEGRA186_SID_HOST1X_CTX4 1
1494 5 &smmu TEGRA186_SID_HOST1X_CTX5 1
1495 6 &smmu TEGRA186_SID_HOST1X_CTX6 1
1496 7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
1497
1498 dpaux1: dpaux@15040000 {
1499 compatible = "nvidia,tegra186-dpaux";
1500 reg = <0x15040000 0x10000>;
1501 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1503 <&bpmp TEGRA186_CLK_PLLDP>;
1504 clock-names = "dpaux", "parent";
1505 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1506 reset-names = "dpaux";
1507 status = "disabled";
1508
1509 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1510
1511 state_dpaux1_aux: pinmux-aux {
1512 groups = "dpaux-io";
1513 function = "aux";
1514 };
1515
1516 state_dpaux1_i2c: pinmux-i2c {
1517 groups = "dpaux-io";
1518 function = "i2c";
1519 };
1520
1521 state_dpaux1_off: pinmux-off {
1522 groups = "dpaux-io";
1523 function = "off";
1524 };
1525
1526 i2c-bus {
1527 #address-cells = <1>;
1528 #size-cells = <0>;
1529 };
1530 };
1531
1532 display-hub@15200000 {
1533 compatible = "nvidia,tegra186-display";
1534 reg = <0x15200000 0x00040000>;
1535 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1536 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1537 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1538 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1539 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1540 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1541 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1542 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1543 "wgrp3", "wgrp4", "wgrp5";
1544 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1545 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1546 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1547 clock-names = "disp", "dsc", "hub";
1548 status = "disabled";
1549
1550 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1551
1552 #address-cells = <1>;
1553 #size-cells = <1>;
1554
1555 ranges = <0x15200000 0x15200000 0x40000>;
1556
1557 display@15200000 {
1558 compatible = "nvidia,tegra186-dc";
1559 reg = <0x15200000 0x10000>;
1560 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1561 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1562 clock-names = "dc";
1563 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1564 reset-names = "dc";
1565
1566 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1567 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1568 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1569 interconnect-names = "dma-mem", "read-1";
1570 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1571
1572 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1573 nvidia,head = <0>;
1574 };
1575
1576 display@15210000 {
1577 compatible = "nvidia,tegra186-dc";
1578 reg = <0x15210000 0x10000>;
1579 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1580 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1581 clock-names = "dc";
1582 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1583 reset-names = "dc";
1584
1585 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1586 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1587 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1588 interconnect-names = "dma-mem", "read-1";
1589 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1590
1591 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1592 nvidia,head = <1>;
1593 };
1594
1595 display@15220000 {
1596 compatible = "nvidia,tegra186-dc";
1597 reg = <0x15220000 0x10000>;
1598 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1599 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1600 clock-names = "dc";
1601 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1602 reset-names = "dc";
1603
1604 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1605 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1606 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1607 interconnect-names = "dma-mem", "read-1";
1608 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1609
1610 nvidia,outputs = <&sor0 &sor1>;
1611 nvidia,head = <2>;
1612 };
1613 };
1614
1615 dsia: dsi@15300000 {
1616 compatible = "nvidia,tegra186-dsi";
1617 reg = <0x15300000 0x10000>;
1618 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1619 clocks = <&bpmp TEGRA186_CLK_DSI>,
1620 <&bpmp TEGRA186_CLK_DSIA_LP>,
1621 <&bpmp TEGRA186_CLK_PLLD>;
1622 clock-names = "dsi", "lp", "parent";
1623 resets = <&bpmp TEGRA186_RESET_DSI>;
1624 reset-names = "dsi";
1625 status = "disabled";
1626
1627 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1628 };
1629
1630 vic@15340000 {
1631 compatible = "nvidia,tegra186-vic";
1632 reg = <0x15340000 0x40000>;
1633 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1634 clocks = <&bpmp TEGRA186_CLK_VIC>;
1635 clock-names = "vic";
1636 resets = <&bpmp TEGRA186_RESET_VIC>;
1637 reset-names = "vic";
1638
1639 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1640 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1641 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1642 interconnect-names = "dma-mem", "write";
1643 iommus = <&smmu TEGRA186_SID_VIC>;
1644 };
1645
1646 nvjpg@15380000 {
1647 compatible = "nvidia,tegra186-nvjpg";
1648 reg = <0x15380000 0x40000>;
1649 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1650 clock-names = "nvjpg";
1651 resets = <&bpmp TEGRA186_RESET_NVJPG>;
1652 reset-names = "nvjpg";
1653
1654 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1655 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
1656 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
1657 interconnect-names = "dma-mem", "write";
1658 iommus = <&smmu TEGRA186_SID_NVJPG>;
1659 };
1660
1661 dsib: dsi@15400000 {
1662 compatible = "nvidia,tegra186-dsi";
1663 reg = <0x15400000 0x10000>;
1664 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1665 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1666 <&bpmp TEGRA186_CLK_DSIB_LP>,
1667 <&bpmp TEGRA186_CLK_PLLD>;
1668 clock-names = "dsi", "lp", "parent";
1669 resets = <&bpmp TEGRA186_RESET_DSIB>;
1670 reset-names = "dsi";
1671 status = "disabled";
1672
1673 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1674 };
1675
1676 nvdec@15480000 {
1677 compatible = "nvidia,tegra186-nvdec";
1678 reg = <0x15480000 0x40000>;
1679 clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1680 clock-names = "nvdec";
1681 resets = <&bpmp TEGRA186_RESET_NVDEC>;
1682 reset-names = "nvdec";
1683
1684 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1685 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1686 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1687 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1688 interconnect-names = "dma-mem", "read-1", "write";
1689 iommus = <&smmu TEGRA186_SID_NVDEC>;
1690 };
1691
1692 nvenc@154c0000 {
1693 compatible = "nvidia,tegra186-nvenc";
1694 reg = <0x154c0000 0x40000>;
1695 clocks = <&bpmp TEGRA186_CLK_NVENC>;
1696 clock-names = "nvenc";
1697 resets = <&bpmp TEGRA186_RESET_NVENC>;
1698 reset-names = "nvenc";
1699
1700 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1701 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
1702 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
1703 interconnect-names = "dma-mem", "write";
1704 iommus = <&smmu TEGRA186_SID_NVENC>;
1705 };
1706
1707 sor0: sor@15540000 {
1708 compatible = "nvidia,tegra186-sor";
1709 reg = <0x15540000 0x10000>;
1710 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1711 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1712 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1713 <&bpmp TEGRA186_CLK_PLLD2>,
1714 <&bpmp TEGRA186_CLK_PLLDP>,
1715 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1716 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1717 clock-names = "sor", "out", "parent", "dp", "safe",
1718 "pad";
1719 resets = <&bpmp TEGRA186_RESET_SOR0>;
1720 reset-names = "sor";
1721 pinctrl-0 = <&state_dpaux_aux>;
1722 pinctrl-1 = <&state_dpaux_i2c>;
1723 pinctrl-2 = <&state_dpaux_off>;
1724 pinctrl-names = "aux", "i2c", "off";
1725 status = "disabled";
1726
1727 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1728 nvidia,interface = <0>;
1729 };
1730
1731 sor1: sor@15580000 {
1732 compatible = "nvidia,tegra186-sor";
1733 reg = <0x15580000 0x10000>;
1734 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1735 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1736 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1737 <&bpmp TEGRA186_CLK_PLLD3>,
1738 <&bpmp TEGRA186_CLK_PLLDP>,
1739 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1740 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1741 clock-names = "sor", "out", "parent", "dp", "safe",
1742 "pad";
1743 resets = <&bpmp TEGRA186_RESET_SOR1>;
1744 reset-names = "sor";
1745 pinctrl-0 = <&state_dpaux1_aux>;
1746 pinctrl-1 = <&state_dpaux1_i2c>;
1747 pinctrl-2 = <&state_dpaux1_off>;
1748 pinctrl-names = "aux", "i2c", "off";
1749 status = "disabled";
1750
1751 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1752 nvidia,interface = <1>;
1753 };
1754
1755 dpaux: dpaux@155c0000 {
1756 compatible = "nvidia,tegra186-dpaux";
1757 reg = <0x155c0000 0x10000>;
1758 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1760 <&bpmp TEGRA186_CLK_PLLDP>;
1761 clock-names = "dpaux", "parent";
1762 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1763 reset-names = "dpaux";
1764 status = "disabled";
1765
1766 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1767
1768 state_dpaux_aux: pinmux-aux {
1769 groups = "dpaux-io";
1770 function = "aux";
1771 };
1772
1773 state_dpaux_i2c: pinmux-i2c {
1774 groups = "dpaux-io";
1775 function = "i2c";
1776 };
1777
1778 state_dpaux_off: pinmux-off {
1779 groups = "dpaux-io";
1780 function = "off";
1781 };
1782
1783 i2c-bus {
1784 #address-cells = <1>;
1785 #size-cells = <0>;
1786 };
1787 };
1788
1789 padctl@15880000 {
1790 compatible = "nvidia,tegra186-dsi-padctl";
1791 reg = <0x15880000 0x10000>;
1792 resets = <&bpmp TEGRA186_RESET_DSI>;
1793 reset-names = "dsi";
1794 status = "disabled";
1795 };
1796
1797 dsic: dsi@15900000 {
1798 compatible = "nvidia,tegra186-dsi";
1799 reg = <0x15900000 0x10000>;
1800 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1801 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1802 <&bpmp TEGRA186_CLK_DSIC_LP>,
1803 <&bpmp TEGRA186_CLK_PLLD>;
1804 clock-names = "dsi", "lp", "parent";
1805 resets = <&bpmp TEGRA186_RESET_DSIC>;
1806 reset-names = "dsi";
1807 status = "disabled";
1808
1809 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1810 };
1811
1812 dsid: dsi@15940000 {
1813 compatible = "nvidia,tegra186-dsi";
1814 reg = <0x15940000 0x10000>;
1815 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1816 clocks = <&bpmp TEGRA186_CLK_DSID>,
1817 <&bpmp TEGRA186_CLK_DSID_LP>,
1818 <&bpmp TEGRA186_CLK_PLLD>;
1819 clock-names = "dsi", "lp", "parent";
1820 resets = <&bpmp TEGRA186_RESET_DSID>;
1821 reset-names = "dsi";
1822 status = "disabled";
1823
1824 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1825 };
1826 };
1827
1828 gpu@17000000 {
1829 compatible = "nvidia,gp10b";
1830 reg = <0x0 0x17000000 0x0 0x1000000>,
1831 <0x0 0x18000000 0x0 0x1000000>;
1832 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1834 interrupt-names = "stall", "nonstall";
1835
1836 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1837 <&bpmp TEGRA186_CLK_GPU>;
1838 clock-names = "gpu", "pwr";
1839 resets = <&bpmp TEGRA186_RESET_GPU>;
1840 reset-names = "gpu";
1841 status = "disabled";
1842
1843 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1844 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1845 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1846 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1847 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1848 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1849 };
1850
1851 sram@30000000 {
1852 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1853 reg = <0x0 0x30000000 0x0 0x50000>;
1854 #address-cells = <1>;
1855 #size-cells = <1>;
1856 ranges = <0x0 0x0 0x30000000 0x50000>;
1857 no-memory-wc;
1858
1859 cpu_bpmp_tx: sram@4e000 {
1860 reg = <0x4e000 0x1000>;
1861 label = "cpu-bpmp-tx";
1862 pool;
1863 };
1864
1865 cpu_bpmp_rx: sram@4f000 {
1866 reg = <0x4f000 0x1000>;
1867 label = "cpu-bpmp-rx";
1868 pool;
1869 };
1870 };
1871
1872 sata@3507000 {
1873 compatible = "nvidia,tegra186-ahci";
1874 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1875 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1876 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1877 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1878
1879 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1880 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1881 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1882 interconnect-names = "dma-mem", "write";
1883 iommus = <&smmu TEGRA186_SID_SATA>;
1884
1885 clocks = <&bpmp TEGRA186_CLK_SATA>,
1886 <&bpmp TEGRA186_CLK_SATA_OOB>;
1887 clock-names = "sata", "sata-oob";
1888 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1889 <&bpmp TEGRA186_CLK_SATA_OOB>;
1890 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1891 <&bpmp TEGRA186_CLK_PLLP>;
1892 assigned-clock-rates = <102000000>,
1893 <204000000>;
1894 resets = <&bpmp TEGRA186_RESET_SATA>,
1895 <&bpmp TEGRA186_RESET_SATACOLD>;
1896 reset-names = "sata", "sata-cold";
1897 status = "disabled";
1898 };
1899
1900 bpmp: bpmp {
1901 compatible = "nvidia,tegra186-bpmp";
1902 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1903 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1904 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1905 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1906 interconnect-names = "read", "write", "dma-mem", "dma-write";
1907 iommus = <&smmu TEGRA186_SID_BPMP>;
1908 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1909 TEGRA_HSP_DB_MASTER_BPMP>;
1910 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
1911 #clock-cells = <1>;
1912 #reset-cells = <1>;
1913 #power-domain-cells = <1>;
1914
1915 bpmp_i2c: i2c {
1916 compatible = "nvidia,tegra186-bpmp-i2c";
1917 nvidia,bpmp-bus-id = <5>;
1918 #address-cells = <1>;
1919 #size-cells = <0>;
1920 status = "disabled";
1921 };
1922
1923 bpmp_thermal: thermal {
1924 compatible = "nvidia,tegra186-bpmp-thermal";
1925 #thermal-sensor-cells = <1>;
1926 };
1927 };
1928
1929 cpus {
1930 #address-cells = <1>;
1931 #size-cells = <0>;
1932
1933 denver_0: cpu@0 {
1934 compatible = "nvidia,tegra186-denver";
1935 device_type = "cpu";
1936 i-cache-size = <0x20000>;
1937 i-cache-line-size = <64>;
1938 i-cache-sets = <512>;
1939 d-cache-size = <0x10000>;
1940 d-cache-line-size = <64>;
1941 d-cache-sets = <256>;
1942 next-level-cache = <&L2_DENVER>;
1943 reg = <0x000>;
1944 };
1945
1946 denver_1: cpu@1 {
1947 compatible = "nvidia,tegra186-denver";
1948 device_type = "cpu";
1949 i-cache-size = <0x20000>;
1950 i-cache-line-size = <64>;
1951 i-cache-sets = <512>;
1952 d-cache-size = <0x10000>;
1953 d-cache-line-size = <64>;
1954 d-cache-sets = <256>;
1955 next-level-cache = <&L2_DENVER>;
1956 reg = <0x001>;
1957 };
1958
1959 ca57_0: cpu@2 {
1960 compatible = "arm,cortex-a57";
1961 device_type = "cpu";
1962 i-cache-size = <0xC000>;
1963 i-cache-line-size = <64>;
1964 i-cache-sets = <256>;
1965 d-cache-size = <0x8000>;
1966 d-cache-line-size = <64>;
1967 d-cache-sets = <256>;
1968 next-level-cache = <&L2_A57>;
1969 reg = <0x100>;
1970 };
1971
1972 ca57_1: cpu@3 {
1973 compatible = "arm,cortex-a57";
1974 device_type = "cpu";
1975 i-cache-size = <0xC000>;
1976 i-cache-line-size = <64>;
1977 i-cache-sets = <256>;
1978 d-cache-size = <0x8000>;
1979 d-cache-line-size = <64>;
1980 d-cache-sets = <256>;
1981 next-level-cache = <&L2_A57>;
1982 reg = <0x101>;
1983 };
1984
1985 ca57_2: cpu@4 {
1986 compatible = "arm,cortex-a57";
1987 device_type = "cpu";
1988 i-cache-size = <0xC000>;
1989 i-cache-line-size = <64>;
1990 i-cache-sets = <256>;
1991 d-cache-size = <0x8000>;
1992 d-cache-line-size = <64>;
1993 d-cache-sets = <256>;
1994 next-level-cache = <&L2_A57>;
1995 reg = <0x102>;
1996 };
1997
1998 ca57_3: cpu@5 {
1999 compatible = "arm,cortex-a57";
2000 device_type = "cpu";
2001 i-cache-size = <0xC000>;
2002 i-cache-line-size = <64>;
2003 i-cache-sets = <256>;
2004 d-cache-size = <0x8000>;
2005 d-cache-line-size = <64>;
2006 d-cache-sets = <256>;
2007 next-level-cache = <&L2_A57>;
2008 reg = <0x103>;
2009 };
2010
2011 L2_DENVER: l2-cache0 {
2012 compatible = "cache";
2013 cache-unified;
2014 cache-level = <2>;
2015 cache-size = <0x200000>;
2016 cache-line-size = <64>;
2017 cache-sets = <2048>;
2018 };
2019
2020 L2_A57: l2-cache1 {
2021 compatible = "cache";
2022 cache-unified;
2023 cache-level = <2>;
2024 cache-size = <0x200000>;
2025 cache-line-size = <64>;
2026 cache-sets = <2048>;
2027 };
2028 };
2029
2030 pmu_denver {
2031 compatible = "nvidia,denver-pmu";
2032 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2034 interrupt-affinity = <&denver_0 &denver_1>;
2035 };
2036
2037 pmu_a57 {
2038 compatible = "arm,cortex-a57-pmu";
2039 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2043 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2044 };
2045
2046 sound {
2047 status = "disabled";
2048
2049 clocks = <&bpmp TEGRA186_CLK_PLLA>,
2050 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2051 clock-names = "pll_a", "plla_out0";
2052 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2053 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2054 <&bpmp TEGRA186_CLK_AUD_MCLK>;
2055 assigned-clock-parents = <0>,
2056 <&bpmp TEGRA186_CLK_PLLA>,
2057 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2058 /*
2059 * PLLA supports dynamic ramp. Below initial rate is chosen
2060 * for this to work and oscillate between base rates required
2061 * for 8x and 11.025x sample rate streams.
2062 */
2063 assigned-clock-rates = <258000000>;
2064
2065 iommus = <&smmu TEGRA186_SID_APE>;
2066 };
2067
2068 thermal-zones {
2069 /* Cortex-A57 cluster */
2070 cpu-thermal {
2071 polling-delay = <0>;
2072 polling-delay-passive = <1000>;
2073
2074 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2075
2076 trips {
2077 critical {
2078 temperature = <101000>;
2079 hysteresis = <0>;
2080 type = "critical";
2081 };
2082 };
2083
2084 cooling-maps {
2085 };
2086 };
2087
2088 /* Denver cluster */
2089 aux-thermal {
2090 polling-delay = <0>;
2091 polling-delay-passive = <1000>;
2092
2093 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2094
2095 trips {
2096 critical {
2097 temperature = <101000>;
2098 hysteresis = <0>;
2099 type = "critical";
2100 };
2101 };
2102
2103 cooling-maps {
2104 };
2105 };
2106
2107 gpu-thermal {
2108 polling-delay = <0>;
2109 polling-delay-passive = <1000>;
2110
2111 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2112
2113 trips {
2114 critical {
2115 temperature = <101000>;
2116 hysteresis = <0>;
2117 type = "critical";
2118 };
2119 };
2120
2121 cooling-maps {
2122 };
2123 };
2124
2125 pll-thermal {
2126 polling-delay = <0>;
2127 polling-delay-passive = <1000>;
2128
2129 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2130
2131 trips {
2132 critical {
2133 temperature = <101000>;
2134 hysteresis = <0>;
2135 type = "critical";
2136 };
2137 };
2138
2139 cooling-maps {
2140 };
2141 };
2142
2143 ao-thermal {
2144 polling-delay = <0>;
2145 polling-delay-passive = <1000>;
2146
2147 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2148
2149 trips {
2150 critical {
2151 temperature = <101000>;
2152 hysteresis = <0>;
2153 type = "critical";
2154 };
2155 };
2156
2157 cooling-maps {
2158 };
2159 };
2160 };
2161
2162 timer {
2163 compatible = "arm,armv8-timer";
2164 interrupts = <GIC_PPI 13
2165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2166 <GIC_PPI 14
2167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2168 <GIC_PPI 11
2169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2170 <GIC_PPI 10
2171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2172 interrupt-parent = <&gic>;
2173 always-on;
2174 };
2175 };
