OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/input/linux-event-codes.h>
0005 #include <dt-bindings/input/gpio-keys.h>
0006
0007 #include "tegra186-p3310.dtsi"
0008
0009 / {
0010 model = "NVIDIA Jetson TX2 Developer Kit";
0011 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
0012
0013 aconnect@2900000 {
0014 status = "okay";
0015
0016 dma-controller@2930000 {
0017 status = "okay";
0018 };
0019
0020 interrupt-controller@2a40000 {
0021 status = "okay";
0022 };
0023
0024 ahub@2900800 {
0025 status = "okay";
0026
0027 ports {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 port@0 {
0032 reg = <0x0>;
0033
0034 xbar_admaif0_ep: endpoint {
0035 remote-endpoint = <&admaif0_ep>;
0036 };
0037 };
0038
0039 port@1 {
0040 reg = <0x1>;
0041
0042 xbar_admaif1_ep: endpoint {
0043 remote-endpoint = <&admaif1_ep>;
0044 };
0045 };
0046
0047 port@2 {
0048 reg = <0x2>;
0049
0050 xbar_admaif2_ep: endpoint {
0051 remote-endpoint = <&admaif2_ep>;
0052 };
0053 };
0054
0055 port@3 {
0056 reg = <0x3>;
0057
0058 xbar_admaif3_ep: endpoint {
0059 remote-endpoint = <&admaif3_ep>;
0060 };
0061 };
0062
0063 port@4 {
0064 reg = <0x4>;
0065
0066 xbar_admaif4_ep: endpoint {
0067 remote-endpoint = <&admaif4_ep>;
0068 };
0069 };
0070
0071 port@5 {
0072 reg = <0x5>;
0073
0074 xbar_admaif5_ep: endpoint {
0075 remote-endpoint = <&admaif5_ep>;
0076 };
0077 };
0078
0079 port@6 {
0080 reg = <0x6>;
0081
0082 xbar_admaif6_ep: endpoint {
0083 remote-endpoint = <&admaif6_ep>;
0084 };
0085 };
0086
0087 port@7 {
0088 reg = <0x7>;
0089
0090 xbar_admaif7_ep: endpoint {
0091 remote-endpoint = <&admaif7_ep>;
0092 };
0093 };
0094
0095 port@8 {
0096 reg = <0x8>;
0097
0098 xbar_admaif8_ep: endpoint {
0099 remote-endpoint = <&admaif8_ep>;
0100 };
0101 };
0102
0103 port@9 {
0104 reg = <0x9>;
0105
0106 xbar_admaif9_ep: endpoint {
0107 remote-endpoint = <&admaif9_ep>;
0108 };
0109 };
0110
0111 port@a {
0112 reg = <0xa>;
0113
0114 xbar_admaif10_ep: endpoint {
0115 remote-endpoint = <&admaif10_ep>;
0116 };
0117 };
0118
0119 port@b {
0120 reg = <0xb>;
0121
0122 xbar_admaif11_ep: endpoint {
0123 remote-endpoint = <&admaif11_ep>;
0124 };
0125 };
0126
0127 port@c {
0128 reg = <0xc>;
0129
0130 xbar_admaif12_ep: endpoint {
0131 remote-endpoint = <&admaif12_ep>;
0132 };
0133 };
0134
0135 port@d {
0136 reg = <0xd>;
0137
0138 xbar_admaif13_ep: endpoint {
0139 remote-endpoint = <&admaif13_ep>;
0140 };
0141 };
0142
0143 port@e {
0144 reg = <0xe>;
0145
0146 xbar_admaif14_ep: endpoint {
0147 remote-endpoint = <&admaif14_ep>;
0148 };
0149 };
0150
0151 port@f {
0152 reg = <0xf>;
0153
0154 xbar_admaif15_ep: endpoint {
0155 remote-endpoint = <&admaif15_ep>;
0156 };
0157 };
0158
0159 port@10 {
0160 reg = <0x10>;
0161
0162 xbar_admaif16_ep: endpoint {
0163 remote-endpoint = <&admaif16_ep>;
0164 };
0165 };
0166
0167 port@11 {
0168 reg = <0x11>;
0169
0170 xbar_admaif17_ep: endpoint {
0171 remote-endpoint = <&admaif17_ep>;
0172 };
0173 };
0174
0175 port@12 {
0176 reg = <0x12>;
0177
0178 xbar_admaif18_ep: endpoint {
0179 remote-endpoint = <&admaif18_ep>;
0180 };
0181 };
0182
0183 port@13 {
0184 reg = <0x13>;
0185
0186 xbar_admaif19_ep: endpoint {
0187 remote-endpoint = <&admaif19_ep>;
0188 };
0189 };
0190
0191 xbar_i2s1_port: port@14 {
0192 reg = <0x14>;
0193
0194 xbar_i2s1_ep: endpoint {
0195 remote-endpoint = <&i2s1_cif_ep>;
0196 };
0197 };
0198
0199 xbar_i2s2_port: port@15 {
0200 reg = <0x15>;
0201
0202 xbar_i2s2_ep: endpoint {
0203 remote-endpoint = <&i2s2_cif_ep>;
0204 };
0205 };
0206
0207 xbar_i2s3_port: port@16 {
0208 reg = <0x16>;
0209
0210 xbar_i2s3_ep: endpoint {
0211 remote-endpoint = <&i2s3_cif_ep>;
0212 };
0213 };
0214
0215 xbar_i2s4_port: port@17 {
0216 reg = <0x17>;
0217
0218 xbar_i2s4_ep: endpoint {
0219 remote-endpoint = <&i2s4_cif_ep>;
0220 };
0221 };
0222
0223 xbar_i2s5_port: port@18 {
0224 reg = <0x18>;
0225
0226 xbar_i2s5_ep: endpoint {
0227 remote-endpoint = <&i2s5_cif_ep>;
0228 };
0229 };
0230
0231 xbar_i2s6_port: port@19 {
0232 reg = <0x19>;
0233
0234 xbar_i2s6_ep: endpoint {
0235 remote-endpoint = <&i2s6_cif_ep>;
0236 };
0237 };
0238
0239 xbar_dmic1_port: port@1a {
0240 reg = <0x1a>;
0241
0242 xbar_dmic1_ep: endpoint {
0243 remote-endpoint = <&dmic1_cif_ep>;
0244 };
0245 };
0246
0247 xbar_dmic2_port: port@1b {
0248 reg = <0x1b>;
0249
0250 xbar_dmic2_ep: endpoint {
0251 remote-endpoint = <&dmic2_cif_ep>;
0252 };
0253 };
0254
0255 xbar_dmic3_port: port@1c {
0256 reg = <0x1c>;
0257
0258 xbar_dmic3_ep: endpoint {
0259 remote-endpoint = <&dmic3_cif_ep>;
0260 };
0261 };
0262
0263 xbar_dspk1_port: port@1e {
0264 reg = <0x1e>;
0265
0266 xbar_dspk1_ep: endpoint {
0267 remote-endpoint = <&dspk1_cif_ep>;
0268 };
0269 };
0270
0271 xbar_dspk2_port: port@1f {
0272 reg = <0x1f>;
0273
0274 xbar_dspk2_ep: endpoint {
0275 remote-endpoint = <&dspk2_cif_ep>;
0276 };
0277 };
0278
0279 xbar_sfc1_in_port: port@20 {
0280 reg = <0x20>;
0281
0282 xbar_sfc1_in_ep: endpoint {
0283 remote-endpoint = <&sfc1_cif_in_ep>;
0284 };
0285 };
0286
0287 port@21 {
0288 reg = <0x21>;
0289
0290 xbar_sfc1_out_ep: endpoint {
0291 remote-endpoint = <&sfc1_cif_out_ep>;
0292 };
0293 };
0294
0295 xbar_sfc2_in_port: port@22 {
0296 reg = <0x22>;
0297
0298 xbar_sfc2_in_ep: endpoint {
0299 remote-endpoint = <&sfc2_cif_in_ep>;
0300 };
0301 };
0302
0303 port@23 {
0304 reg = <0x23>;
0305
0306 xbar_sfc2_out_ep: endpoint {
0307 remote-endpoint = <&sfc2_cif_out_ep>;
0308 };
0309 };
0310
0311 xbar_sfc3_in_port: port@24 {
0312 reg = <0x24>;
0313
0314 xbar_sfc3_in_ep: endpoint {
0315 remote-endpoint = <&sfc3_cif_in_ep>;
0316 };
0317 };
0318
0319 port@25 {
0320 reg = <0x25>;
0321
0322 xbar_sfc3_out_ep: endpoint {
0323 remote-endpoint = <&sfc3_cif_out_ep>;
0324 };
0325 };
0326
0327 xbar_sfc4_in_port: port@26 {
0328 reg = <0x26>;
0329
0330 xbar_sfc4_in_ep: endpoint {
0331 remote-endpoint = <&sfc4_cif_in_ep>;
0332 };
0333 };
0334
0335 port@27 {
0336 reg = <0x27>;
0337
0338 xbar_sfc4_out_ep: endpoint {
0339 remote-endpoint = <&sfc4_cif_out_ep>;
0340 };
0341 };
0342
0343 xbar_mvc1_in_port: port@28 {
0344 reg = <0x28>;
0345
0346 xbar_mvc1_in_ep: endpoint {
0347 remote-endpoint = <&mvc1_cif_in_ep>;
0348 };
0349 };
0350
0351 port@29 {
0352 reg = <0x29>;
0353
0354 xbar_mvc1_out_ep: endpoint {
0355 remote-endpoint = <&mvc1_cif_out_ep>;
0356 };
0357 };
0358
0359 xbar_mvc2_in_port: port@2a {
0360 reg = <0x2a>;
0361
0362 xbar_mvc2_in_ep: endpoint {
0363 remote-endpoint = <&mvc2_cif_in_ep>;
0364 };
0365 };
0366
0367 port@2b {
0368 reg = <0x2b>;
0369
0370 xbar_mvc2_out_ep: endpoint {
0371 remote-endpoint = <&mvc2_cif_out_ep>;
0372 };
0373 };
0374
0375 xbar_amx1_in1_port: port@2c {
0376 reg = <0x2c>;
0377
0378 xbar_amx1_in1_ep: endpoint {
0379 remote-endpoint = <&amx1_in1_ep>;
0380 };
0381 };
0382
0383 xbar_amx1_in2_port: port@2d {
0384 reg = <0x2d>;
0385
0386 xbar_amx1_in2_ep: endpoint {
0387 remote-endpoint = <&amx1_in2_ep>;
0388 };
0389 };
0390
0391 xbar_amx1_in3_port: port@2e {
0392 reg = <0x2e>;
0393
0394 xbar_amx1_in3_ep: endpoint {
0395 remote-endpoint = <&amx1_in3_ep>;
0396 };
0397 };
0398
0399 xbar_amx1_in4_port: port@2f {
0400 reg = <0x2f>;
0401
0402 xbar_amx1_in4_ep: endpoint {
0403 remote-endpoint = <&amx1_in4_ep>;
0404 };
0405 };
0406
0407 port@30 {
0408 reg = <0x30>;
0409
0410 xbar_amx1_out_ep: endpoint {
0411 remote-endpoint = <&amx1_out_ep>;
0412 };
0413 };
0414
0415 xbar_amx2_in1_port: port@31 {
0416 reg = <0x31>;
0417
0418 xbar_amx2_in1_ep: endpoint {
0419 remote-endpoint = <&amx2_in1_ep>;
0420 };
0421 };
0422
0423 xbar_amx2_in2_port: port@32 {
0424 reg = <0x32>;
0425
0426 xbar_amx2_in2_ep: endpoint {
0427 remote-endpoint = <&amx2_in2_ep>;
0428 };
0429 };
0430
0431 xbar_amx2_in3_port: port@33 {
0432 reg = <0x33>;
0433
0434 xbar_amx2_in3_ep: endpoint {
0435 remote-endpoint = <&amx2_in3_ep>;
0436 };
0437 };
0438
0439 xbar_amx2_in4_port: port@34 {
0440 reg = <0x34>;
0441
0442 xbar_amx2_in4_ep: endpoint {
0443 remote-endpoint = <&amx2_in4_ep>;
0444 };
0445 };
0446
0447 port@35 {
0448 reg = <0x35>;
0449
0450 xbar_amx2_out_ep: endpoint {
0451 remote-endpoint = <&amx2_out_ep>;
0452 };
0453 };
0454
0455 xbar_amx3_in1_port: port@36 {
0456 reg = <0x36>;
0457
0458 xbar_amx3_in1_ep: endpoint {
0459 remote-endpoint = <&amx3_in1_ep>;
0460 };
0461 };
0462
0463 xbar_amx3_in2_port: port@37 {
0464 reg = <0x37>;
0465
0466 xbar_amx3_in2_ep: endpoint {
0467 remote-endpoint = <&amx3_in2_ep>;
0468 };
0469 };
0470
0471 xbar_amx3_in3_port: port@38 {
0472 reg = <0x38>;
0473
0474 xbar_amx3_in3_ep: endpoint {
0475 remote-endpoint = <&amx3_in3_ep>;
0476 };
0477 };
0478
0479 xbar_amx3_in4_port: port@39 {
0480 reg = <0x39>;
0481
0482 xbar_amx3_in4_ep: endpoint {
0483 remote-endpoint = <&amx3_in4_ep>;
0484 };
0485 };
0486
0487 port@3a {
0488 reg = <0x3a>;
0489
0490 xbar_amx3_out_ep: endpoint {
0491 remote-endpoint = <&amx3_out_ep>;
0492 };
0493 };
0494
0495 xbar_amx4_in1_port: port@3b {
0496 reg = <0x3b>;
0497
0498 xbar_amx4_in1_ep: endpoint {
0499 remote-endpoint = <&amx4_in1_ep>;
0500 };
0501 };
0502
0503 xbar_amx4_in2_port: port@3c {
0504 reg = <0x3c>;
0505
0506 xbar_amx4_in2_ep: endpoint {
0507 remote-endpoint = <&amx4_in2_ep>;
0508 };
0509 };
0510
0511 xbar_amx4_in3_port: port@3d {
0512 reg = <0x3d>;
0513
0514 xbar_amx4_in3_ep: endpoint {
0515 remote-endpoint = <&amx4_in3_ep>;
0516 };
0517 };
0518
0519 xbar_amx4_in4_port: port@3e {
0520 reg = <0x3e>;
0521
0522 xbar_amx4_in4_ep: endpoint {
0523 remote-endpoint = <&amx4_in4_ep>;
0524 };
0525 };
0526
0527 port@3f {
0528 reg = <0x3f>;
0529
0530 xbar_amx4_out_ep: endpoint {
0531 remote-endpoint = <&amx4_out_ep>;
0532 };
0533 };
0534
0535 xbar_adx1_in_port: port@40 {
0536 reg = <0x40>;
0537
0538 xbar_adx1_in_ep: endpoint {
0539 remote-endpoint = <&adx1_in_ep>;
0540 };
0541 };
0542
0543 port@41 {
0544 reg = <0x41>;
0545
0546 xbar_adx1_out1_ep: endpoint {
0547 remote-endpoint = <&adx1_out1_ep>;
0548 };
0549 };
0550
0551 port@42 {
0552 reg = <0x42>;
0553
0554 xbar_adx1_out2_ep: endpoint {
0555 remote-endpoint = <&adx1_out2_ep>;
0556 };
0557 };
0558
0559 port@43 {
0560 reg = <0x43>;
0561
0562 xbar_adx1_out3_ep: endpoint {
0563 remote-endpoint = <&adx1_out3_ep>;
0564 };
0565 };
0566
0567 port@44 {
0568 reg = <0x44>;
0569
0570 xbar_adx1_out4_ep: endpoint {
0571 remote-endpoint = <&adx1_out4_ep>;
0572 };
0573 };
0574
0575 xbar_adx2_in_port: port@45 {
0576 reg = <0x45>;
0577
0578 xbar_adx2_in_ep: endpoint {
0579 remote-endpoint = <&adx2_in_ep>;
0580 };
0581 };
0582
0583 port@46 {
0584 reg = <0x46>;
0585
0586 xbar_adx2_out1_ep: endpoint {
0587 remote-endpoint = <&adx2_out1_ep>;
0588 };
0589 };
0590
0591 port@47 {
0592 reg = <0x47>;
0593
0594 xbar_adx2_out2_ep: endpoint {
0595 remote-endpoint = <&adx2_out2_ep>;
0596 };
0597 };
0598
0599 port@48 {
0600 reg = <0x48>;
0601
0602 xbar_adx2_out3_ep: endpoint {
0603 remote-endpoint = <&adx2_out3_ep>;
0604 };
0605 };
0606
0607 port@49 {
0608 reg = <0x49>;
0609
0610 xbar_adx2_out4_ep: endpoint {
0611 remote-endpoint = <&adx2_out4_ep>;
0612 };
0613 };
0614
0615 xbar_adx3_in_port: port@4a {
0616 reg = <0x4a>;
0617
0618 xbar_adx3_in_ep: endpoint {
0619 remote-endpoint = <&adx3_in_ep>;
0620 };
0621 };
0622
0623 port@4b {
0624 reg = <0x4b>;
0625
0626 xbar_adx3_out1_ep: endpoint {
0627 remote-endpoint = <&adx3_out1_ep>;
0628 };
0629 };
0630
0631 port@4c {
0632 reg = <0x4c>;
0633
0634 xbar_adx3_out2_ep: endpoint {
0635 remote-endpoint = <&adx3_out2_ep>;
0636 };
0637 };
0638
0639 port@4d {
0640 reg = <0x4d>;
0641
0642 xbar_adx3_out3_ep: endpoint {
0643 remote-endpoint = <&adx3_out3_ep>;
0644 };
0645 };
0646
0647 port@4e {
0648 reg = <0x4e>;
0649
0650 xbar_adx3_out4_ep: endpoint {
0651 remote-endpoint = <&adx3_out4_ep>;
0652 };
0653 };
0654
0655 xbar_adx4_in_port: port@4f {
0656 reg = <0x4f>;
0657
0658 xbar_adx4_in_ep: endpoint {
0659 remote-endpoint = <&adx4_in_ep>;
0660 };
0661 };
0662
0663 port@50 {
0664 reg = <0x50>;
0665
0666 xbar_adx4_out1_ep: endpoint {
0667 remote-endpoint = <&adx4_out1_ep>;
0668 };
0669 };
0670
0671 port@51 {
0672 reg = <0x51>;
0673
0674 xbar_adx4_out2_ep: endpoint {
0675 remote-endpoint = <&adx4_out2_ep>;
0676 };
0677 };
0678
0679 port@52 {
0680 reg = <0x52>;
0681
0682 xbar_adx4_out3_ep: endpoint {
0683 remote-endpoint = <&adx4_out3_ep>;
0684 };
0685 };
0686
0687 port@53 {
0688 reg = <0x53>;
0689
0690 xbar_adx4_out4_ep: endpoint {
0691 remote-endpoint = <&adx4_out4_ep>;
0692 };
0693 };
0694
0695 xbar_mixer_in1_port: port@54 {
0696 reg = <0x54>;
0697
0698 xbar_mixer_in1_ep: endpoint {
0699 remote-endpoint = <&mixer_in1_ep>;
0700 };
0701 };
0702
0703 xbar_mixer_in2_port: port@55 {
0704 reg = <0x55>;
0705
0706 xbar_mixer_in2_ep: endpoint {
0707 remote-endpoint = <&mixer_in2_ep>;
0708 };
0709 };
0710
0711 xbar_mixer_in3_port: port@56 {
0712 reg = <0x56>;
0713
0714 xbar_mixer_in3_ep: endpoint {
0715 remote-endpoint = <&mixer_in3_ep>;
0716 };
0717 };
0718
0719 xbar_mixer_in4_port: port@57 {
0720 reg = <0x57>;
0721
0722 xbar_mixer_in4_ep: endpoint {
0723 remote-endpoint = <&mixer_in4_ep>;
0724 };
0725 };
0726
0727 xbar_mixer_in5_port: port@58 {
0728 reg = <0x58>;
0729
0730 xbar_mixer_in5_ep: endpoint {
0731 remote-endpoint = <&mixer_in5_ep>;
0732 };
0733 };
0734
0735 xbar_mixer_in6_port: port@59 {
0736 reg = <0x59>;
0737
0738 xbar_mixer_in6_ep: endpoint {
0739 remote-endpoint = <&mixer_in6_ep>;
0740 };
0741 };
0742
0743 xbar_mixer_in7_port: port@5a {
0744 reg = <0x5a>;
0745
0746 xbar_mixer_in7_ep: endpoint {
0747 remote-endpoint = <&mixer_in7_ep>;
0748 };
0749 };
0750
0751 xbar_mixer_in8_port: port@5b {
0752 reg = <0x5b>;
0753
0754 xbar_mixer_in8_ep: endpoint {
0755 remote-endpoint = <&mixer_in8_ep>;
0756 };
0757 };
0758
0759 xbar_mixer_in9_port: port@5c {
0760 reg = <0x5c>;
0761
0762 xbar_mixer_in9_ep: endpoint {
0763 remote-endpoint = <&mixer_in9_ep>;
0764 };
0765 };
0766
0767 xbar_mixer_in10_port: port@5d {
0768 reg = <0x5d>;
0769
0770 xbar_mixer_in10_ep: endpoint {
0771 remote-endpoint = <&mixer_in10_ep>;
0772 };
0773 };
0774
0775 port@5e {
0776 reg = <0x5e>;
0777
0778 xbar_mixer_out1_ep: endpoint {
0779 remote-endpoint = <&mixer_out1_ep>;
0780 };
0781 };
0782
0783 port@5f {
0784 reg = <0x5f>;
0785
0786 xbar_mixer_out2_ep: endpoint {
0787 remote-endpoint = <&mixer_out2_ep>;
0788 };
0789 };
0790
0791 port@60 {
0792 reg = <0x60>;
0793
0794 xbar_mixer_out3_ep: endpoint {
0795 remote-endpoint = <&mixer_out3_ep>;
0796 };
0797 };
0798
0799 port@61 {
0800 reg = <0x61>;
0801
0802 xbar_mixer_out4_ep: endpoint {
0803 remote-endpoint = <&mixer_out4_ep>;
0804 };
0805 };
0806
0807 port@62 {
0808 reg = <0x62>;
0809
0810 xbar_mixer_out5_ep: endpoint {
0811 remote-endpoint = <&mixer_out5_ep>;
0812 };
0813 };
0814
0815 xbar_asrc_in1_port: port@63 {
0816 reg = <0x63>;
0817
0818 xbar_asrc_in1_ep: endpoint {
0819 remote-endpoint = <&asrc_in1_ep>;
0820 };
0821 };
0822
0823 port@64 {
0824 reg = <0x64>;
0825
0826 xbar_asrc_out1_ep: endpoint {
0827 remote-endpoint = <&asrc_out1_ep>;
0828 };
0829 };
0830
0831 xbar_asrc_in2_port: port@65 {
0832 reg = <0x65>;
0833
0834 xbar_asrc_in2_ep: endpoint {
0835 remote-endpoint = <&asrc_in2_ep>;
0836 };
0837 };
0838
0839 port@66 {
0840 reg = <0x66>;
0841
0842 xbar_asrc_out2_ep: endpoint {
0843 remote-endpoint = <&asrc_out2_ep>;
0844 };
0845 };
0846
0847 xbar_asrc_in3_port: port@67 {
0848 reg = <0x67>;
0849
0850 xbar_asrc_in3_ep: endpoint {
0851 remote-endpoint = <&asrc_in3_ep>;
0852 };
0853 };
0854
0855 port@68 {
0856 reg = <0x68>;
0857
0858 xbar_asrc_out3_ep: endpoint {
0859 remote-endpoint = <&asrc_out3_ep>;
0860 };
0861 };
0862
0863 xbar_asrc_in4_port: port@69 {
0864 reg = <0x69>;
0865
0866 xbar_asrc_in4_ep: endpoint {
0867 remote-endpoint = <&asrc_in4_ep>;
0868 };
0869 };
0870
0871 port@6a {
0872 reg = <0x6a>;
0873
0874 xbar_asrc_out4_ep: endpoint {
0875 remote-endpoint = <&asrc_out4_ep>;
0876 };
0877 };
0878
0879 xbar_asrc_in5_port: port@6b {
0880 reg = <0x6b>;
0881
0882 xbar_asrc_in5_ep: endpoint {
0883 remote-endpoint = <&asrc_in5_ep>;
0884 };
0885 };
0886
0887 port@6c {
0888 reg = <0x6c>;
0889
0890 xbar_asrc_out5_ep: endpoint {
0891 remote-endpoint = <&asrc_out5_ep>;
0892 };
0893 };
0894
0895 xbar_asrc_in6_port: port@6d {
0896 reg = <0x6d>;
0897
0898 xbar_asrc_in6_ep: endpoint {
0899 remote-endpoint = <&asrc_in6_ep>;
0900 };
0901 };
0902
0903 port@6e {
0904 reg = <0x6e>;
0905
0906 xbar_asrc_out6_ep: endpoint {
0907 remote-endpoint = <&asrc_out6_ep>;
0908 };
0909 };
0910
0911 xbar_asrc_in7_port: port@6f {
0912 reg = <0x6f>;
0913
0914 xbar_asrc_in7_ep: endpoint {
0915 remote-endpoint = <&asrc_in7_ep>;
0916 };
0917 };
0918
0919 xbar_ope1_in_port: port@70 {
0920 reg = <0x70>;
0921
0922 xbar_ope1_in_ep: endpoint {
0923 remote-endpoint = <&ope1_cif_in_ep>;
0924 };
0925 };
0926
0927 port@71 {
0928 reg = <0x71>;
0929
0930 xbar_ope1_out_ep: endpoint {
0931 remote-endpoint = <&ope1_cif_out_ep>;
0932 };
0933 };
0934 };
0935
0936 admaif@290f000 {
0937 status = "okay";
0938
0939 ports {
0940 #address-cells = <1>;
0941 #size-cells = <0>;
0942
0943 admaif0_port: port@0 {
0944 reg = <0x0>;
0945
0946 admaif0_ep: endpoint {
0947 remote-endpoint = <&xbar_admaif0_ep>;
0948 };
0949 };
0950
0951 admaif1_port: port@1 {
0952 reg = <0x1>;
0953
0954 admaif1_ep: endpoint {
0955 remote-endpoint = <&xbar_admaif1_ep>;
0956 };
0957 };
0958
0959 admaif2_port: port@2 {
0960 reg = <0x2>;
0961
0962 admaif2_ep: endpoint {
0963 remote-endpoint = <&xbar_admaif2_ep>;
0964 };
0965 };
0966
0967 admaif3_port: port@3 {
0968 reg = <0x3>;
0969
0970 admaif3_ep: endpoint {
0971 remote-endpoint = <&xbar_admaif3_ep>;
0972 };
0973 };
0974
0975 admaif4_port: port@4 {
0976 reg = <0x4>;
0977
0978 admaif4_ep: endpoint {
0979 remote-endpoint = <&xbar_admaif4_ep>;
0980 };
0981 };
0982
0983 admaif5_port: port@5 {
0984 reg = <0x5>;
0985
0986 admaif5_ep: endpoint {
0987 remote-endpoint = <&xbar_admaif5_ep>;
0988 };
0989 };
0990
0991 admaif6_port: port@6 {
0992 reg = <0x6>;
0993
0994 admaif6_ep: endpoint {
0995 remote-endpoint = <&xbar_admaif6_ep>;
0996 };
0997 };
0998
0999 admaif7_port: port@7 {
1000 reg = <0x7>;
1001
1002 admaif7_ep: endpoint {
1003 remote-endpoint = <&xbar_admaif7_ep>;
1004 };
1005 };
1006
1007 admaif8_port: port@8 {
1008 reg = <0x8>;
1009
1010 admaif8_ep: endpoint {
1011 remote-endpoint = <&xbar_admaif8_ep>;
1012 };
1013 };
1014
1015 admaif9_port: port@9 {
1016 reg = <0x9>;
1017
1018 admaif9_ep: endpoint {
1019 remote-endpoint = <&xbar_admaif9_ep>;
1020 };
1021 };
1022
1023 admaif10_port: port@a {
1024 reg = <0xa>;
1025
1026 admaif10_ep: endpoint {
1027 remote-endpoint = <&xbar_admaif10_ep>;
1028 };
1029 };
1030
1031 admaif11_port: port@b {
1032 reg = <0xb>;
1033
1034 admaif11_ep: endpoint {
1035 remote-endpoint = <&xbar_admaif11_ep>;
1036 };
1037 };
1038
1039 admaif12_port: port@c {
1040 reg = <0xc>;
1041
1042 admaif12_ep: endpoint {
1043 remote-endpoint = <&xbar_admaif12_ep>;
1044 };
1045 };
1046
1047 admaif13_port: port@d {
1048 reg = <0xd>;
1049
1050 admaif13_ep: endpoint {
1051 remote-endpoint = <&xbar_admaif13_ep>;
1052 };
1053 };
1054
1055 admaif14_port: port@e {
1056 reg = <0xe>;
1057
1058 admaif14_ep: endpoint {
1059 remote-endpoint = <&xbar_admaif14_ep>;
1060 };
1061 };
1062
1063 admaif15_port: port@f {
1064 reg = <0xf>;
1065
1066 admaif15_ep: endpoint {
1067 remote-endpoint = <&xbar_admaif15_ep>;
1068 };
1069 };
1070
1071 admaif16_port: port@10 {
1072 reg = <0x10>;
1073
1074 admaif16_ep: endpoint {
1075 remote-endpoint = <&xbar_admaif16_ep>;
1076 };
1077 };
1078
1079 admaif17_port: port@11 {
1080 reg = <0x11>;
1081
1082 admaif17_ep: endpoint {
1083 remote-endpoint = <&xbar_admaif17_ep>;
1084 };
1085 };
1086
1087 admaif18_port: port@12 {
1088 reg = <0x12>;
1089
1090 admaif18_ep: endpoint {
1091 remote-endpoint = <&xbar_admaif18_ep>;
1092 };
1093 };
1094
1095 admaif19_port: port@13 {
1096 reg = <0x13>;
1097
1098 admaif19_ep: endpoint {
1099 remote-endpoint = <&xbar_admaif19_ep>;
1100 };
1101 };
1102 };
1103 };
1104
1105 i2s@2901000 {
1106 status = "okay";
1107
1108 ports {
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111
1112 port@0 {
1113 reg = <0>;
1114
1115 i2s1_cif_ep: endpoint {
1116 remote-endpoint = <&xbar_i2s1_ep>;
1117 };
1118 };
1119
1120 i2s1_port: port@1 {
1121 reg = <1>;
1122
1123 i2s1_dap_ep: endpoint {
1124 dai-format = "i2s";
1125 /* Placeholder for external Codec */
1126 };
1127 };
1128 };
1129 };
1130
1131 i2s@2901100 {
1132 status = "okay";
1133
1134 ports {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137
1138 port@0 {
1139 reg = <0>;
1140
1141 i2s2_cif_ep: endpoint {
1142 remote-endpoint = <&xbar_i2s2_ep>;
1143 };
1144 };
1145
1146 i2s2_port: port@1 {
1147 reg = <1>;
1148
1149 i2s2_dap_ep: endpoint {
1150 dai-format = "i2s";
1151 /* Placeholder for external Codec */
1152 };
1153 };
1154 };
1155 };
1156
1157 i2s@2901200 {
1158 status = "okay";
1159
1160 ports {
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163
1164 port@0 {
1165 reg = <0>;
1166
1167 i2s3_cif_ep: endpoint {
1168 remote-endpoint = <&xbar_i2s3_ep>;
1169 };
1170 };
1171
1172 i2s3_port: port@1 {
1173 reg = <1>;
1174
1175 i2s3_dap_ep: endpoint {
1176 dai-format = "i2s";
1177 /* Placeholder for external Codec */
1178 };
1179 };
1180 };
1181 };
1182
1183 i2s@2901300 {
1184 status = "okay";
1185
1186 ports {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189
1190 port@0 {
1191 reg = <0>;
1192
1193 i2s4_cif_ep: endpoint {
1194 remote-endpoint = <&xbar_i2s4_ep>;
1195 };
1196 };
1197
1198 i2s4_port: port@1 {
1199 reg = <1>;
1200
1201 i2s4_dap_ep: endpoint {
1202 dai-format = "i2s";
1203 /* Placeholder for external Codec */
1204 };
1205 };
1206 };
1207 };
1208
1209 i2s@2901400 {
1210 status = "okay";
1211
1212 ports {
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1215
1216 port@0 {
1217 reg = <0>;
1218
1219 i2s5_cif_ep: endpoint {
1220 remote-endpoint = <&xbar_i2s5_ep>;
1221 };
1222 };
1223
1224 i2s5_port: port@1 {
1225 reg = <1>;
1226
1227 i2s5_dap_ep: endpoint {
1228 dai-format = "i2s";
1229 /* Placeholder for external Codec */
1230 };
1231 };
1232 };
1233 };
1234
1235 i2s@2901500 {
1236 status = "okay";
1237
1238 ports {
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241
1242 port@0 {
1243 reg = <0>;
1244
1245 i2s6_cif_ep: endpoint {
1246 remote-endpoint = <&xbar_i2s6_ep>;
1247 };
1248 };
1249
1250 i2s6_port: port@1 {
1251 reg = <1>;
1252
1253 i2s6_dap_ep: endpoint {
1254 dai-format = "i2s";
1255 /* Placeholder for external Codec */
1256 };
1257 };
1258 };
1259 };
1260
1261 dmic@2904000 {
1262 status = "okay";
1263
1264 ports {
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267
1268 port@0 {
1269 reg = <0>;
1270
1271 dmic1_cif_ep: endpoint {
1272 remote-endpoint = <&xbar_dmic1_ep>;
1273 };
1274 };
1275
1276 dmic1_port: port@1 {
1277 reg = <1>;
1278
1279 dmic1_dap_ep: endpoint {
1280 /* Place holder for external Codec */
1281 };
1282 };
1283 };
1284 };
1285
1286 dmic@2904100 {
1287 status = "okay";
1288
1289 ports {
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1292
1293 port@0 {
1294 reg = <0>;
1295
1296 dmic2_cif_ep: endpoint {
1297 remote-endpoint = <&xbar_dmic2_ep>;
1298 };
1299 };
1300
1301 dmic2_port: port@1 {
1302 reg = <1>;
1303
1304 dmic2_dap_ep: endpoint {
1305 /* Place holder for external Codec */
1306 };
1307 };
1308 };
1309 };
1310
1311 dmic@2904200 {
1312 status = "okay";
1313
1314 ports {
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317
1318 port@0 {
1319 reg = <0>;
1320
1321 dmic3_cif_ep: endpoint {
1322 remote-endpoint = <&xbar_dmic3_ep>;
1323 };
1324 };
1325
1326 dmic3_port: port@1 {
1327 reg = <1>;
1328
1329 dmic3_dap_ep: endpoint {
1330 /* Place holder for external Codec */
1331 };
1332 };
1333 };
1334 };
1335
1336 dspk@2905000 {
1337 status = "okay";
1338
1339 ports {
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342
1343 port@0 {
1344 reg = <0>;
1345
1346 dspk1_cif_ep: endpoint {
1347 remote-endpoint = <&xbar_dspk1_ep>;
1348 };
1349 };
1350
1351 dspk1_port: port@1 {
1352 reg = <1>;
1353
1354 dspk1_dap_ep: endpoint {
1355 /* Place holder for external Codec */
1356 };
1357 };
1358 };
1359 };
1360
1361 dspk@2905100 {
1362 status = "okay";
1363
1364 ports {
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1367
1368 port@0 {
1369 reg = <0>;
1370
1371 dspk2_cif_ep: endpoint {
1372 remote-endpoint = <&xbar_dspk2_ep>;
1373 };
1374 };
1375
1376 dspk2_port: port@1 {
1377 reg = <1>;
1378
1379 dspk2_dap_ep: endpoint {
1380 /* Place holder for external Codec */
1381 };
1382 };
1383 };
1384 };
1385
1386 sfc@2902000 {
1387 status = "okay";
1388
1389 ports {
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392
1393 port@0 {
1394 reg = <0>;
1395
1396 sfc1_cif_in_ep: endpoint {
1397 remote-endpoint = <&xbar_sfc1_in_ep>;
1398 convert-rate = <44100>;
1399 };
1400 };
1401
1402 sfc1_out_port: port@1 {
1403 reg = <1>;
1404
1405 sfc1_cif_out_ep: endpoint {
1406 remote-endpoint = <&xbar_sfc1_out_ep>;
1407 convert-rate = <48000>;
1408 };
1409 };
1410 };
1411 };
1412
1413 sfc@2902200 {
1414 status = "okay";
1415
1416 ports {
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1419
1420 port@0 {
1421 reg = <0>;
1422
1423 sfc2_cif_in_ep: endpoint {
1424 remote-endpoint = <&xbar_sfc2_in_ep>;
1425 };
1426 };
1427
1428 sfc2_out_port: port@1 {
1429 reg = <1>;
1430
1431 sfc2_cif_out_ep: endpoint {
1432 remote-endpoint = <&xbar_sfc2_out_ep>;
1433 };
1434 };
1435 };
1436 };
1437
1438 sfc@2902400 {
1439 status = "okay";
1440
1441 ports {
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1444
1445 port@0 {
1446 reg = <0>;
1447
1448 sfc3_cif_in_ep: endpoint {
1449 remote-endpoint = <&xbar_sfc3_in_ep>;
1450 };
1451 };
1452
1453 sfc3_out_port: port@1 {
1454 reg = <1>;
1455
1456 sfc3_cif_out_ep: endpoint {
1457 remote-endpoint = <&xbar_sfc3_out_ep>;
1458 };
1459 };
1460 };
1461 };
1462
1463 sfc@2902600 {
1464 status = "okay";
1465
1466 ports {
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1469
1470 port@0 {
1471 reg = <0>;
1472
1473 sfc4_cif_in_ep: endpoint {
1474 remote-endpoint = <&xbar_sfc4_in_ep>;
1475 };
1476 };
1477
1478 sfc4_out_port: port@1 {
1479 reg = <1>;
1480
1481 sfc4_cif_out_ep: endpoint {
1482 remote-endpoint = <&xbar_sfc4_out_ep>;
1483 };
1484 };
1485 };
1486 };
1487
1488 mvc@290a000 {
1489 status = "okay";
1490
1491 ports {
1492 #address-cells = <1>;
1493 #size-cells = <0>;
1494
1495 port@0 {
1496 reg = <0>;
1497
1498 mvc1_cif_in_ep: endpoint {
1499 remote-endpoint = <&xbar_mvc1_in_ep>;
1500 };
1501 };
1502
1503 mvc1_out_port: port@1 {
1504 reg = <1>;
1505
1506 mvc1_cif_out_ep: endpoint {
1507 remote-endpoint = <&xbar_mvc1_out_ep>;
1508 };
1509 };
1510 };
1511 };
1512
1513 mvc@290a200 {
1514 status = "okay";
1515
1516 ports {
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519
1520 port@0 {
1521 reg = <0>;
1522
1523 mvc2_cif_in_ep: endpoint {
1524 remote-endpoint = <&xbar_mvc2_in_ep>;
1525 };
1526 };
1527
1528 mvc2_out_port: port@1 {
1529 reg = <1>;
1530
1531 mvc2_cif_out_ep: endpoint {
1532 remote-endpoint = <&xbar_mvc2_out_ep>;
1533 };
1534 };
1535 };
1536 };
1537
1538 amx@2903000 {
1539 status = "okay";
1540
1541 ports {
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544
1545 port@0 {
1546 reg = <0>;
1547
1548 amx1_in1_ep: endpoint {
1549 remote-endpoint = <&xbar_amx1_in1_ep>;
1550 };
1551 };
1552
1553 port@1 {
1554 reg = <1>;
1555
1556 amx1_in2_ep: endpoint {
1557 remote-endpoint = <&xbar_amx1_in2_ep>;
1558 };
1559 };
1560
1561 port@2 {
1562 reg = <2>;
1563
1564 amx1_in3_ep: endpoint {
1565 remote-endpoint = <&xbar_amx1_in3_ep>;
1566 };
1567 };
1568
1569 port@3 {
1570 reg = <3>;
1571
1572 amx1_in4_ep: endpoint {
1573 remote-endpoint = <&xbar_amx1_in4_ep>;
1574 };
1575 };
1576
1577 amx1_out_port: port@4 {
1578 reg = <4>;
1579
1580 amx1_out_ep: endpoint {
1581 remote-endpoint = <&xbar_amx1_out_ep>;
1582 };
1583 };
1584 };
1585 };
1586
1587 amx@2903100 {
1588 status = "okay";
1589
1590 ports {
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593
1594 port@0 {
1595 reg = <0>;
1596
1597 amx2_in1_ep: endpoint {
1598 remote-endpoint = <&xbar_amx2_in1_ep>;
1599 };
1600 };
1601
1602 port@1 {
1603 reg = <1>;
1604
1605 amx2_in2_ep: endpoint {
1606 remote-endpoint = <&xbar_amx2_in2_ep>;
1607 };
1608 };
1609
1610 amx2_in3_port: port@2 {
1611 reg = <2>;
1612
1613 amx2_in3_ep: endpoint {
1614 remote-endpoint = <&xbar_amx2_in3_ep>;
1615 };
1616 };
1617
1618 amx2_in4_port: port@3 {
1619 reg = <3>;
1620
1621 amx2_in4_ep: endpoint {
1622 remote-endpoint = <&xbar_amx2_in4_ep>;
1623 };
1624 };
1625
1626 amx2_out_port: port@4 {
1627 reg = <4>;
1628
1629 amx2_out_ep: endpoint {
1630 remote-endpoint = <&xbar_amx2_out_ep>;
1631 };
1632 };
1633 };
1634 };
1635
1636 amx@2903200 {
1637 status = "okay";
1638
1639 ports {
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642
1643 port@0 {
1644 reg = <0>;
1645
1646 amx3_in1_ep: endpoint {
1647 remote-endpoint = <&xbar_amx3_in1_ep>;
1648 };
1649 };
1650
1651 port@1 {
1652 reg = <1>;
1653
1654 amx3_in2_ep: endpoint {
1655 remote-endpoint = <&xbar_amx3_in2_ep>;
1656 };
1657 };
1658
1659 port@2 {
1660 reg = <2>;
1661
1662 amx3_in3_ep: endpoint {
1663 remote-endpoint = <&xbar_amx3_in3_ep>;
1664 };
1665 };
1666
1667 port@3 {
1668 reg = <3>;
1669
1670 amx3_in4_ep: endpoint {
1671 remote-endpoint = <&xbar_amx3_in4_ep>;
1672 };
1673 };
1674
1675 amx3_out_port: port@4 {
1676 reg = <4>;
1677
1678 amx3_out_ep: endpoint {
1679 remote-endpoint = <&xbar_amx3_out_ep>;
1680 };
1681 };
1682 };
1683 };
1684
1685 amx@2903300 {
1686 status = "okay";
1687
1688 ports {
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1691
1692 port@0 {
1693 reg = <0>;
1694
1695 amx4_in1_ep: endpoint {
1696 remote-endpoint = <&xbar_amx4_in1_ep>;
1697 };
1698 };
1699
1700 port@1 {
1701 reg = <1>;
1702
1703 amx4_in2_ep: endpoint {
1704 remote-endpoint = <&xbar_amx4_in2_ep>;
1705 };
1706 };
1707
1708 port@2 {
1709 reg = <2>;
1710
1711 amx4_in3_ep: endpoint {
1712 remote-endpoint = <&xbar_amx4_in3_ep>;
1713 };
1714 };
1715
1716 port@3 {
1717 reg = <3>;
1718
1719 amx4_in4_ep: endpoint {
1720 remote-endpoint = <&xbar_amx4_in4_ep>;
1721 };
1722 };
1723
1724 amx4_out_port: port@4 {
1725 reg = <4>;
1726
1727 amx4_out_ep: endpoint {
1728 remote-endpoint = <&xbar_amx4_out_ep>;
1729 };
1730 };
1731 };
1732 };
1733
1734 adx@2903800 {
1735 status = "okay";
1736
1737 ports {
1738 #address-cells = <1>;
1739 #size-cells = <0>;
1740
1741 port@0 {
1742 reg = <0>;
1743
1744 adx1_in_ep: endpoint {
1745 remote-endpoint = <&xbar_adx1_in_ep>;
1746 };
1747 };
1748
1749 adx1_out1_port: port@1 {
1750 reg = <1>;
1751
1752 adx1_out1_ep: endpoint {
1753 remote-endpoint = <&xbar_adx1_out1_ep>;
1754 };
1755 };
1756
1757 adx1_out2_port: port@2 {
1758 reg = <2>;
1759
1760 adx1_out2_ep: endpoint {
1761 remote-endpoint = <&xbar_adx1_out2_ep>;
1762 };
1763 };
1764
1765 adx1_out3_port: port@3 {
1766 reg = <3>;
1767
1768 adx1_out3_ep: endpoint {
1769 remote-endpoint = <&xbar_adx1_out3_ep>;
1770 };
1771 };
1772
1773 adx1_out4_port: port@4 {
1774 reg = <4>;
1775
1776 adx1_out4_ep: endpoint {
1777 remote-endpoint = <&xbar_adx1_out4_ep>;
1778 };
1779 };
1780 };
1781 };
1782
1783 adx@2903900 {
1784 status = "okay";
1785
1786 ports {
1787 #address-cells = <1>;
1788 #size-cells = <0>;
1789
1790 port@0 {
1791 reg = <0>;
1792
1793 adx2_in_ep: endpoint {
1794 remote-endpoint = <&xbar_adx2_in_ep>;
1795 };
1796 };
1797
1798 adx2_out1_port: port@1 {
1799 reg = <1>;
1800
1801 adx2_out1_ep: endpoint {
1802 remote-endpoint = <&xbar_adx2_out1_ep>;
1803 };
1804 };
1805
1806 adx2_out2_port: port@2 {
1807 reg = <2>;
1808
1809 adx2_out2_ep: endpoint {
1810 remote-endpoint = <&xbar_adx2_out2_ep>;
1811 };
1812 };
1813
1814 adx2_out3_port: port@3 {
1815 reg = <3>;
1816
1817 adx2_out3_ep: endpoint {
1818 remote-endpoint = <&xbar_adx2_out3_ep>;
1819 };
1820 };
1821
1822 adx2_out4_port: port@4 {
1823 reg = <4>;
1824
1825 adx2_out4_ep: endpoint {
1826 remote-endpoint = <&xbar_adx2_out4_ep>;
1827 };
1828 };
1829 };
1830 };
1831
1832 adx@2903a00 {
1833 status = "okay";
1834
1835 ports {
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1838
1839 port@0 {
1840 reg = <0>;
1841
1842 adx3_in_ep: endpoint {
1843 remote-endpoint = <&xbar_adx3_in_ep>;
1844 };
1845 };
1846
1847 adx3_out1_port: port@1 {
1848 reg = <1>;
1849
1850 adx3_out1_ep: endpoint {
1851 remote-endpoint = <&xbar_adx3_out1_ep>;
1852 };
1853 };
1854
1855 adx3_out2_port: port@2 {
1856 reg = <2>;
1857
1858 adx3_out2_ep: endpoint {
1859 remote-endpoint = <&xbar_adx3_out2_ep>;
1860 };
1861 };
1862
1863 adx3_out3_port: port@3 {
1864 reg = <3>;
1865
1866 adx3_out3_ep: endpoint {
1867 remote-endpoint = <&xbar_adx3_out3_ep>;
1868 };
1869 };
1870
1871 adx3_out4_port: port@4 {
1872 reg = <4>;
1873
1874 adx3_out4_ep: endpoint {
1875 remote-endpoint = <&xbar_adx3_out4_ep>;
1876 };
1877 };
1878 };
1879 };
1880
1881 adx@2903b00 {
1882 status = "okay";
1883
1884 ports {
1885 #address-cells = <1>;
1886 #size-cells = <0>;
1887
1888 port@0 {
1889 reg = <0>;
1890
1891 adx4_in_ep: endpoint {
1892 remote-endpoint = <&xbar_adx4_in_ep>;
1893 };
1894 };
1895
1896 adx4_out1_port: port@1 {
1897 reg = <1>;
1898
1899 adx4_out1_ep: endpoint {
1900 remote-endpoint = <&xbar_adx4_out1_ep>;
1901 };
1902 };
1903
1904 adx4_out2_port: port@2 {
1905 reg = <2>;
1906
1907 adx4_out2_ep: endpoint {
1908 remote-endpoint = <&xbar_adx4_out2_ep>;
1909 };
1910 };
1911
1912 adx4_out3_port: port@3 {
1913 reg = <3>;
1914
1915 adx4_out3_ep: endpoint {
1916 remote-endpoint = <&xbar_adx4_out3_ep>;
1917 };
1918 };
1919
1920 adx4_out4_port: port@4 {
1921 reg = <4>;
1922
1923 adx4_out4_ep: endpoint {
1924 remote-endpoint = <&xbar_adx4_out4_ep>;
1925 };
1926 };
1927 };
1928 };
1929
1930 processing-engine@2908000 {
1931 status = "okay";
1932
1933 ports {
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1936
1937 port@0 {
1938 reg = <0x0>;
1939
1940 ope1_cif_in_ep: endpoint {
1941 remote-endpoint = <&xbar_ope1_in_ep>;
1942 };
1943 };
1944
1945 ope1_out_port: port@1 {
1946 reg = <0x1>;
1947
1948 ope1_cif_out_ep: endpoint {
1949 remote-endpoint = <&xbar_ope1_out_ep>;
1950 };
1951 };
1952 };
1953 };
1954
1955 amixer@290bb00 {
1956 status = "okay";
1957
1958 ports {
1959 #address-cells = <1>;
1960 #size-cells = <0>;
1961
1962 port@0 {
1963 reg = <0x0>;
1964
1965 mixer_in1_ep: endpoint {
1966 remote-endpoint = <&xbar_mixer_in1_ep>;
1967 };
1968 };
1969
1970 port@1 {
1971 reg = <0x1>;
1972
1973 mixer_in2_ep: endpoint {
1974 remote-endpoint = <&xbar_mixer_in2_ep>;
1975 };
1976 };
1977
1978 port@2 {
1979 reg = <0x2>;
1980
1981 mixer_in3_ep: endpoint {
1982 remote-endpoint = <&xbar_mixer_in3_ep>;
1983 };
1984 };
1985
1986 port@3 {
1987 reg = <0x3>;
1988
1989 mixer_in4_ep: endpoint {
1990 remote-endpoint = <&xbar_mixer_in4_ep>;
1991 };
1992 };
1993
1994 port@4 {
1995 reg = <0x4>;
1996
1997 mixer_in5_ep: endpoint {
1998 remote-endpoint = <&xbar_mixer_in5_ep>;
1999 };
2000 };
2001
2002 port@5 {
2003 reg = <0x5>;
2004
2005 mixer_in6_ep: endpoint {
2006 remote-endpoint = <&xbar_mixer_in6_ep>;
2007 };
2008 };
2009
2010 port@6 {
2011 reg = <0x6>;
2012
2013 mixer_in7_ep: endpoint {
2014 remote-endpoint = <&xbar_mixer_in7_ep>;
2015 };
2016 };
2017
2018 port@7 {
2019 reg = <0x7>;
2020
2021 mixer_in8_ep: endpoint {
2022 remote-endpoint = <&xbar_mixer_in8_ep>;
2023 };
2024 };
2025
2026 port@8 {
2027 reg = <0x8>;
2028
2029 mixer_in9_ep: endpoint {
2030 remote-endpoint = <&xbar_mixer_in9_ep>;
2031 };
2032 };
2033
2034 port@9 {
2035 reg = <0x9>;
2036
2037 mixer_in10_ep: endpoint {
2038 remote-endpoint = <&xbar_mixer_in10_ep>;
2039 };
2040 };
2041
2042 mixer_out1_port: port@a {
2043 reg = <0xa>;
2044
2045 mixer_out1_ep: endpoint {
2046 remote-endpoint = <&xbar_mixer_out1_ep>;
2047 };
2048 };
2049
2050 mixer_out2_port: port@b {
2051 reg = <0xb>;
2052
2053 mixer_out2_ep: endpoint {
2054 remote-endpoint = <&xbar_mixer_out2_ep>;
2055 };
2056 };
2057
2058 mixer_out3_port: port@c {
2059 reg = <0xc>;
2060
2061 mixer_out3_ep: endpoint {
2062 remote-endpoint = <&xbar_mixer_out3_ep>;
2063 };
2064 };
2065
2066 mixer_out4_port: port@d {
2067 reg = <0xd>;
2068
2069 mixer_out4_ep: endpoint {
2070 remote-endpoint = <&xbar_mixer_out4_ep>;
2071 };
2072 };
2073
2074 mixer_out5_port: port@e {
2075 reg = <0xe>;
2076
2077 mixer_out5_ep: endpoint {
2078 remote-endpoint = <&xbar_mixer_out5_ep>;
2079 };
2080 };
2081 };
2082 };
2083
2084 asrc@2910000 {
2085 status = "okay";
2086
2087 ports {
2088 #address-cells = <1>;
2089 #size-cells = <0>;
2090
2091 port@0 {
2092 reg = <0x0>;
2093
2094 asrc_in1_ep: endpoint {
2095 remote-endpoint = <&xbar_asrc_in1_ep>;
2096 };
2097 };
2098
2099 port@1 {
2100 reg = <0x1>;
2101
2102 asrc_in2_ep: endpoint {
2103 remote-endpoint = <&xbar_asrc_in2_ep>;
2104 };
2105 };
2106
2107 port@2 {
2108 reg = <0x2>;
2109
2110 asrc_in3_ep: endpoint {
2111 remote-endpoint = <&xbar_asrc_in3_ep>;
2112 };
2113 };
2114
2115 port@3 {
2116 reg = <0x3>;
2117
2118 asrc_in4_ep: endpoint {
2119 remote-endpoint = <&xbar_asrc_in4_ep>;
2120 };
2121 };
2122
2123 port@4 {
2124 reg = <0x4>;
2125
2126 asrc_in5_ep: endpoint {
2127 remote-endpoint = <&xbar_asrc_in5_ep>;
2128 };
2129 };
2130
2131 port@5 {
2132 reg = <0x5>;
2133
2134 asrc_in6_ep: endpoint {
2135 remote-endpoint = <&xbar_asrc_in6_ep>;
2136 };
2137 };
2138
2139 port@6 {
2140 reg = <0x6>;
2141
2142 asrc_in7_ep: endpoint {
2143 remote-endpoint = <&xbar_asrc_in7_ep>;
2144 };
2145 };
2146
2147 asrc_out1_port: port@7 {
2148 reg = <0x7>;
2149
2150 asrc_out1_ep: endpoint {
2151 remote-endpoint = <&xbar_asrc_out1_ep>;
2152 };
2153 };
2154
2155 asrc_out2_port: port@8 {
2156 reg = <0x8>;
2157
2158 asrc_out2_ep: endpoint {
2159 remote-endpoint = <&xbar_asrc_out2_ep>;
2160 };
2161 };
2162
2163 asrc_out3_port: port@9 {
2164 reg = <0x9>;
2165
2166 asrc_out3_ep: endpoint {
2167 remote-endpoint = <&xbar_asrc_out3_ep>;
2168 };
2169 };
2170
2171 asrc_out4_port: port@a {
2172 reg = <0xa>;
2173
2174 asrc_out4_ep: endpoint {
2175 remote-endpoint = <&xbar_asrc_out4_ep>;
2176 };
2177 };
2178
2179 asrc_out5_port: port@b {
2180 reg = <0xb>;
2181
2182 asrc_out5_ep: endpoint {
2183 remote-endpoint = <&xbar_asrc_out5_ep>;
2184 };
2185 };
2186
2187 asrc_out6_port: port@c {
2188 reg = <0xc>;
2189
2190 asrc_out6_ep: endpoint {
2191 remote-endpoint = <&xbar_asrc_out6_ep>;
2192 };
2193 };
2194 };
2195 };
2196 };
2197 };
2198
2199 i2c@3160000 {
2200 power-monitor@42 {
2201 compatible = "ti,ina3221";
2202 reg = <0x42>;
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2205
2206 input@0 {
2207 reg = <0x0>;
2208 label = "VDD_MUX";
2209 shunt-resistor-micro-ohms = <20000>;
2210 };
2211
2212 input@1 {
2213 reg = <0x1>;
2214 label = "VDD_5V0_IO_SYS";
2215 shunt-resistor-micro-ohms = <5000>;
2216 };
2217
2218 input@2 {
2219 reg = <0x2>;
2220 label = "VDD_3V3_SYS";
2221 shunt-resistor-micro-ohms = <10000>;
2222 };
2223 };
2224
2225 power-monitor@43 {
2226 compatible = "ti,ina3221";
2227 reg = <0x43>;
2228 #address-cells = <1>;
2229 #size-cells = <0>;
2230
2231 input@0 {
2232 reg = <0x0>;
2233 label = "VDD_3V3_IO_SLP";
2234 shunt-resistor-micro-ohms = <10000>;
2235 };
2236
2237 input@1 {
2238 reg = <0x1>;
2239 label = "VDD_1V8_IO";
2240 shunt-resistor-micro-ohms = <10000>;
2241 };
2242
2243 input@2 {
2244 reg = <0x2>;
2245 label = "VDD_M2_IN";
2246 shunt-resistor-micro-ohms = <10000>;
2247 };
2248 };
2249
2250 exp1: gpio@74 {
2251 compatible = "ti,tca9539";
2252 reg = <0x74>;
2253
2254 interrupt-parent = <&gpio>;
2255 interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
2256 GPIO_ACTIVE_LOW>;
2257
2258 #gpio-cells = <2>;
2259 gpio-controller;
2260
2261 vcc-supply = <&vdd_3v3_sys>;
2262 };
2263
2264 exp2: gpio@77 {
2265 compatible = "ti,tca9539";
2266 reg = <0x77>;
2267
2268 interrupt-parent = <&gpio>;
2269 interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
2270 GPIO_ACTIVE_LOW>;
2271
2272 #gpio-cells = <2>;
2273 gpio-controller;
2274
2275 vcc-supply = <&vdd_1v8>;
2276 };
2277 };
2278
2279 /* SDMMC1 (SD/MMC) */
2280 mmc@3400000 {
2281 status = "okay";
2282
2283 vmmc-supply = <&vdd_sd>;
2284 };
2285
2286 hda@3510000 {
2287 nvidia,model = "NVIDIA Jetson TX2 HDA";
2288 status = "okay";
2289 };
2290
2291 padctl@3520000 {
2292 status = "okay";
2293
2294 avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
2295 avdd-usb-supply = <&vdd_3v3_sys>;
2296 vclamp-usb-supply = <&vdd_1v8>;
2297 vddio-hsic-supply = <&gnd>;
2298
2299 pads {
2300 usb2 {
2301 status = "okay";
2302
2303 lanes {
2304 micro_b: usb2-0 {
2305 nvidia,function = "xusb";
2306 status = "okay";
2307 };
2308
2309 usb2-1 {
2310 nvidia,function = "xusb";
2311 status = "okay";
2312 };
2313
2314 usb2-2 {
2315 nvidia,function = "xusb";
2316 status = "okay";
2317 };
2318 };
2319 };
2320
2321 usb3 {
2322 status = "okay";
2323
2324 lanes {
2325 usb3-0 {
2326 nvidia,function = "xusb";
2327 status = "okay";
2328 };
2329
2330 usb3-1 {
2331 nvidia,function = "xusb";
2332 status = "okay";
2333 };
2334
2335 usb3-2 {
2336 nvidia,function = "xusb";
2337 status = "okay";
2338 };
2339 };
2340 };
2341 };
2342
2343 ports {
2344 usb2-0 {
2345 status = "okay";
2346 mode = "otg";
2347 vbus-supply = <&vdd_usb0>;
2348 usb-role-switch;
2349
2350 connector {
2351 compatible = "gpio-usb-b-connector",
2352 "usb-b-connector";
2353 label = "micro-USB";
2354 type = "micro";
2355 vbus-gpios = <&gpio
2356 TEGRA186_MAIN_GPIO(X, 7)
2357 GPIO_ACTIVE_LOW>;
2358 id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
2359 };
2360 };
2361
2362 usb2-1 {
2363 status = "okay";
2364 mode = "host";
2365
2366 vbus-supply = <&vdd_usb1>;
2367 };
2368
2369 usb3-0 {
2370 nvidia,usb2-companion = <1>;
2371 vbus-supply = <&vdd_usb1>;
2372 status = "okay";
2373 };
2374 };
2375 };
2376
2377 usb@3530000 {
2378 status = "okay";
2379
2380 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
2381 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
2382 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
2383 phy-names = "usb2-0", "usb2-1", "usb3-0";
2384 };
2385
2386 usb@3550000 {
2387 status = "okay";
2388
2389 phys = <µ_b>;
2390 phy-names = "usb2-0";
2391 };
2392
2393 i2c@c250000 {
2394 /* carrier board ID EEPROM */
2395 eeprom@57 {
2396 compatible = "atmel,24c02";
2397 reg = <0x57>;
2398
2399 label = "system";
2400 vcc-supply = <&vdd_1v8>;
2401 address-width = <8>;
2402 pagesize = <8>;
2403 size = <256>;
2404 read-only;
2405 };
2406 };
2407
2408 pcie@10003000 {
2409 status = "okay";
2410
2411 dvdd-pex-supply = <&vdd_pex>;
2412 hvdd-pex-pll-supply = <&vdd_1v8>;
2413 hvdd-pex-supply = <&vdd_1v8>;
2414 vddio-pexctl-aud-supply = <&vdd_1v8>;
2415
2416 pci@1,0 {
2417 nvidia,num-lanes = <4>;
2418 status = "okay";
2419 };
2420
2421 pci@2,0 {
2422 nvidia,num-lanes = <0>;
2423 status = "disabled";
2424 };
2425
2426 pci@3,0 {
2427 nvidia,num-lanes = <1>;
2428 status = "disabled";
2429 };
2430 };
2431
2432 host1x@13e00000 {
2433 status = "okay";
2434
2435 dpaux@15040000 {
2436 status = "okay";
2437 };
2438
2439 display-hub@15200000 {
2440 status = "okay";
2441 };
2442
2443 dsi@15300000 {
2444 status = "disabled";
2445 };
2446
2447 /* DP on E3320 */
2448 sor@15540000 {
2449 status = "okay";
2450
2451 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2452 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2453
2454 nvidia,dpaux = <&dpaux>;
2455 };
2456
2457 sor@15580000 {
2458 status = "okay";
2459
2460 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
2461 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
2462 hdmi-supply = <&vdd_hdmi>;
2463
2464 nvidia,ddc-i2c-bus = <&ddc>;
2465 nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
2466 GPIO_ACTIVE_LOW>;
2467 };
2468
2469 dpaux@155c0000 {
2470 status = "okay";
2471 };
2472 };
2473
2474 sata@3507000 {
2475 status = "okay";
2476 };
2477
2478 gpio-keys {
2479 compatible = "gpio-keys";
2480
2481 key-power {
2482 label = "Power";
2483 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
2484 GPIO_ACTIVE_LOW>;
2485 linux,input-type = <EV_KEY>;
2486 linux,code = <KEY_POWER>;
2487 debounce-interval = <10>;
2488 wakeup-event-action = <EV_ACT_ASSERTED>;
2489 wakeup-source;
2490 };
2491
2492 key-volume-up {
2493 label = "Volume Up";
2494 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
2495 GPIO_ACTIVE_LOW>;
2496 linux,input-type = <EV_KEY>;
2497 linux,code = <KEY_VOLUMEUP>;
2498 debounce-interval = <10>;
2499 };
2500
2501 key-volume-down {
2502 label = "Volume Down";
2503 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
2504 GPIO_ACTIVE_LOW>;
2505 linux,input-type = <EV_KEY>;
2506 linux,code = <KEY_VOLUMEDOWN>;
2507 debounce-interval = <10>;
2508 };
2509 };
2510
2511 vdd_sd: regulator-vdd-sd {
2512 compatible = "regulator-fixed";
2513 regulator-name = "SD_CARD_SW_PWR";
2514 regulator-min-microvolt = <3300000>;
2515 regulator-max-microvolt = <3300000>;
2516
2517 gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
2518 enable-active-high;
2519
2520 vin-supply = <&vdd_3v3_sys>;
2521 };
2522
2523 vdd_hdmi: regulator-vdd-hdmi {
2524 compatible = "regulator-fixed";
2525 regulator-name = "VDD_HDMI_5V0";
2526 regulator-min-microvolt = <5000000>;
2527 regulator-max-microvolt = <5000000>;
2528
2529 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
2530 enable-active-high;
2531
2532 vin-supply = <&vdd_5v0_sys>;
2533 };
2534
2535 vdd_usb0: regulator-vdd-usb0 {
2536 compatible = "regulator-fixed";
2537 regulator-name = "VDD_USB0";
2538 regulator-min-microvolt = <5000000>;
2539 regulator-max-microvolt = <5000000>;
2540
2541 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
2542 enable-active-high;
2543
2544 vin-supply = <&vdd_5v0_sys>;
2545 };
2546
2547 vdd_usb1: regulator-vdd-usb1 {
2548 compatible = "regulator-fixed";
2549 regulator-name = "VDD_USB1";
2550 regulator-min-microvolt = <5000000>;
2551 regulator-max-microvolt = <5000000>;
2552
2553 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
2554 enable-active-high;
2555
2556 vin-supply = <&vdd_5v0_sys>;
2557 };
2558
2559 sound {
2560 compatible = "nvidia,tegra186-audio-graph-card";
2561 status = "okay";
2562
2563 dais = /* FE */
2564 <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
2565 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
2566 <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
2567 <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
2568 <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
2569 /* Router */
2570 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
2571 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
2572 <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
2573 <&xbar_dspk1_port>, <&xbar_dspk2_port>,
2574 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
2575 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
2576 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
2577 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
2578 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
2579 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
2580 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
2581 <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
2582 <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
2583 <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
2584 <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
2585 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
2586 <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
2587 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
2588 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
2589 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
2590 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
2591 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
2592 <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
2593 <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
2594 <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
2595 <&xbar_asrc_in7_port>,
2596 <&xbar_ope1_in_port>,
2597 /* HW accelerators */
2598 <&sfc1_out_port>, <&sfc2_out_port>,
2599 <&sfc3_out_port>, <&sfc4_out_port>,
2600 <&mvc1_out_port>, <&mvc2_out_port>,
2601 <&amx1_out_port>, <&amx2_out_port>,
2602 <&amx3_out_port>, <&amx4_out_port>,
2603 <&adx1_out1_port>, <&adx1_out2_port>,
2604 <&adx1_out3_port>, <&adx1_out4_port>,
2605 <&adx2_out1_port>, <&adx2_out2_port>,
2606 <&adx2_out3_port>, <&adx2_out4_port>,
2607 <&adx3_out1_port>, <&adx3_out2_port>,
2608 <&adx3_out3_port>, <&adx3_out4_port>,
2609 <&adx4_out1_port>, <&adx4_out2_port>,
2610 <&adx4_out3_port>, <&adx4_out4_port>,
2611 <&mixer_out1_port>, <&mixer_out2_port>,
2612 <&mixer_out3_port>, <&mixer_out4_port>,
2613 <&mixer_out5_port>,
2614 <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
2615 <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
2616 <&ope1_out_port>,
2617 /* I/O */
2618 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
2619 <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
2620 <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
2621
2622 label = "NVIDIA Jetson TX2 APE";
2623 };
2624 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|