0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra124-car.h>
0003 #include <dt-bindings/gpio/tegra-gpio.h>
0004 #include <dt-bindings/memory/tegra124-mc.h>
0005 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0006 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 #include <dt-bindings/thermal/tegra124-soctherm.h>
0009 #include <dt-bindings/soc/tegra-pmc.h>
0010
0011 #include "tegra132-peripherals-opp.dtsi"
0012
0013 / {
0014 compatible = "nvidia,tegra132", "nvidia,tegra124";
0015 interrupt-parent = <&lic>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 pcie@1003000 {
0020 compatible = "nvidia,tegra124-pcie";
0021 device_type = "pci";
0022 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
0023 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
0024 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
0025 reg-names = "pads", "afi", "cs";
0026 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0027 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0028 interrupt-names = "intr", "msi";
0029
0030 #interrupt-cells = <1>;
0031 interrupt-map-mask = <0 0 0 0>;
0032 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0033
0034 bus-range = <0x00 0xff>;
0035 #address-cells = <3>;
0036 #size-cells = <2>;
0037
0038 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
0039 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
0040 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
0041 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
0042 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
0043
0044 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
0045 <&tegra_car TEGRA124_CLK_AFI>,
0046 <&tegra_car TEGRA124_CLK_PLL_E>,
0047 <&tegra_car TEGRA124_CLK_CML0>;
0048 clock-names = "pex", "afi", "pll_e", "cml";
0049 resets = <&tegra_car 70>,
0050 <&tegra_car 72>,
0051 <&tegra_car 74>;
0052 reset-names = "pex", "afi", "pcie_x";
0053 status = "disabled";
0054
0055 pci@1,0 {
0056 device_type = "pci";
0057 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
0058 reg = <0x000800 0 0 0 0>;
0059 bus-range = <0x00 0xff>;
0060 status = "disabled";
0061
0062 #address-cells = <3>;
0063 #size-cells = <2>;
0064 ranges;
0065
0066 nvidia,num-lanes = <2>;
0067 };
0068
0069 pci@2,0 {
0070 device_type = "pci";
0071 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
0072 reg = <0x001000 0 0 0 0>;
0073 bus-range = <0x00 0xff>;
0074 status = "disabled";
0075
0076 #address-cells = <3>;
0077 #size-cells = <2>;
0078 ranges;
0079
0080 nvidia,num-lanes = <1>;
0081 };
0082 };
0083
0084 host1x@50000000 {
0085 compatible = "nvidia,tegra132-host1x",
0086 "nvidia,tegra124-host1x";
0087 reg = <0x0 0x50000000 0x0 0x00034000>;
0088 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0089 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
0090 interrupt-names = "syncpt", "host1x";
0091 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
0092 clock-names = "host1x";
0093 resets = <&tegra_car 28>;
0094 reset-names = "host1x";
0095
0096 #address-cells = <2>;
0097 #size-cells = <2>;
0098
0099 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
0100
0101 dc@54200000 {
0102 compatible = "nvidia,tegra124-dc";
0103 reg = <0x0 0x54200000 0x0 0x00040000>;
0104 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0105 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
0106 clock-names = "dc";
0107 resets = <&tegra_car 27>;
0108 reset-names = "dc";
0109
0110 iommus = <&mc TEGRA_SWGROUP_DC>;
0111
0112 nvidia,head = <0>;
0113 };
0114
0115 dc@54240000 {
0116 compatible = "nvidia,tegra124-dc";
0117 reg = <0x0 0x54240000 0x0 0x00040000>;
0118 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0119 clocks = <&tegra_car TEGRA124_CLK_DISP2>;
0120 clock-names = "dc";
0121 resets = <&tegra_car 26>;
0122 reset-names = "dc";
0123
0124 iommus = <&mc TEGRA_SWGROUP_DCB>;
0125
0126 nvidia,head = <1>;
0127 };
0128
0129 hdmi@54280000 {
0130 compatible = "nvidia,tegra124-hdmi";
0131 reg = <0x0 0x54280000 0x0 0x00040000>;
0132 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0133 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
0134 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
0135 clock-names = "hdmi", "parent";
0136 resets = <&tegra_car 51>;
0137 reset-names = "hdmi";
0138 status = "disabled";
0139 };
0140
0141 sor@54540000 {
0142 compatible = "nvidia,tegra124-sor";
0143 reg = <0x0 0x54540000 0x0 0x00040000>;
0144 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0145 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
0146 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
0147 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
0148 <&tegra_car TEGRA124_CLK_PLL_DP>,
0149 <&tegra_car TEGRA124_CLK_CLK_M>;
0150 clock-names = "sor", "out", "parent", "dp", "safe";
0151 resets = <&tegra_car 182>;
0152 reset-names = "sor";
0153 status = "disabled";
0154 };
0155
0156 dpaux: dpaux@545c0000 {
0157 compatible = "nvidia,tegra124-dpaux";
0158 reg = <0x0 0x545c0000 0x0 0x00040000>;
0159 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0160 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
0161 <&tegra_car TEGRA124_CLK_PLL_DP>;
0162 clock-names = "dpaux", "parent";
0163 resets = <&tegra_car 181>;
0164 reset-names = "dpaux";
0165 status = "disabled";
0166
0167 i2c-bus {
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170 };
0171 };
0172 };
0173
0174 gic: interrupt-controller@50041000 {
0175 compatible = "arm,cortex-a15-gic";
0176 #interrupt-cells = <3>;
0177 interrupt-controller;
0178 reg = <0x0 0x50041000 0x0 0x1000>,
0179 <0x0 0x50042000 0x0 0x2000>,
0180 <0x0 0x50044000 0x0 0x2000>,
0181 <0x0 0x50046000 0x0 0x2000>;
0182 interrupts = <GIC_PPI 9
0183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0184 interrupt-parent = <&gic>;
0185 };
0186
0187 gpu@57000000 {
0188 compatible = "nvidia,gk20a";
0189 reg = <0x0 0x57000000 0x0 0x01000000>,
0190 <0x0 0x58000000 0x0 0x01000000>;
0191 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0192 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0193 interrupt-names = "stall", "nonstall";
0194 clocks = <&tegra_car TEGRA124_CLK_GPU>,
0195 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
0196 clock-names = "gpu", "pwr";
0197 resets = <&tegra_car 184>;
0198 reset-names = "gpu";
0199 status = "disabled";
0200 };
0201
0202 lic: interrupt-controller@60004000 {
0203 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
0204 reg = <0x0 0x60004000 0x0 0x100>,
0205 <0x0 0x60004100 0x0 0x100>,
0206 <0x0 0x60004200 0x0 0x100>,
0207 <0x0 0x60004300 0x0 0x100>,
0208 <0x0 0x60004400 0x0 0x100>;
0209 interrupt-controller;
0210 #interrupt-cells = <3>;
0211 interrupt-parent = <&gic>;
0212 };
0213
0214 timer@60005000 {
0215 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
0216 reg = <0x0 0x60005000 0x0 0x400>;
0217 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0219 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0221 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0222 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0223 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
0224 clock-names = "timer";
0225 };
0226
0227 tegra_car: clock@60006000 {
0228 compatible = "nvidia,tegra132-car";
0229 reg = <0x0 0x60006000 0x0 0x1000>;
0230 #clock-cells = <1>;
0231 #reset-cells = <1>;
0232 nvidia,external-memory-controller = <&emc>;
0233 };
0234
0235 flow-controller@60007000 {
0236 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
0237 reg = <0x0 0x60007000 0x0 0x1000>;
0238 };
0239
0240 actmon@6000c800 {
0241 compatible = "nvidia,tegra124-actmon";
0242 reg = <0x0 0x6000c800 0x0 0x400>;
0243 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0244 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
0245 <&tegra_car TEGRA124_CLK_EMC>;
0246 clock-names = "actmon", "emc";
0247 resets = <&tegra_car 119>;
0248 reset-names = "actmon";
0249 operating-points-v2 = <&emc_bw_dfs_opp_table>;
0250 interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
0251 interconnect-names = "cpu-read";
0252 #cooling-cells = <2>;
0253 };
0254
0255 gpio: gpio@6000d000 {
0256 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
0257 reg = <0x0 0x6000d000 0x0 0x1000>;
0258 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0259 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0260 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0261 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0262 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0265 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0266 #gpio-cells = <2>;
0267 gpio-controller;
0268 #interrupt-cells = <2>;
0269 interrupt-controller;
0270 };
0271
0272 apbdma: dma@60020000 {
0273 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
0274 reg = <0x0 0x60020000 0x0 0x1400>;
0275 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0276 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0277 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0278 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0279 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0280 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0281 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0282 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0283 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0284 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0285 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0286 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0287 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0288 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0289 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0290 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0291 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0293 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0294 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0295 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0296 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0297 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0298 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0299 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0300 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0302 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0303 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0305 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0306 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0307 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
0308 clock-names = "dma";
0309 resets = <&tegra_car 34>;
0310 reset-names = "dma";
0311 #dma-cells = <1>;
0312 };
0313
0314 apbmisc@70000800 {
0315 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
0316 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
0317 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
0318 };
0319
0320 pinmux: pinmux@70000868 {
0321 compatible = "nvidia,tegra124-pinmux";
0322 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
0323 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
0324 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
0325 };
0326
0327 /*
0328 * There are two serial driver i.e. 8250 based simple serial
0329 * driver and APB DMA based serial driver for higher baudrate
0330 * and performance. To enable the 8250 based driver, the compatible
0331 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
0332 * the APB DMA based serial driver, the compatible is
0333 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
0334 */
0335 uarta: serial@70006000 {
0336 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0337 reg = <0x0 0x70006000 0x0 0x40>;
0338 reg-shift = <2>;
0339 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0340 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
0341 clock-names = "serial";
0342 resets = <&tegra_car 6>;
0343 reset-names = "serial";
0344 dmas = <&apbdma 8>, <&apbdma 8>;
0345 dma-names = "rx", "tx";
0346 status = "disabled";
0347 };
0348
0349 uartb: serial@70006040 {
0350 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0351 reg = <0x0 0x70006040 0x0 0x40>;
0352 reg-shift = <2>;
0353 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0354 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
0355 clock-names = "serial";
0356 resets = <&tegra_car 7>;
0357 reset-names = "serial";
0358 dmas = <&apbdma 9>, <&apbdma 9>;
0359 dma-names = "rx", "tx";
0360 status = "disabled";
0361 };
0362
0363 uartc: serial@70006200 {
0364 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0365 reg = <0x0 0x70006200 0x0 0x40>;
0366 reg-shift = <2>;
0367 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0368 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
0369 clock-names = "serial";
0370 resets = <&tegra_car 55>;
0371 reset-names = "serial";
0372 dmas = <&apbdma 10>, <&apbdma 10>;
0373 dma-names = "rx", "tx";
0374 status = "disabled";
0375 };
0376
0377 uartd: serial@70006300 {
0378 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0379 reg = <0x0 0x70006300 0x0 0x40>;
0380 reg-shift = <2>;
0381 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0382 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
0383 clock-names = "serial";
0384 resets = <&tegra_car 65>;
0385 reset-names = "serial";
0386 dmas = <&apbdma 19>, <&apbdma 19>;
0387 dma-names = "rx", "tx";
0388 status = "disabled";
0389 };
0390
0391 pwm: pwm@7000a000 {
0392 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
0393 reg = <0x0 0x7000a000 0x0 0x100>;
0394 #pwm-cells = <2>;
0395 clocks = <&tegra_car TEGRA124_CLK_PWM>;
0396 clock-names = "pwm";
0397 resets = <&tegra_car 17>;
0398 reset-names = "pwm";
0399 status = "disabled";
0400 };
0401
0402 i2c@7000c000 {
0403 compatible = "nvidia,tegra124-i2c";
0404 reg = <0x0 0x7000c000 0x0 0x100>;
0405 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0406 #address-cells = <1>;
0407 #size-cells = <0>;
0408 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
0409 clock-names = "div-clk";
0410 resets = <&tegra_car 12>;
0411 reset-names = "i2c";
0412 dmas = <&apbdma 21>, <&apbdma 21>;
0413 dma-names = "rx", "tx";
0414 status = "disabled";
0415 };
0416
0417 i2c@7000c400 {
0418 compatible = "nvidia,tegra124-i2c";
0419 reg = <0x0 0x7000c400 0x0 0x100>;
0420 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0421 #address-cells = <1>;
0422 #size-cells = <0>;
0423 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
0424 clock-names = "div-clk";
0425 resets = <&tegra_car 54>;
0426 reset-names = "i2c";
0427 dmas = <&apbdma 22>, <&apbdma 22>;
0428 dma-names = "rx", "tx";
0429 status = "disabled";
0430 };
0431
0432 i2c@7000c500 {
0433 compatible = "nvidia,tegra124-i2c";
0434 reg = <0x0 0x7000c500 0x0 0x100>;
0435 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0436 #address-cells = <1>;
0437 #size-cells = <0>;
0438 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
0439 clock-names = "div-clk";
0440 resets = <&tegra_car 67>;
0441 reset-names = "i2c";
0442 dmas = <&apbdma 23>, <&apbdma 23>;
0443 dma-names = "rx", "tx";
0444 status = "disabled";
0445 };
0446
0447 i2c@7000c700 {
0448 compatible = "nvidia,tegra124-i2c";
0449 reg = <0x0 0x7000c700 0x0 0x100>;
0450 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0451 #address-cells = <1>;
0452 #size-cells = <0>;
0453 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
0454 clock-names = "div-clk";
0455 resets = <&tegra_car 103>;
0456 reset-names = "i2c";
0457 dmas = <&apbdma 26>, <&apbdma 26>;
0458 dma-names = "rx", "tx";
0459 status = "disabled";
0460 };
0461
0462 i2c@7000d000 {
0463 compatible = "nvidia,tegra124-i2c";
0464 reg = <0x0 0x7000d000 0x0 0x100>;
0465 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0466 #address-cells = <1>;
0467 #size-cells = <0>;
0468 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
0469 clock-names = "div-clk";
0470 resets = <&tegra_car 47>;
0471 reset-names = "i2c";
0472 dmas = <&apbdma 24>, <&apbdma 24>;
0473 dma-names = "rx", "tx";
0474 status = "disabled";
0475 };
0476
0477 i2c@7000d100 {
0478 compatible = "nvidia,tegra124-i2c";
0479 reg = <0x0 0x7000d100 0x0 0x100>;
0480 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0481 #address-cells = <1>;
0482 #size-cells = <0>;
0483 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
0484 clock-names = "div-clk";
0485 resets = <&tegra_car 166>;
0486 reset-names = "i2c";
0487 dmas = <&apbdma 30>, <&apbdma 30>;
0488 dma-names = "rx", "tx";
0489 status = "disabled";
0490 };
0491
0492 spi@7000d400 {
0493 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0494 reg = <0x0 0x7000d400 0x0 0x200>;
0495 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0496 #address-cells = <1>;
0497 #size-cells = <0>;
0498 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
0499 clock-names = "spi";
0500 resets = <&tegra_car 41>;
0501 reset-names = "spi";
0502 dmas = <&apbdma 15>, <&apbdma 15>;
0503 dma-names = "rx", "tx";
0504 status = "disabled";
0505 };
0506
0507 spi@7000d600 {
0508 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0509 reg = <0x0 0x7000d600 0x0 0x200>;
0510 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0511 #address-cells = <1>;
0512 #size-cells = <0>;
0513 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
0514 clock-names = "spi";
0515 resets = <&tegra_car 44>;
0516 reset-names = "spi";
0517 dmas = <&apbdma 16>, <&apbdma 16>;
0518 dma-names = "rx", "tx";
0519 status = "disabled";
0520 };
0521
0522 spi@7000d800 {
0523 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0524 reg = <0x0 0x7000d800 0x0 0x200>;
0525 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0526 #address-cells = <1>;
0527 #size-cells = <0>;
0528 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
0529 clock-names = "spi";
0530 resets = <&tegra_car 46>;
0531 reset-names = "spi";
0532 dmas = <&apbdma 17>, <&apbdma 17>;
0533 dma-names = "rx", "tx";
0534 status = "disabled";
0535 };
0536
0537 spi@7000da00 {
0538 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0539 reg = <0x0 0x7000da00 0x0 0x200>;
0540 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0541 #address-cells = <1>;
0542 #size-cells = <0>;
0543 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
0544 clock-names = "spi";
0545 resets = <&tegra_car 68>;
0546 reset-names = "spi";
0547 dmas = <&apbdma 18>, <&apbdma 18>;
0548 dma-names = "rx", "tx";
0549 status = "disabled";
0550 };
0551
0552 spi@7000dc00 {
0553 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0554 reg = <0x0 0x7000dc00 0x0 0x200>;
0555 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0556 #address-cells = <1>;
0557 #size-cells = <0>;
0558 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
0559 clock-names = "spi";
0560 resets = <&tegra_car 104>;
0561 reset-names = "spi";
0562 dmas = <&apbdma 27>, <&apbdma 27>;
0563 dma-names = "rx", "tx";
0564 status = "disabled";
0565 };
0566
0567 spi@7000de00 {
0568 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0569 reg = <0x0 0x7000de00 0x0 0x200>;
0570 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0571 #address-cells = <1>;
0572 #size-cells = <0>;
0573 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
0574 clock-names = "spi";
0575 resets = <&tegra_car 105>;
0576 reset-names = "spi";
0577 dmas = <&apbdma 28>, <&apbdma 28>;
0578 dma-names = "rx", "tx";
0579 status = "disabled";
0580 };
0581
0582 rtc@7000e000 {
0583 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
0584 reg = <0x0 0x7000e000 0x0 0x100>;
0585 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0586 clocks = <&tegra_car TEGRA124_CLK_RTC>;
0587 clock-names = "rtc";
0588 };
0589
0590 tegra_pmc: pmc@7000e400 {
0591 compatible = "nvidia,tegra124-pmc";
0592 reg = <0x0 0x7000e400 0x0 0x400>;
0593 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
0594 clock-names = "pclk", "clk32k_in";
0595 #clock-cells = <1>;
0596 };
0597
0598 fuse@7000f800 {
0599 compatible = "nvidia,tegra124-efuse";
0600 reg = <0x0 0x7000f800 0x0 0x400>;
0601 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
0602 clock-names = "fuse";
0603 resets = <&tegra_car 39>;
0604 reset-names = "fuse";
0605 };
0606
0607 mc: memory-controller@70019000 {
0608 compatible = "nvidia,tegra132-mc";
0609 reg = <0x0 0x70019000 0x0 0x1000>;
0610 clocks = <&tegra_car TEGRA124_CLK_MC>;
0611 clock-names = "mc";
0612
0613 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0614
0615 #iommu-cells = <1>;
0616 #reset-cells = <1>;
0617 #interconnect-cells = <1>;
0618 };
0619
0620 emc: external-memory-controller@7001b000 {
0621 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
0622 reg = <0x0 0x7001b000 0x0 0x1000>;
0623 clocks = <&tegra_car TEGRA124_CLK_EMC>;
0624 clock-names = "emc";
0625
0626 nvidia,memory-controller = <&mc>;
0627 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
0628
0629 #interconnect-cells = <0>;
0630 };
0631
0632 sata@70020000 {
0633 compatible = "nvidia,tegra124-ahci";
0634 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
0635 <0x0 0x70020000 0x0 0x7000>; /* SATA */
0636 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0637 clocks = <&tegra_car TEGRA124_CLK_SATA>,
0638 <&tegra_car TEGRA124_CLK_SATA_OOB>;
0639 clock-names = "sata", "sata-oob";
0640 resets = <&tegra_car 124>,
0641 <&tegra_car 129>,
0642 <&tegra_car 123>;
0643 reset-names = "sata", "sata-cold", "sata-oob";
0644 status = "disabled";
0645 };
0646
0647 hda@70030000 {
0648 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
0649 "nvidia,tegra30-hda";
0650 reg = <0x0 0x70030000 0x0 0x10000>;
0651 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0652 clocks = <&tegra_car TEGRA124_CLK_HDA>,
0653 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
0654 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
0655 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
0656 resets = <&tegra_car 125>, /* hda */
0657 <&tegra_car 128>, /* hda2hdmi */
0658 <&tegra_car 111>; /* hda2codec_2x */
0659 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
0660 status = "disabled";
0661 };
0662
0663 usb@70090000 {
0664 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
0665 reg = <0x0 0x70090000 0x0 0x8000>,
0666 <0x0 0x70098000 0x0 0x1000>,
0667 <0x0 0x70099000 0x0 0x1000>;
0668 reg-names = "hcd", "fpci", "ipfs";
0669
0670 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0671 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0672
0673 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
0674 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
0675 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
0676 <&tegra_car TEGRA124_CLK_XUSB_SS>,
0677 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
0678 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
0679 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
0680 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
0681 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
0682 <&tegra_car TEGRA124_CLK_CLK_M>,
0683 <&tegra_car TEGRA124_CLK_PLL_E>;
0684 clock-names = "xusb_host", "xusb_host_src",
0685 "xusb_falcon_src", "xusb_ss",
0686 "xusb_ss_div2", "xusb_ss_src",
0687 "xusb_hs_src", "xusb_fs_src",
0688 "pll_u_480m", "clk_m", "pll_e";
0689 resets = <&tegra_car 89>, <&tegra_car 156>,
0690 <&tegra_car 143>;
0691 reset-names = "xusb_host", "xusb_ss", "xusb_src";
0692
0693 nvidia,xusb-padctl = <&padctl>;
0694
0695 status = "disabled";
0696 };
0697
0698 padctl: padctl@7009f000 {
0699 compatible = "nvidia,tegra132-xusb-padctl",
0700 "nvidia,tegra124-xusb-padctl";
0701 reg = <0x0 0x7009f000 0x0 0x1000>;
0702 resets = <&tegra_car 142>;
0703 reset-names = "padctl";
0704
0705 pads {
0706 usb2 {
0707 status = "disabled";
0708
0709 lanes {
0710 usb2-0 {
0711 status = "disabled";
0712 #phy-cells = <0>;
0713 };
0714
0715 usb2-1 {
0716 status = "disabled";
0717 #phy-cells = <0>;
0718 };
0719
0720 usb2-2 {
0721 status = "disabled";
0722 #phy-cells = <0>;
0723 };
0724 };
0725 };
0726
0727 ulpi {
0728 status = "disabled";
0729
0730 lanes {
0731 ulpi-0 {
0732 status = "disabled";
0733 #phy-cells = <0>;
0734 };
0735 };
0736 };
0737
0738 hsic {
0739 status = "disabled";
0740
0741 lanes {
0742 hsic-0 {
0743 status = "disabled";
0744 #phy-cells = <0>;
0745 };
0746
0747 hsic-1 {
0748 status = "disabled";
0749 #phy-cells = <0>;
0750 };
0751 };
0752 };
0753
0754 pcie {
0755 status = "disabled";
0756
0757 lanes {
0758 pcie-0 {
0759 status = "disabled";
0760 #phy-cells = <0>;
0761 };
0762
0763 pcie-1 {
0764 status = "disabled";
0765 #phy-cells = <0>;
0766 };
0767
0768 pcie-2 {
0769 status = "disabled";
0770 #phy-cells = <0>;
0771 };
0772
0773 pcie-3 {
0774 status = "disabled";
0775 #phy-cells = <0>;
0776 };
0777
0778 pcie-4 {
0779 status = "disabled";
0780 #phy-cells = <0>;
0781 };
0782 };
0783 };
0784
0785 sata {
0786 status = "disabled";
0787
0788 lanes {
0789 sata-0 {
0790 status = "disabled";
0791 #phy-cells = <0>;
0792 };
0793 };
0794 };
0795 };
0796
0797 ports {
0798 usb2-0 {
0799 status = "disabled";
0800 };
0801
0802 usb2-1 {
0803 status = "disabled";
0804 };
0805
0806 usb2-2 {
0807 status = "disabled";
0808 };
0809
0810 hsic-0 {
0811 status = "disabled";
0812 };
0813
0814 hsic-1 {
0815 status = "disabled";
0816 };
0817
0818 usb3-0 {
0819 status = "disabled";
0820 };
0821
0822 usb3-1 {
0823 status = "disabled";
0824 };
0825 };
0826 };
0827
0828 mmc@700b0000 {
0829 compatible = "nvidia,tegra124-sdhci";
0830 reg = <0x0 0x700b0000 0x0 0x200>;
0831 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0832 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
0833 clock-names = "sdhci";
0834 resets = <&tegra_car 14>;
0835 reset-names = "sdhci";
0836 status = "disabled";
0837 };
0838
0839 mmc@700b0200 {
0840 compatible = "nvidia,tegra124-sdhci";
0841 reg = <0x0 0x700b0200 0x0 0x200>;
0842 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0843 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
0844 clock-names = "sdhci";
0845 resets = <&tegra_car 9>;
0846 reset-names = "sdhci";
0847 status = "disabled";
0848 };
0849
0850 mmc@700b0400 {
0851 compatible = "nvidia,tegra124-sdhci";
0852 reg = <0x0 0x700b0400 0x0 0x200>;
0853 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0854 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
0855 clock-names = "sdhci";
0856 resets = <&tegra_car 69>;
0857 reset-names = "sdhci";
0858 status = "disabled";
0859 };
0860
0861 mmc@700b0600 {
0862 compatible = "nvidia,tegra124-sdhci";
0863 reg = <0x0 0x700b0600 0x0 0x200>;
0864 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0865 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
0866 clock-names = "sdhci";
0867 resets = <&tegra_car 15>;
0868 reset-names = "sdhci";
0869 status = "disabled";
0870 };
0871
0872 soctherm: thermal-sensor@700e2000 {
0873 compatible = "nvidia,tegra132-soctherm";
0874 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
0875 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
0876 reg-names = "soctherm-reg", "ccroc-reg";
0877 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0878 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0879 interrupt-names = "thermal", "edp";
0880 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
0881 <&tegra_car TEGRA124_CLK_SOC_THERM>;
0882 clock-names = "tsensor", "soctherm";
0883 resets = <&tegra_car 78>;
0884 reset-names = "soctherm";
0885 #thermal-sensor-cells = <1>;
0886
0887 throttle-cfgs {
0888 throttle_heavy: heavy {
0889 nvidia,priority = <100>;
0890 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
0891
0892 #cooling-cells = <2>;
0893 };
0894 };
0895 };
0896
0897 thermal-zones {
0898 cpu-thermal {
0899 polling-delay-passive = <1000>;
0900 polling-delay = <0>;
0901
0902 thermal-sensors =
0903 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
0904
0905 trips {
0906 cpu_shutdown_trip {
0907 temperature = <105000>;
0908 hysteresis = <1000>;
0909 type = "critical";
0910 };
0911
0912 cpu_throttle_trip: throttle-trip {
0913 temperature = <102000>;
0914 hysteresis = <1000>;
0915 type = "hot";
0916 };
0917 };
0918
0919 cooling-maps {
0920 map0 {
0921 trip = <&cpu_throttle_trip>;
0922 cooling-device = <&throttle_heavy 1 1>;
0923 };
0924 };
0925 };
0926
0927 mem-thermal {
0928 polling-delay-passive = <0>;
0929 polling-delay = <0>;
0930
0931 thermal-sensors =
0932 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
0933
0934 trips {
0935 mem_shutdown_trip {
0936 temperature = <101000>;
0937 hysteresis = <1000>;
0938 type = "critical";
0939 };
0940 mem_throttle_trip {
0941 temperature = <99000>;
0942 hysteresis = <1000>;
0943 type = "hot";
0944 };
0945 };
0946
0947 cooling-maps {
0948 /*
0949 * There are currently no cooling maps,
0950 * because there are no cooling devices.
0951 */
0952 };
0953 };
0954
0955 gpu-thermal {
0956 polling-delay-passive = <1000>;
0957 polling-delay = <0>;
0958
0959 thermal-sensors =
0960 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
0961
0962 trips {
0963 gpu_shutdown_trip {
0964 temperature = <101000>;
0965 hysteresis = <1000>;
0966 type = "critical";
0967 };
0968
0969 gpu_throttle_trip: throttle-trip {
0970 temperature = <99000>;
0971 hysteresis = <1000>;
0972 type = "hot";
0973 };
0974 };
0975
0976 cooling-maps {
0977 map0 {
0978 trip = <&gpu_throttle_trip>;
0979 cooling-device = <&throttle_heavy 1 1>;
0980 };
0981 };
0982 };
0983
0984 pllx-thermal {
0985 polling-delay-passive = <0>;
0986 polling-delay = <0>;
0987
0988 thermal-sensors =
0989 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
0990
0991 trips {
0992 pllx_shutdown_trip {
0993 temperature = <105000>;
0994 hysteresis = <1000>;
0995 type = "critical";
0996 };
0997 pllx_throttle_trip {
0998 temperature = <99000>;
0999 hysteresis = <1000>;
1000 type = "hot";
1001 };
1002 };
1003
1004 cooling-maps {
1005 /*
1006 * There are currently no cooling maps,
1007 * because there are no cooling devices.
1008 */
1009 };
1010 };
1011 };
1012
1013 ahub@70300000 {
1014 compatible = "nvidia,tegra124-ahub";
1015 reg = <0x0 0x70300000 0x0 0x200>,
1016 <0x0 0x70300800 0x0 0x800>,
1017 <0x0 0x70300200 0x0 0x600>;
1018 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
1020 <&tegra_car TEGRA124_CLK_APBIF>;
1021 clock-names = "d_audio", "apbif";
1022 resets = <&tegra_car 106>, /* d_audio */
1023 <&tegra_car 107>, /* apbif */
1024 <&tegra_car 30>, /* i2s0 */
1025 <&tegra_car 11>, /* i2s1 */
1026 <&tegra_car 18>, /* i2s2 */
1027 <&tegra_car 101>, /* i2s3 */
1028 <&tegra_car 102>, /* i2s4 */
1029 <&tegra_car 108>, /* dam0 */
1030 <&tegra_car 109>, /* dam1 */
1031 <&tegra_car 110>, /* dam2 */
1032 <&tegra_car 10>, /* spdif */
1033 <&tegra_car 153>, /* amx */
1034 <&tegra_car 185>, /* amx1 */
1035 <&tegra_car 154>, /* adx */
1036 <&tegra_car 180>, /* adx1 */
1037 <&tegra_car 186>, /* afc0 */
1038 <&tegra_car 187>, /* afc1 */
1039 <&tegra_car 188>, /* afc2 */
1040 <&tegra_car 189>, /* afc3 */
1041 <&tegra_car 190>, /* afc4 */
1042 <&tegra_car 191>; /* afc5 */
1043 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1044 "i2s3", "i2s4", "dam0", "dam1", "dam2",
1045 "spdif", "amx", "amx1", "adx", "adx1",
1046 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1047 dmas = <&apbdma 1>, <&apbdma 1>,
1048 <&apbdma 2>, <&apbdma 2>,
1049 <&apbdma 3>, <&apbdma 3>,
1050 <&apbdma 4>, <&apbdma 4>,
1051 <&apbdma 6>, <&apbdma 6>,
1052 <&apbdma 7>, <&apbdma 7>,
1053 <&apbdma 12>, <&apbdma 12>,
1054 <&apbdma 13>, <&apbdma 13>,
1055 <&apbdma 14>, <&apbdma 14>,
1056 <&apbdma 29>, <&apbdma 29>;
1057 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1058 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1059 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1060 "rx9", "tx9";
1061 ranges;
1062 #address-cells = <2>;
1063 #size-cells = <2>;
1064
1065 tegra_i2s0: i2s@70301000 {
1066 compatible = "nvidia,tegra124-i2s";
1067 reg = <0x0 0x70301000 0x0 0x100>;
1068 nvidia,ahub-cif-ids = <4 4>;
1069 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1070 clock-names = "i2s";
1071 resets = <&tegra_car 30>;
1072 reset-names = "i2s";
1073 status = "disabled";
1074 };
1075
1076 tegra_i2s1: i2s@70301100 {
1077 compatible = "nvidia,tegra124-i2s";
1078 reg = <0x0 0x70301100 0x0 0x100>;
1079 nvidia,ahub-cif-ids = <5 5>;
1080 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1081 clock-names = "i2s";
1082 resets = <&tegra_car 11>;
1083 reset-names = "i2s";
1084 status = "disabled";
1085 };
1086
1087 tegra_i2s2: i2s@70301200 {
1088 compatible = "nvidia,tegra124-i2s";
1089 reg = <0x0 0x70301200 0x0 0x100>;
1090 nvidia,ahub-cif-ids = <6 6>;
1091 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1092 clock-names = "i2s";
1093 resets = <&tegra_car 18>;
1094 reset-names = "i2s";
1095 status = "disabled";
1096 };
1097
1098 tegra_i2s3: i2s@70301300 {
1099 compatible = "nvidia,tegra124-i2s";
1100 reg = <0x0 0x70301300 0x0 0x100>;
1101 nvidia,ahub-cif-ids = <7 7>;
1102 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1103 clock-names = "i2s";
1104 resets = <&tegra_car 101>;
1105 reset-names = "i2s";
1106 status = "disabled";
1107 };
1108
1109 tegra_i2s4: i2s@70301400 {
1110 compatible = "nvidia,tegra124-i2s";
1111 reg = <0x0 0x70301400 0x0 0x100>;
1112 nvidia,ahub-cif-ids = <8 8>;
1113 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1114 clock-names = "i2s";
1115 resets = <&tegra_car 102>;
1116 reset-names = "i2s";
1117 status = "disabled";
1118 };
1119 };
1120
1121 usb@7d000000 {
1122 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1123 reg = <0x0 0x7d000000 0x0 0x4000>;
1124 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1125 phy_type = "utmi";
1126 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1127 clock-names = "usb";
1128 resets = <&tegra_car 22>;
1129 reset-names = "usb";
1130 nvidia,phy = <&phy1>;
1131 status = "disabled";
1132 };
1133
1134 phy1: usb-phy@7d000000 {
1135 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1136 reg = <0x0 0x7d000000 0x0 0x4000>,
1137 <0x0 0x7d000000 0x0 0x4000>;
1138 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1139 phy_type = "utmi";
1140 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1141 <&tegra_car TEGRA124_CLK_PLL_U>,
1142 <&tegra_car TEGRA124_CLK_USBD>;
1143 clock-names = "reg", "pll_u", "utmi-pads";
1144 resets = <&tegra_car 22>, <&tegra_car 22>;
1145 reset-names = "usb", "utmi-pads";
1146 #phy-cells = <0>;
1147 nvidia,hssync-start-delay = <0>;
1148 nvidia,idle-wait-delay = <17>;
1149 nvidia,elastic-limit = <16>;
1150 nvidia,term-range-adj = <6>;
1151 nvidia,xcvr-setup = <9>;
1152 nvidia,xcvr-lsfslew = <0>;
1153 nvidia,xcvr-lsrslew = <3>;
1154 nvidia,hssquelch-level = <2>;
1155 nvidia,hsdiscon-level = <5>;
1156 nvidia,xcvr-hsslew = <12>;
1157 nvidia,has-utmi-pad-registers;
1158 nvidia,pmc = <&tegra_pmc 0>;
1159 status = "disabled";
1160 };
1161
1162 usb@7d004000 {
1163 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1164 reg = <0x0 0x7d004000 0x0 0x4000>;
1165 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1166 phy_type = "utmi";
1167 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1168 clock-names = "usb";
1169 resets = <&tegra_car 58>;
1170 reset-names = "usb";
1171 nvidia,phy = <&phy2>;
1172 status = "disabled";
1173 };
1174
1175 phy2: usb-phy@7d004000 {
1176 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1177 reg = <0x0 0x7d004000 0x0 0x4000>,
1178 <0x0 0x7d000000 0x0 0x4000>;
1179 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1180 phy_type = "utmi";
1181 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1182 <&tegra_car TEGRA124_CLK_PLL_U>,
1183 <&tegra_car TEGRA124_CLK_USBD>;
1184 clock-names = "reg", "pll_u", "utmi-pads";
1185 resets = <&tegra_car 58>, <&tegra_car 22>;
1186 reset-names = "usb", "utmi-pads";
1187 #phy-cells = <0>;
1188 nvidia,hssync-start-delay = <0>;
1189 nvidia,idle-wait-delay = <17>;
1190 nvidia,elastic-limit = <16>;
1191 nvidia,term-range-adj = <6>;
1192 nvidia,xcvr-setup = <9>;
1193 nvidia,xcvr-lsfslew = <0>;
1194 nvidia,xcvr-lsrslew = <3>;
1195 nvidia,hssquelch-level = <2>;
1196 nvidia,hsdiscon-level = <5>;
1197 nvidia,xcvr-hsslew = <12>;
1198 nvidia,pmc = <&tegra_pmc 1>;
1199 status = "disabled";
1200 };
1201
1202 usb@7d008000 {
1203 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1204 reg = <0x0 0x7d008000 0x0 0x4000>;
1205 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1206 phy_type = "utmi";
1207 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1208 clock-names = "usb";
1209 resets = <&tegra_car 59>;
1210 reset-names = "usb";
1211 nvidia,phy = <&phy3>;
1212 status = "disabled";
1213 };
1214
1215 phy3: usb-phy@7d008000 {
1216 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1217 reg = <0x0 0x7d008000 0x0 0x4000>,
1218 <0x0 0x7d000000 0x0 0x4000>;
1219 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1220 phy_type = "utmi";
1221 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1222 <&tegra_car TEGRA124_CLK_PLL_U>,
1223 <&tegra_car TEGRA124_CLK_USBD>;
1224 clock-names = "reg", "pll_u", "utmi-pads";
1225 resets = <&tegra_car 59>, <&tegra_car 22>;
1226 reset-names = "usb", "utmi-pads";
1227 #phy-cells = <0>;
1228 nvidia,hssync-start-delay = <0>;
1229 nvidia,idle-wait-delay = <17>;
1230 nvidia,elastic-limit = <16>;
1231 nvidia,term-range-adj = <6>;
1232 nvidia,xcvr-setup = <9>;
1233 nvidia,xcvr-lsfslew = <0>;
1234 nvidia,xcvr-lsrslew = <3>;
1235 nvidia,hssquelch-level = <2>;
1236 nvidia,hsdiscon-level = <5>;
1237 nvidia,xcvr-hsslew = <12>;
1238 nvidia,pmc = <&tegra_pmc 2>;
1239 status = "disabled";
1240 };
1241
1242 cpus {
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1245
1246 cpu@0 {
1247 device_type = "cpu";
1248 compatible = "nvidia,tegra132-denver";
1249 reg = <0>;
1250 };
1251
1252 cpu@1 {
1253 device_type = "cpu";
1254 compatible = "nvidia,tegra132-denver";
1255 reg = <1>;
1256 };
1257 };
1258
1259 timer {
1260 compatible = "arm,armv7-timer";
1261 interrupts = <GIC_PPI 13
1262 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1263 <GIC_PPI 14
1264 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1265 <GIC_PPI 11
1266 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1267 <GIC_PPI 10
1268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1269 interrupt-parent = <&gic>;
1270 };
1271 };
