0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
0003
0004 #include "nuvoton-common-npcm8xx.dtsi"
0005
0006 / {
0007 #address-cells = <2>;
0008 #size-cells = <2>;
0009
0010 cpus {
0011 #address-cells = <2>;
0012 #size-cells = <0>;
0013
0014 cpu0: cpu@0 {
0015 device_type = "cpu";
0016 compatible = "arm,cortex-a35";
0017 clocks = <&clk NPCM8XX_CLK_CPU>;
0018 reg = <0x0 0x0>;
0019 next-level-cache = <&l2>;
0020 enable-method = "psci";
0021 };
0022
0023 cpu1: cpu@1 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a35";
0026 clocks = <&clk NPCM8XX_CLK_CPU>;
0027 reg = <0x0 0x1>;
0028 next-level-cache = <&l2>;
0029 enable-method = "psci";
0030 };
0031
0032 cpu2: cpu@2 {
0033 device_type = "cpu";
0034 compatible = "arm,cortex-a35";
0035 clocks = <&clk NPCM8XX_CLK_CPU>;
0036 reg = <0x0 0x2>;
0037 next-level-cache = <&l2>;
0038 enable-method = "psci";
0039 };
0040
0041 cpu3: cpu@3 {
0042 device_type = "cpu";
0043 compatible = "arm,cortex-a35";
0044 clocks = <&clk NPCM8XX_CLK_CPU>;
0045 reg = <0x0 0x3>;
0046 next-level-cache = <&l2>;
0047 enable-method = "psci";
0048 };
0049
0050 l2: l2-cache {
0051 compatible = "cache";
0052 };
0053 };
0054
0055 arm-pmu {
0056 compatible = "arm,cortex-a35-pmu";
0057 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
0058 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
0059 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
0060 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
0061 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0062 };
0063
0064 psci {
0065 compatible = "arm,psci-1.0";
0066 method = "smc";
0067 };
0068
0069 timer {
0070 compatible = "arm,armv8-timer";
0071 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0072 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0073 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0074 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0075 };
0076 };
