0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
0003
0004 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007
0008 / {
0009 #address-cells = <2>;
0010 #size-cells = <2>;
0011 interrupt-parent = <&gic>;
0012
0013 soc {
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016 compatible = "simple-bus";
0017 interrupt-parent = <&gic>;
0018 ranges;
0019
0020 gcr: system-controller@f0800000 {
0021 compatible = "nuvoton,npcm845-gcr", "syscon";
0022 reg = <0x0 0xf0800000 0x0 0x1000>;
0023 };
0024
0025 gic: interrupt-controller@dfff9000 {
0026 compatible = "arm,gic-400";
0027 reg = <0x0 0xdfff9000 0x0 0x1000>,
0028 <0x0 0xdfffa000 0x0 0x2000>,
0029 <0x0 0xdfffc000 0x0 0x2000>,
0030 <0x0 0xdfffe000 0x0 0x2000>;
0031 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0032 #interrupt-cells = <3>;
0033 interrupt-controller;
0034 #address-cells = <0>;
0035 ppi-partitions {
0036 ppi_cluster0: interrupt-partition-0 {
0037 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
0038 };
0039 };
0040 };
0041 };
0042
0043 ahb {
0044 #address-cells = <2>;
0045 #size-cells = <2>;
0046 compatible = "simple-bus";
0047 interrupt-parent = <&gic>;
0048 ranges;
0049
0050 rstc: reset-controller@f0801000 {
0051 compatible = "nuvoton,npcm845-reset";
0052 reg = <0x0 0xf0801000 0x0 0x78>;
0053 #reset-cells = <2>;
0054 nuvoton,sysgcr = <&gcr>;
0055 };
0056
0057 clk: clock-controller@f0801000 {
0058 compatible = "nuvoton,npcm845-clk";
0059 #clock-cells = <1>;
0060 reg = <0x0 0xf0801000 0x0 0x1000>;
0061 };
0062
0063 apb {
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 compatible = "simple-bus";
0067 interrupt-parent = <&gic>;
0068 ranges = <0x0 0x0 0xf0000000 0x00300000>,
0069 <0xfff00000 0x0 0xfff00000 0x00016000>;
0070
0071 timer0: timer@8000 {
0072 compatible = "nuvoton,npcm845-timer";
0073 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0074 reg = <0x8000 0x1C>;
0075 clocks = <&clk NPCM8XX_CLK_REFCLK>;
0076 clock-names = "refclk";
0077 };
0078
0079 serial0: serial@0 {
0080 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0081 reg = <0x0 0x1000>;
0082 clocks = <&clk NPCM8XX_CLK_UART>;
0083 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0084 reg-shift = <2>;
0085 status = "disabled";
0086 };
0087
0088 serial1: serial@1000 {
0089 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0090 reg = <0x1000 0x1000>;
0091 clocks = <&clk NPCM8XX_CLK_UART>;
0092 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0093 reg-shift = <2>;
0094 status = "disabled";
0095 };
0096
0097 serial2: serial@2000 {
0098 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0099 reg = <0x2000 0x1000>;
0100 clocks = <&clk NPCM8XX_CLK_UART>;
0101 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0102 reg-shift = <2>;
0103 status = "disabled";
0104 };
0105
0106 serial3: serial@3000 {
0107 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0108 reg = <0x3000 0x1000>;
0109 clocks = <&clk NPCM8XX_CLK_UART>;
0110 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
0111 reg-shift = <2>;
0112 status = "disabled";
0113 };
0114
0115 serial4: serial@4000 {
0116 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0117 reg = <0x4000 0x1000>;
0118 clocks = <&clk NPCM8XX_CLK_UART>;
0119 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
0120 reg-shift = <2>;
0121 status = "disabled";
0122 };
0123
0124 serial5: serial@5000 {
0125 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0126 reg = <0x5000 0x1000>;
0127 clocks = <&clk NPCM8XX_CLK_UART>;
0128 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
0129 reg-shift = <2>;
0130 status = "disabled";
0131 };
0132
0133 serial6: serial@6000 {
0134 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
0135 reg = <0x6000 0x1000>;
0136 clocks = <&clk NPCM8XX_CLK_UART>;
0137 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
0138 reg-shift = <2>;
0139 status = "disabled";
0140 };
0141
0142 watchdog0: watchdog@801c {
0143 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
0144 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0145 reg = <0x801c 0x4>;
0146 status = "disabled";
0147 clocks = <&clk NPCM8XX_CLK_REFCLK>;
0148 syscon = <&gcr>;
0149 };
0150
0151 watchdog1: watchdog@901c {
0152 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
0153 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0154 reg = <0x901c 0x4>;
0155 status = "disabled";
0156 clocks = <&clk NPCM8XX_CLK_REFCLK>;
0157 syscon = <&gcr>;
0158 };
0159
0160 watchdog2: watchdog@a01c {
0161 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
0162 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0163 reg = <0xa01c 0x4>;
0164 status = "disabled";
0165 clocks = <&clk NPCM8XX_CLK_REFCLK>;
0166 syscon = <&gcr>;
0167 };
0168 };
0169 };
0170 };
