0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 #include <dt-bindings/clock/microchip,sparx5.h>
0009
0010 / {
0011 compatible = "microchip,sparx5";
0012 interrupt-parent = <&gic>;
0013 #address-cells = <2>;
0014 #size-cells = <1>;
0015
0016 aliases {
0017 spi0 = &spi0;
0018 serial0 = &uart0;
0019 serial1 = &uart1;
0020 };
0021
0022 chosen {
0023 stdout-path = "serial0:115200n8";
0024 };
0025
0026 cpus {
0027 #address-cells = <2>;
0028 #size-cells = <0>;
0029 cpu-map {
0030 cluster0 {
0031 core0 {
0032 cpu = <&cpu0>;
0033 };
0034 core1 {
0035 cpu = <&cpu1>;
0036 };
0037 };
0038 };
0039 cpu0: cpu@0 {
0040 compatible = "arm,cortex-a53";
0041 device_type = "cpu";
0042 reg = <0x0 0x0>;
0043 enable-method = "psci";
0044 next-level-cache = <&L2_0>;
0045 };
0046 cpu1: cpu@1 {
0047 compatible = "arm,cortex-a53";
0048 device_type = "cpu";
0049 reg = <0x0 0x1>;
0050 enable-method = "psci";
0051 next-level-cache = <&L2_0>;
0052 };
0053 L2_0: l2-cache0 {
0054 compatible = "cache";
0055 };
0056 };
0057
0058 arm-pmu {
0059 compatible = "arm,cortex-a53-pmu";
0060 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0061 interrupt-affinity = <&cpu0>, <&cpu1>;
0062 };
0063
0064 psci {
0065 compatible = "arm,psci-0.2";
0066 method = "smc";
0067 };
0068
0069 timer {
0070 compatible = "arm,armv8-timer";
0071 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0072 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0073 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0074 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0075 };
0076
0077 lcpll_clk: lcpll-clk {
0078 compatible = "fixed-clock";
0079 #clock-cells = <0>;
0080 clock-frequency = <2500000000>;
0081 };
0082
0083 clks: clock-controller@61110000c {
0084 compatible = "microchip,sparx5-dpll";
0085 #clock-cells = <1>;
0086 clocks = <&lcpll_clk>;
0087 reg = <0x6 0x1110000c 0x24>;
0088 };
0089
0090 ahb_clk: ahb-clk {
0091 compatible = "fixed-clock";
0092 #clock-cells = <0>;
0093 clock-frequency = <250000000>;
0094 };
0095
0096 sys_clk: sys-clk {
0097 compatible = "fixed-clock";
0098 #clock-cells = <0>;
0099 clock-frequency = <625000000>;
0100 };
0101
0102 axi: axi@600000000 {
0103 compatible = "simple-bus";
0104 #address-cells = <2>;
0105 #size-cells = <1>;
0106 ranges;
0107
0108 gic: interrupt-controller@600300000 {
0109 compatible = "arm,gic-v3";
0110 #interrupt-cells = <3>;
0111 #address-cells = <2>;
0112 #size-cells = <2>;
0113 interrupt-controller;
0114 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
0115 <0x6 0x00340000 0xc0000>, /* GICR */
0116 <0x6 0x00200000 0x2000>, /* GICC */
0117 <0x6 0x00210000 0x2000>, /* GICV */
0118 <0x6 0x00220000 0x2000>; /* GICH */
0119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0120 };
0121
0122 cpu_ctrl: syscon@600000000 {
0123 compatible = "microchip,sparx5-cpu-syscon", "syscon",
0124 "simple-mfd";
0125 reg = <0x6 0x00000000 0xd0>;
0126 mux: mux-controller {
0127 compatible = "mmio-mux";
0128 #mux-control-cells = <0>;
0129 /*
0130 * SI_OWNER and SI2_OWNER in GENERAL_CTRL
0131 * SPI: value 9 - (SIMC,SIBM) = 0b1001
0132 * SPI2: value 6 - (SIBM,SIMC) = 0b0110
0133 */
0134 mux-reg-masks = <0x88 0xf0>;
0135 };
0136 };
0137
0138 reset: reset-controller@611010008 {
0139 compatible = "microchip,sparx5-switch-reset";
0140 reg = <0x6 0x11010008 0x4>;
0141 reg-names = "gcb";
0142 #reset-cells = <1>;
0143 cpu-syscon = <&cpu_ctrl>;
0144 };
0145
0146 uart0: serial@600100000 {
0147 pinctrl-0 = <&uart_pins>;
0148 pinctrl-names = "default";
0149 compatible = "ns16550a";
0150 reg = <0x6 0x00100000 0x20>;
0151 clocks = <&ahb_clk>;
0152 reg-io-width = <4>;
0153 reg-shift = <2>;
0154 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0155
0156 status = "disabled";
0157 };
0158
0159 uart1: serial@600102000 {
0160 pinctrl-0 = <&uart2_pins>;
0161 pinctrl-names = "default";
0162 compatible = "ns16550a";
0163 reg = <0x6 0x00102000 0x20>;
0164 clocks = <&ahb_clk>;
0165 reg-io-width = <4>;
0166 reg-shift = <2>;
0167 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0168
0169 status = "disabled";
0170 };
0171
0172 spi0: spi@600104000 {
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175 compatible = "microchip,sparx5-spi";
0176 reg = <0x6 0x00104000 0x40>;
0177 num-cs = <16>;
0178 reg-io-width = <4>;
0179 reg-shift = <2>;
0180 clocks = <&ahb_clk>;
0181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0182 status = "disabled";
0183 };
0184
0185 timer1: timer@600105000 {
0186 compatible = "snps,dw-apb-timer";
0187 reg = <0x6 0x00105000 0x1000>;
0188 clocks = <&ahb_clk>;
0189 clock-names = "timer";
0190 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0191 };
0192
0193 sdhci0: mmc@600800000 {
0194 compatible = "microchip,dw-sparx5-sdhci";
0195 status = "disabled";
0196 reg = <0x6 0x00800000 0x1000>;
0197 pinctrl-0 = <&emmc_pins>;
0198 pinctrl-names = "default";
0199 clocks = <&clks CLK_ID_AUX1>;
0200 clock-names = "core";
0201 assigned-clocks = <&clks CLK_ID_AUX1>;
0202 assigned-clock-rates = <800000000>;
0203 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0204 bus-width = <8>;
0205 };
0206
0207 gpio: pinctrl@6110101e0 {
0208 compatible = "microchip,sparx5-pinctrl";
0209 reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
0210 gpio-controller;
0211 #gpio-cells = <2>;
0212 gpio-ranges = <&gpio 0 0 64>;
0213 interrupt-controller;
0214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0215 #interrupt-cells = <2>;
0216
0217 cs1_pins: cs1-pins {
0218 pins = "GPIO_16";
0219 function = "si";
0220 };
0221
0222 cs2_pins: cs2-pins {
0223 pins = "GPIO_17";
0224 function = "si";
0225 };
0226
0227 cs3_pins: cs3-pins {
0228 pins = "GPIO_18";
0229 function = "si";
0230 };
0231
0232 si2_pins: si2-pins {
0233 pins = "GPIO_39", "GPIO_40", "GPIO_41";
0234 function = "si2";
0235 };
0236
0237 sgpio0_pins: sgpio-pins {
0238 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
0239 function = "sg0";
0240 };
0241
0242 sgpio1_pins: sgpio1-pins {
0243 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
0244 function = "sg1";
0245 };
0246
0247 sgpio2_pins: sgpio2-pins {
0248 pins = "GPIO_30", "GPIO_31", "GPIO_32",
0249 "GPIO_33";
0250 function = "sg2";
0251 };
0252
0253 uart_pins: uart-pins {
0254 pins = "GPIO_10", "GPIO_11";
0255 function = "uart";
0256 };
0257
0258 uart2_pins: uart2-pins {
0259 pins = "GPIO_26", "GPIO_27";
0260 function = "uart2";
0261 };
0262
0263 i2c_pins: i2c-pins {
0264 pins = "GPIO_14", "GPIO_15";
0265 function = "twi";
0266 };
0267
0268 i2c2_pins: i2c2-pins {
0269 pins = "GPIO_28", "GPIO_29";
0270 function = "twi2";
0271 };
0272
0273 emmc_pins: emmc-pins {
0274 pins = "GPIO_34", "GPIO_35", "GPIO_36",
0275 "GPIO_37", "GPIO_38", "GPIO_39",
0276 "GPIO_40", "GPIO_41", "GPIO_42",
0277 "GPIO_43", "GPIO_44", "GPIO_45",
0278 "GPIO_46", "GPIO_47";
0279 function = "emmc";
0280 };
0281
0282 miim1_pins: miim1-pins {
0283 pins = "GPIO_56", "GPIO_57";
0284 function = "miim";
0285 };
0286
0287 miim2_pins: miim2-pins {
0288 pins = "GPIO_58", "GPIO_59";
0289 function = "miim";
0290 };
0291
0292 miim3_pins: miim3-pins {
0293 pins = "GPIO_52", "GPIO_53";
0294 function = "miim";
0295 };
0296 };
0297
0298 sgpio0: gpio@61101036c {
0299 #address-cells = <1>;
0300 #size-cells = <0>;
0301 compatible = "microchip,sparx5-sgpio";
0302 status = "disabled";
0303 clocks = <&sys_clk>;
0304 pinctrl-0 = <&sgpio0_pins>;
0305 pinctrl-names = "default";
0306 resets = <&reset 0>;
0307 reset-names = "switch";
0308 reg = <0x6 0x1101036c 0x100>;
0309 sgpio_in0: gpio@0 {
0310 compatible = "microchip,sparx5-sgpio-bank";
0311 reg = <0>;
0312 gpio-controller;
0313 #gpio-cells = <3>;
0314 ngpios = <96>;
0315 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0316 interrupt-controller;
0317 #interrupt-cells = <3>;
0318 };
0319 sgpio_out0: gpio@1 {
0320 compatible = "microchip,sparx5-sgpio-bank";
0321 reg = <1>;
0322 gpio-controller;
0323 #gpio-cells = <3>;
0324 ngpios = <96>;
0325 };
0326 };
0327
0328 sgpio1: gpio@611010484 {
0329 #address-cells = <1>;
0330 #size-cells = <0>;
0331 compatible = "microchip,sparx5-sgpio";
0332 status = "disabled";
0333 clocks = <&sys_clk>;
0334 pinctrl-0 = <&sgpio1_pins>;
0335 pinctrl-names = "default";
0336 resets = <&reset 0>;
0337 reset-names = "switch";
0338 reg = <0x6 0x11010484 0x100>;
0339 sgpio_in1: gpio@0 {
0340 compatible = "microchip,sparx5-sgpio-bank";
0341 reg = <0>;
0342 gpio-controller;
0343 #gpio-cells = <3>;
0344 ngpios = <96>;
0345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0346 interrupt-controller;
0347 #interrupt-cells = <3>;
0348 };
0349 sgpio_out1: gpio@1 {
0350 compatible = "microchip,sparx5-sgpio-bank";
0351 reg = <1>;
0352 gpio-controller;
0353 #gpio-cells = <3>;
0354 ngpios = <96>;
0355 };
0356 };
0357
0358 sgpio2: gpio@61101059c {
0359 #address-cells = <1>;
0360 #size-cells = <0>;
0361 compatible = "microchip,sparx5-sgpio";
0362 status = "disabled";
0363 clocks = <&sys_clk>;
0364 pinctrl-0 = <&sgpio2_pins>;
0365 pinctrl-names = "default";
0366 resets = <&reset 0>;
0367 reset-names = "switch";
0368 reg = <0x6 0x1101059c 0x100>;
0369 sgpio_in2: gpio@0 {
0370 reg = <0>;
0371 compatible = "microchip,sparx5-sgpio-bank";
0372 gpio-controller;
0373 #gpio-cells = <3>;
0374 ngpios = <96>;
0375 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0376 interrupt-controller;
0377 #interrupt-cells = <3>;
0378 };
0379 sgpio_out2: gpio@1 {
0380 compatible = "microchip,sparx5-sgpio-bank";
0381 reg = <1>;
0382 gpio-controller;
0383 #gpio-cells = <3>;
0384 ngpios = <96>;
0385 };
0386 };
0387
0388 i2c0: i2c@600101000 {
0389 compatible = "snps,designware-i2c";
0390 status = "disabled";
0391 pinctrl-0 = <&i2c_pins>;
0392 pinctrl-names = "default";
0393 reg = <0x6 0x00101000 0x100>;
0394 #address-cells = <1>;
0395 #size-cells = <0>;
0396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0397 i2c-sda-hold-time-ns = <300>;
0398 clock-frequency = <100000>;
0399 clocks = <&ahb_clk>;
0400 };
0401
0402 i2c1: i2c@600103000 {
0403 compatible = "snps,designware-i2c";
0404 status = "disabled";
0405 pinctrl-0 = <&i2c2_pins>;
0406 pinctrl-names = "default";
0407 reg = <0x6 0x00103000 0x100>;
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0411 i2c-sda-hold-time-ns = <300>;
0412 clock-frequency = <100000>;
0413 clocks = <&ahb_clk>;
0414 };
0415
0416 tmon0: tmon@610508110 {
0417 compatible = "microchip,sparx5-temp";
0418 reg = <0x6 0x10508110 0xc>;
0419 #thermal-sensor-cells = <0>;
0420 clocks = <&ahb_clk>;
0421 };
0422
0423 mdio0: mdio@6110102b0 {
0424 compatible = "mscc,ocelot-miim";
0425 status = "disabled";
0426 #address-cells = <1>;
0427 #size-cells = <0>;
0428 reg = <0x6 0x110102b0 0x24>;
0429 };
0430
0431 mdio1: mdio@6110102d4 {
0432 compatible = "mscc,ocelot-miim";
0433 status = "disabled";
0434 pinctrl-0 = <&miim1_pins>;
0435 pinctrl-names = "default";
0436 #address-cells = <1>;
0437 #size-cells = <0>;
0438 reg = <0x6 0x110102d4 0x24>;
0439 };
0440
0441 mdio2: mdio@6110102f8 {
0442 compatible = "mscc,ocelot-miim";
0443 status = "disabled";
0444 pinctrl-0 = <&miim2_pins>;
0445 pinctrl-names = "default";
0446 #address-cells = <1>;
0447 #size-cells = <0>;
0448 reg = <0x6 0x110102d4 0x24>;
0449 };
0450
0451 mdio3: mdio@61101031c {
0452 compatible = "mscc,ocelot-miim";
0453 status = "disabled";
0454 pinctrl-0 = <&miim3_pins>;
0455 pinctrl-names = "default";
0456 #address-cells = <1>;
0457 #size-cells = <0>;
0458 reg = <0x6 0x1101031c 0x24>;
0459 };
0460
0461 serdes: serdes@10808000 {
0462 compatible = "microchip,sparx5-serdes";
0463 #phy-cells = <1>;
0464 clocks = <&sys_clk>;
0465 reg = <0x6 0x10808000 0x5d0000>;
0466 };
0467
0468 switch: switch@0x600000000 {
0469 compatible = "microchip,sparx5-switch";
0470 reg = <0x6 0 0x401000>,
0471 <0x6 0x10004000 0x7fc000>,
0472 <0x6 0x11010000 0xaf0000>;
0473 reg-names = "cpu", "dev", "gcb";
0474 interrupt-names = "xtr", "fdma", "ptp";
0475 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0476 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0477 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0478 resets = <&reset 0>;
0479 reset-names = "switch";
0480 };
0481 };
0482 };
