0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (c) 2021 MediaTek Inc.
0004 * Author: Seiya Wang <seiya.wang@mediatek.com>
0005 */
0006
0007 /dts-v1/;
0008 #include <dt-bindings/clock/mt8195-clk.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/phy/phy.h>
0012 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
0013
0014 / {
0015 compatible = "mediatek,mt8195";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 cpu0: cpu@0 {
0025 device_type = "cpu";
0026 compatible = "arm,cortex-a55";
0027 reg = <0x000>;
0028 enable-method = "psci";
0029 clock-frequency = <1701000000>;
0030 capacity-dmips-mhz = <578>;
0031 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
0032 next-level-cache = <&l2_0>;
0033 #cooling-cells = <2>;
0034 };
0035
0036 cpu1: cpu@100 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a55";
0039 reg = <0x100>;
0040 enable-method = "psci";
0041 clock-frequency = <1701000000>;
0042 capacity-dmips-mhz = <578>;
0043 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
0044 next-level-cache = <&l2_0>;
0045 #cooling-cells = <2>;
0046 };
0047
0048 cpu2: cpu@200 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a55";
0051 reg = <0x200>;
0052 enable-method = "psci";
0053 clock-frequency = <1701000000>;
0054 capacity-dmips-mhz = <578>;
0055 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
0056 next-level-cache = <&l2_0>;
0057 #cooling-cells = <2>;
0058 };
0059
0060 cpu3: cpu@300 {
0061 device_type = "cpu";
0062 compatible = "arm,cortex-a55";
0063 reg = <0x300>;
0064 enable-method = "psci";
0065 clock-frequency = <1701000000>;
0066 capacity-dmips-mhz = <578>;
0067 cpu-idle-states = <&cpu_off_l &cluster_off_l>;
0068 next-level-cache = <&l2_0>;
0069 #cooling-cells = <2>;
0070 };
0071
0072 cpu4: cpu@400 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a78";
0075 reg = <0x400>;
0076 enable-method = "psci";
0077 clock-frequency = <2171000000>;
0078 capacity-dmips-mhz = <1024>;
0079 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
0080 next-level-cache = <&l2_1>;
0081 #cooling-cells = <2>;
0082 };
0083
0084 cpu5: cpu@500 {
0085 device_type = "cpu";
0086 compatible = "arm,cortex-a78";
0087 reg = <0x500>;
0088 enable-method = "psci";
0089 clock-frequency = <2171000000>;
0090 capacity-dmips-mhz = <1024>;
0091 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
0092 next-level-cache = <&l2_1>;
0093 #cooling-cells = <2>;
0094 };
0095
0096 cpu6: cpu@600 {
0097 device_type = "cpu";
0098 compatible = "arm,cortex-a78";
0099 reg = <0x600>;
0100 enable-method = "psci";
0101 clock-frequency = <2171000000>;
0102 capacity-dmips-mhz = <1024>;
0103 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
0104 next-level-cache = <&l2_1>;
0105 #cooling-cells = <2>;
0106 };
0107
0108 cpu7: cpu@700 {
0109 device_type = "cpu";
0110 compatible = "arm,cortex-a78";
0111 reg = <0x700>;
0112 enable-method = "psci";
0113 clock-frequency = <2171000000>;
0114 capacity-dmips-mhz = <1024>;
0115 cpu-idle-states = <&cpu_off_b &cluster_off_b>;
0116 next-level-cache = <&l2_1>;
0117 #cooling-cells = <2>;
0118 };
0119
0120 cpu-map {
0121 cluster0 {
0122 core0 {
0123 cpu = <&cpu0>;
0124 };
0125
0126 core1 {
0127 cpu = <&cpu1>;
0128 };
0129
0130 core2 {
0131 cpu = <&cpu2>;
0132 };
0133
0134 core3 {
0135 cpu = <&cpu3>;
0136 };
0137 };
0138
0139 cluster1 {
0140 core0 {
0141 cpu = <&cpu4>;
0142 };
0143
0144 core1 {
0145 cpu = <&cpu5>;
0146 };
0147
0148 core2 {
0149 cpu = <&cpu6>;
0150 };
0151
0152 core3 {
0153 cpu = <&cpu7>;
0154 };
0155 };
0156 };
0157
0158 idle-states {
0159 entry-method = "psci";
0160
0161 cpu_off_l: cpu-off-l {
0162 compatible = "arm,idle-state";
0163 arm,psci-suspend-param = <0x00010001>;
0164 local-timer-stop;
0165 entry-latency-us = <50>;
0166 exit-latency-us = <95>;
0167 min-residency-us = <580>;
0168 };
0169
0170 cpu_off_b: cpu-off-b {
0171 compatible = "arm,idle-state";
0172 arm,psci-suspend-param = <0x00010001>;
0173 local-timer-stop;
0174 entry-latency-us = <45>;
0175 exit-latency-us = <140>;
0176 min-residency-us = <740>;
0177 };
0178
0179 cluster_off_l: cluster-off-l {
0180 compatible = "arm,idle-state";
0181 arm,psci-suspend-param = <0x01010002>;
0182 local-timer-stop;
0183 entry-latency-us = <55>;
0184 exit-latency-us = <155>;
0185 min-residency-us = <840>;
0186 };
0187
0188 cluster_off_b: cluster-off-b {
0189 compatible = "arm,idle-state";
0190 arm,psci-suspend-param = <0x01010002>;
0191 local-timer-stop;
0192 entry-latency-us = <50>;
0193 exit-latency-us = <200>;
0194 min-residency-us = <1000>;
0195 };
0196 };
0197
0198 l2_0: l2-cache0 {
0199 compatible = "cache";
0200 next-level-cache = <&l3_0>;
0201 };
0202
0203 l2_1: l2-cache1 {
0204 compatible = "cache";
0205 next-level-cache = <&l3_0>;
0206 };
0207
0208 l3_0: l3-cache {
0209 compatible = "cache";
0210 };
0211 };
0212
0213 dsu-pmu {
0214 compatible = "arm,dsu-pmu";
0215 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
0216 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
0217 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
0218 };
0219
0220 clk26m: oscillator-26m {
0221 compatible = "fixed-clock";
0222 #clock-cells = <0>;
0223 clock-frequency = <26000000>;
0224 clock-output-names = "clk26m";
0225 };
0226
0227 clk32k: oscillator-32k {
0228 compatible = "fixed-clock";
0229 #clock-cells = <0>;
0230 clock-frequency = <32768>;
0231 clock-output-names = "clk32k";
0232 };
0233
0234 pmu-a55 {
0235 compatible = "arm,cortex-a55-pmu";
0236 interrupt-parent = <&gic>;
0237 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
0238 };
0239
0240 pmu-a78 {
0241 compatible = "arm,cortex-a78-pmu";
0242 interrupt-parent = <&gic>;
0243 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
0244 };
0245
0246 psci {
0247 compatible = "arm,psci-1.0";
0248 method = "smc";
0249 };
0250
0251 timer: timer {
0252 compatible = "arm,armv8-timer";
0253 interrupt-parent = <&gic>;
0254 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
0255 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
0256 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
0257 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
0258 };
0259
0260 soc {
0261 #address-cells = <2>;
0262 #size-cells = <2>;
0263 compatible = "simple-bus";
0264 ranges;
0265
0266 gic: interrupt-controller@c000000 {
0267 compatible = "arm,gic-v3";
0268 #interrupt-cells = <4>;
0269 #redistributor-regions = <1>;
0270 interrupt-parent = <&gic>;
0271 interrupt-controller;
0272 reg = <0 0x0c000000 0 0x40000>,
0273 <0 0x0c040000 0 0x200000>;
0274 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
0275
0276 ppi-partitions {
0277 ppi_cluster0: interrupt-partition-0 {
0278 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
0279 };
0280
0281 ppi_cluster1: interrupt-partition-1 {
0282 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
0283 };
0284 };
0285 };
0286
0287 topckgen: syscon@10000000 {
0288 compatible = "mediatek,mt8195-topckgen", "syscon";
0289 reg = <0 0x10000000 0 0x1000>;
0290 #clock-cells = <1>;
0291 };
0292
0293 infracfg_ao: syscon@10001000 {
0294 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
0295 reg = <0 0x10001000 0 0x1000>;
0296 #clock-cells = <1>;
0297 #reset-cells = <1>;
0298 };
0299
0300 pericfg: syscon@10003000 {
0301 compatible = "mediatek,mt8195-pericfg", "syscon";
0302 reg = <0 0x10003000 0 0x1000>;
0303 #clock-cells = <1>;
0304 };
0305
0306 pio: pinctrl@10005000 {
0307 compatible = "mediatek,mt8195-pinctrl";
0308 reg = <0 0x10005000 0 0x1000>,
0309 <0 0x11d10000 0 0x1000>,
0310 <0 0x11d30000 0 0x1000>,
0311 <0 0x11d40000 0 0x1000>,
0312 <0 0x11e20000 0 0x1000>,
0313 <0 0x11eb0000 0 0x1000>,
0314 <0 0x11f40000 0 0x1000>,
0315 <0 0x1000b000 0 0x1000>;
0316 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
0317 "iocfg_br", "iocfg_lm", "iocfg_rb",
0318 "iocfg_tl", "eint";
0319 gpio-controller;
0320 #gpio-cells = <2>;
0321 gpio-ranges = <&pio 0 0 144>;
0322 interrupt-controller;
0323 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
0324 #interrupt-cells = <2>;
0325 };
0326
0327 watchdog: watchdog@10007000 {
0328 compatible = "mediatek,mt8195-wdt",
0329 "mediatek,mt6589-wdt";
0330 reg = <0 0x10007000 0 0x100>;
0331 };
0332
0333 apmixedsys: syscon@1000c000 {
0334 compatible = "mediatek,mt8195-apmixedsys", "syscon";
0335 reg = <0 0x1000c000 0 0x1000>;
0336 #clock-cells = <1>;
0337 };
0338
0339 systimer: timer@10017000 {
0340 compatible = "mediatek,mt8195-timer",
0341 "mediatek,mt6765-timer";
0342 reg = <0 0x10017000 0 0x1000>;
0343 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
0344 clocks = <&topckgen CLK_TOP_CLK26M_D2>;
0345 };
0346
0347 pwrap: pwrap@10024000 {
0348 compatible = "mediatek,mt8195-pwrap", "syscon";
0349 reg = <0 0x10024000 0 0x1000>;
0350 reg-names = "pwrap";
0351 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
0352 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
0353 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
0354 clock-names = "spi", "wrap";
0355 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
0356 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
0357 };
0358
0359 scp_adsp: clock-controller@10720000 {
0360 compatible = "mediatek,mt8195-scp_adsp";
0361 reg = <0 0x10720000 0 0x1000>;
0362 #clock-cells = <1>;
0363 };
0364
0365 uart0: serial@11001100 {
0366 compatible = "mediatek,mt8195-uart",
0367 "mediatek,mt6577-uart";
0368 reg = <0 0x11001100 0 0x100>;
0369 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
0370 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
0371 clock-names = "baud", "bus";
0372 status = "disabled";
0373 };
0374
0375 uart1: serial@11001200 {
0376 compatible = "mediatek,mt8195-uart",
0377 "mediatek,mt6577-uart";
0378 reg = <0 0x11001200 0 0x100>;
0379 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
0380 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
0381 clock-names = "baud", "bus";
0382 status = "disabled";
0383 };
0384
0385 uart2: serial@11001300 {
0386 compatible = "mediatek,mt8195-uart",
0387 "mediatek,mt6577-uart";
0388 reg = <0 0x11001300 0 0x100>;
0389 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
0390 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
0391 clock-names = "baud", "bus";
0392 status = "disabled";
0393 };
0394
0395 uart3: serial@11001400 {
0396 compatible = "mediatek,mt8195-uart",
0397 "mediatek,mt6577-uart";
0398 reg = <0 0x11001400 0 0x100>;
0399 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
0400 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
0401 clock-names = "baud", "bus";
0402 status = "disabled";
0403 };
0404
0405 uart4: serial@11001500 {
0406 compatible = "mediatek,mt8195-uart",
0407 "mediatek,mt6577-uart";
0408 reg = <0 0x11001500 0 0x100>;
0409 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
0410 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
0411 clock-names = "baud", "bus";
0412 status = "disabled";
0413 };
0414
0415 uart5: serial@11001600 {
0416 compatible = "mediatek,mt8195-uart",
0417 "mediatek,mt6577-uart";
0418 reg = <0 0x11001600 0 0x100>;
0419 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
0420 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
0421 clock-names = "baud", "bus";
0422 status = "disabled";
0423 };
0424
0425 auxadc: auxadc@11002000 {
0426 compatible = "mediatek,mt8195-auxadc",
0427 "mediatek,mt8173-auxadc";
0428 reg = <0 0x11002000 0 0x1000>;
0429 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
0430 clock-names = "main";
0431 #io-channel-cells = <1>;
0432 status = "disabled";
0433 };
0434
0435 pericfg_ao: syscon@11003000 {
0436 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
0437 reg = <0 0x11003000 0 0x1000>;
0438 #clock-cells = <1>;
0439 };
0440
0441 spi0: spi@1100a000 {
0442 compatible = "mediatek,mt8195-spi",
0443 "mediatek,mt6765-spi";
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 reg = <0 0x1100a000 0 0x1000>;
0447 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
0448 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
0449 <&topckgen CLK_TOP_SPI>,
0450 <&infracfg_ao CLK_INFRA_AO_SPI0>;
0451 clock-names = "parent-clk", "sel-clk", "spi-clk";
0452 status = "disabled";
0453 };
0454
0455 spi1: spi@11010000 {
0456 compatible = "mediatek,mt8195-spi",
0457 "mediatek,mt6765-spi";
0458 #address-cells = <1>;
0459 #size-cells = <0>;
0460 reg = <0 0x11010000 0 0x1000>;
0461 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
0462 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
0463 <&topckgen CLK_TOP_SPI>,
0464 <&infracfg_ao CLK_INFRA_AO_SPI1>;
0465 clock-names = "parent-clk", "sel-clk", "spi-clk";
0466 status = "disabled";
0467 };
0468
0469 spi2: spi@11012000 {
0470 compatible = "mediatek,mt8195-spi",
0471 "mediatek,mt6765-spi";
0472 #address-cells = <1>;
0473 #size-cells = <0>;
0474 reg = <0 0x11012000 0 0x1000>;
0475 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
0476 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
0477 <&topckgen CLK_TOP_SPI>,
0478 <&infracfg_ao CLK_INFRA_AO_SPI2>;
0479 clock-names = "parent-clk", "sel-clk", "spi-clk";
0480 status = "disabled";
0481 };
0482
0483 spi3: spi@11013000 {
0484 compatible = "mediatek,mt8195-spi",
0485 "mediatek,mt6765-spi";
0486 #address-cells = <1>;
0487 #size-cells = <0>;
0488 reg = <0 0x11013000 0 0x1000>;
0489 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
0490 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
0491 <&topckgen CLK_TOP_SPI>,
0492 <&infracfg_ao CLK_INFRA_AO_SPI3>;
0493 clock-names = "parent-clk", "sel-clk", "spi-clk";
0494 status = "disabled";
0495 };
0496
0497 spi4: spi@11018000 {
0498 compatible = "mediatek,mt8195-spi",
0499 "mediatek,mt6765-spi";
0500 #address-cells = <1>;
0501 #size-cells = <0>;
0502 reg = <0 0x11018000 0 0x1000>;
0503 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
0504 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
0505 <&topckgen CLK_TOP_SPI>,
0506 <&infracfg_ao CLK_INFRA_AO_SPI4>;
0507 clock-names = "parent-clk", "sel-clk", "spi-clk";
0508 status = "disabled";
0509 };
0510
0511 spi5: spi@11019000 {
0512 compatible = "mediatek,mt8195-spi",
0513 "mediatek,mt6765-spi";
0514 #address-cells = <1>;
0515 #size-cells = <0>;
0516 reg = <0 0x11019000 0 0x1000>;
0517 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
0518 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
0519 <&topckgen CLK_TOP_SPI>,
0520 <&infracfg_ao CLK_INFRA_AO_SPI5>;
0521 clock-names = "parent-clk", "sel-clk", "spi-clk";
0522 status = "disabled";
0523 };
0524
0525 spis0: spi@1101d000 {
0526 compatible = "mediatek,mt8195-spi-slave";
0527 reg = <0 0x1101d000 0 0x1000>;
0528 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
0529 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
0530 clock-names = "spi";
0531 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
0532 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
0533 status = "disabled";
0534 };
0535
0536 spis1: spi@1101e000 {
0537 compatible = "mediatek,mt8195-spi-slave";
0538 reg = <0 0x1101e000 0 0x1000>;
0539 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
0540 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
0541 clock-names = "spi";
0542 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
0543 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
0544 status = "disabled";
0545 };
0546
0547 xhci0: usb@11200000 {
0548 compatible = "mediatek,mt8195-xhci",
0549 "mediatek,mtk-xhci";
0550 reg = <0 0x11200000 0 0x1000>,
0551 <0 0x11203e00 0 0x0100>;
0552 reg-names = "mac", "ippc";
0553 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
0554 phys = <&u2port0 PHY_TYPE_USB2>,
0555 <&u3port0 PHY_TYPE_USB3>;
0556 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
0557 <&topckgen CLK_TOP_SSUSB_XHCI>;
0558 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
0559 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
0560 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
0561 <&topckgen CLK_TOP_SSUSB_REF>,
0562 <&apmixedsys CLK_APMIXED_USB1PLL>,
0563 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
0564 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
0565 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
0566 wakeup-source;
0567 status = "disabled";
0568 };
0569
0570 mmc0: mmc@11230000 {
0571 compatible = "mediatek,mt8195-mmc",
0572 "mediatek,mt8183-mmc";
0573 reg = <0 0x11230000 0 0x10000>,
0574 <0 0x11f50000 0 0x1000>;
0575 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
0576 clocks = <&topckgen CLK_TOP_MSDC50_0>,
0577 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
0578 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
0579 clock-names = "source", "hclk", "source_cg";
0580 status = "disabled";
0581 };
0582
0583 mmc1: mmc@11240000 {
0584 compatible = "mediatek,mt8195-mmc",
0585 "mediatek,mt8183-mmc";
0586 reg = <0 0x11240000 0 0x1000>,
0587 <0 0x11c70000 0 0x1000>;
0588 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
0589 clocks = <&topckgen CLK_TOP_MSDC30_1>,
0590 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
0591 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
0592 clock-names = "source", "hclk", "source_cg";
0593 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
0594 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
0595 status = "disabled";
0596 };
0597
0598 mmc2: mmc@11250000 {
0599 compatible = "mediatek,mt8195-mmc",
0600 "mediatek,mt8183-mmc";
0601 reg = <0 0x11250000 0 0x1000>,
0602 <0 0x11e60000 0 0x1000>;
0603 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
0604 clocks = <&topckgen CLK_TOP_MSDC30_2>,
0605 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
0606 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
0607 clock-names = "source", "hclk", "source_cg";
0608 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
0609 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
0610 status = "disabled";
0611 };
0612
0613 xhci1: usb@11290000 {
0614 compatible = "mediatek,mt8195-xhci",
0615 "mediatek,mtk-xhci";
0616 reg = <0 0x11290000 0 0x1000>,
0617 <0 0x11293e00 0 0x0100>;
0618 reg-names = "mac", "ippc";
0619 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
0620 phys = <&u2port1 PHY_TYPE_USB2>;
0621 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
0622 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
0623 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
0624 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
0625 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
0626 <&topckgen CLK_TOP_SSUSB_P1_REF>,
0627 <&apmixedsys CLK_APMIXED_USB1PLL>,
0628 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
0629 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
0630 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
0631 wakeup-source;
0632 status = "disabled";
0633 };
0634
0635 xhci2: usb@112a0000 {
0636 compatible = "mediatek,mt8195-xhci",
0637 "mediatek,mtk-xhci";
0638 reg = <0 0x112a0000 0 0x1000>,
0639 <0 0x112a3e00 0 0x0100>;
0640 reg-names = "mac", "ippc";
0641 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
0642 phys = <&u2port2 PHY_TYPE_USB2>;
0643 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
0644 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
0645 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
0646 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
0647 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
0648 <&topckgen CLK_TOP_SSUSB_P2_REF>,
0649 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
0650 clock-names = "sys_ck", "ref_ck", "xhci_ck";
0651 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
0652 wakeup-source;
0653 status = "disabled";
0654 };
0655
0656 xhci3: usb@112b0000 {
0657 compatible = "mediatek,mt8195-xhci",
0658 "mediatek,mtk-xhci";
0659 reg = <0 0x112b0000 0 0x1000>,
0660 <0 0x112b3e00 0 0x0100>;
0661 reg-names = "mac", "ippc";
0662 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
0663 phys = <&u2port3 PHY_TYPE_USB2>;
0664 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
0665 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
0666 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
0667 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
0668 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
0669 <&topckgen CLK_TOP_SSUSB_P3_REF>,
0670 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
0671 clock-names = "sys_ck", "ref_ck", "xhci_ck";
0672 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
0673 wakeup-source;
0674 status = "disabled";
0675 };
0676
0677 nor_flash: spi@1132c000 {
0678 compatible = "mediatek,mt8195-nor",
0679 "mediatek,mt8173-nor";
0680 reg = <0 0x1132c000 0 0x1000>;
0681 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
0682 clocks = <&topckgen CLK_TOP_SPINOR>,
0683 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
0684 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
0685 clock-names = "spi", "sf", "axi";
0686 #address-cells = <1>;
0687 #size-cells = <0>;
0688 status = "disabled";
0689 };
0690
0691 efuse: efuse@11c10000 {
0692 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
0693 reg = <0 0x11c10000 0 0x1000>;
0694 #address-cells = <1>;
0695 #size-cells = <1>;
0696 u3_tx_imp_p0: usb3-tx-imp@184,1 {
0697 reg = <0x184 0x1>;
0698 bits = <0 5>;
0699 };
0700 u3_rx_imp_p0: usb3-rx-imp@184,2 {
0701 reg = <0x184 0x2>;
0702 bits = <5 5>;
0703 };
0704 u3_intr_p0: usb3-intr@185 {
0705 reg = <0x185 0x1>;
0706 bits = <2 6>;
0707 };
0708 comb_tx_imp_p1: usb3-tx-imp@186,1 {
0709 reg = <0x186 0x1>;
0710 bits = <0 5>;
0711 };
0712 comb_rx_imp_p1: usb3-rx-imp@186,2 {
0713 reg = <0x186 0x2>;
0714 bits = <5 5>;
0715 };
0716 comb_intr_p1: usb3-intr@187 {
0717 reg = <0x187 0x1>;
0718 bits = <2 6>;
0719 };
0720 u2_intr_p0: usb2-intr-p0@188,1 {
0721 reg = <0x188 0x1>;
0722 bits = <0 5>;
0723 };
0724 u2_intr_p1: usb2-intr-p1@188,2 {
0725 reg = <0x188 0x2>;
0726 bits = <5 5>;
0727 };
0728 u2_intr_p2: usb2-intr-p2@189,1 {
0729 reg = <0x189 0x1>;
0730 bits = <2 5>;
0731 };
0732 u2_intr_p3: usb2-intr-p3@189,2 {
0733 reg = <0x189 0x2>;
0734 bits = <7 5>;
0735 };
0736 };
0737
0738 u3phy2: t-phy@11c40000 {
0739 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
0740 #address-cells = <1>;
0741 #size-cells = <1>;
0742 ranges = <0 0 0x11c40000 0x700>;
0743 status = "disabled";
0744
0745 u2port2: usb-phy@0 {
0746 reg = <0x0 0x700>;
0747 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
0748 clock-names = "ref";
0749 #phy-cells = <1>;
0750 };
0751 };
0752
0753 u3phy3: t-phy@11c50000 {
0754 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
0755 #address-cells = <1>;
0756 #size-cells = <1>;
0757 ranges = <0 0 0x11c50000 0x700>;
0758 status = "disabled";
0759
0760 u2port3: usb-phy@0 {
0761 reg = <0x0 0x700>;
0762 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
0763 clock-names = "ref";
0764 #phy-cells = <1>;
0765 };
0766 };
0767
0768 i2c5: i2c@11d00000 {
0769 compatible = "mediatek,mt8195-i2c",
0770 "mediatek,mt8192-i2c";
0771 reg = <0 0x11d00000 0 0x1000>,
0772 <0 0x10220580 0 0x80>;
0773 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
0774 clock-div = <1>;
0775 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
0776 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0777 clock-names = "main", "dma";
0778 #address-cells = <1>;
0779 #size-cells = <0>;
0780 status = "disabled";
0781 };
0782
0783 i2c6: i2c@11d01000 {
0784 compatible = "mediatek,mt8195-i2c",
0785 "mediatek,mt8192-i2c";
0786 reg = <0 0x11d01000 0 0x1000>,
0787 <0 0x10220600 0 0x80>;
0788 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
0789 clock-div = <1>;
0790 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
0791 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0792 clock-names = "main", "dma";
0793 #address-cells = <1>;
0794 #size-cells = <0>;
0795 status = "disabled";
0796 };
0797
0798 i2c7: i2c@11d02000 {
0799 compatible = "mediatek,mt8195-i2c",
0800 "mediatek,mt8192-i2c";
0801 reg = <0 0x11d02000 0 0x1000>,
0802 <0 0x10220680 0 0x80>;
0803 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
0804 clock-div = <1>;
0805 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
0806 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0807 clock-names = "main", "dma";
0808 #address-cells = <1>;
0809 #size-cells = <0>;
0810 status = "disabled";
0811 };
0812
0813 imp_iic_wrap_s: clock-controller@11d03000 {
0814 compatible = "mediatek,mt8195-imp_iic_wrap_s";
0815 reg = <0 0x11d03000 0 0x1000>;
0816 #clock-cells = <1>;
0817 };
0818
0819 i2c0: i2c@11e00000 {
0820 compatible = "mediatek,mt8195-i2c",
0821 "mediatek,mt8192-i2c";
0822 reg = <0 0x11e00000 0 0x1000>,
0823 <0 0x10220080 0 0x80>;
0824 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
0825 clock-div = <1>;
0826 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
0827 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0828 clock-names = "main", "dma";
0829 #address-cells = <1>;
0830 #size-cells = <0>;
0831 status = "okay";
0832 };
0833
0834 i2c1: i2c@11e01000 {
0835 compatible = "mediatek,mt8195-i2c",
0836 "mediatek,mt8192-i2c";
0837 reg = <0 0x11e01000 0 0x1000>,
0838 <0 0x10220200 0 0x80>;
0839 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
0840 clock-div = <1>;
0841 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
0842 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0843 clock-names = "main", "dma";
0844 #address-cells = <1>;
0845 #size-cells = <0>;
0846 status = "disabled";
0847 };
0848
0849 i2c2: i2c@11e02000 {
0850 compatible = "mediatek,mt8195-i2c",
0851 "mediatek,mt8192-i2c";
0852 reg = <0 0x11e02000 0 0x1000>,
0853 <0 0x10220380 0 0x80>;
0854 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
0855 clock-div = <1>;
0856 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
0857 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0858 clock-names = "main", "dma";
0859 #address-cells = <1>;
0860 #size-cells = <0>;
0861 status = "disabled";
0862 };
0863
0864 i2c3: i2c@11e03000 {
0865 compatible = "mediatek,mt8195-i2c",
0866 "mediatek,mt8192-i2c";
0867 reg = <0 0x11e03000 0 0x1000>,
0868 <0 0x10220480 0 0x80>;
0869 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
0870 clock-div = <1>;
0871 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
0872 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0873 clock-names = "main", "dma";
0874 #address-cells = <1>;
0875 #size-cells = <0>;
0876 status = "disabled";
0877 };
0878
0879 i2c4: i2c@11e04000 {
0880 compatible = "mediatek,mt8195-i2c",
0881 "mediatek,mt8192-i2c";
0882 reg = <0 0x11e04000 0 0x1000>,
0883 <0 0x10220500 0 0x80>;
0884 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
0885 clock-div = <1>;
0886 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
0887 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
0888 clock-names = "main", "dma";
0889 #address-cells = <1>;
0890 #size-cells = <0>;
0891 status = "disabled";
0892 };
0893
0894 imp_iic_wrap_w: clock-controller@11e05000 {
0895 compatible = "mediatek,mt8195-imp_iic_wrap_w";
0896 reg = <0 0x11e05000 0 0x1000>;
0897 #clock-cells = <1>;
0898 };
0899
0900 u3phy1: t-phy@11e30000 {
0901 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
0902 #address-cells = <1>;
0903 #size-cells = <1>;
0904 ranges = <0 0 0x11e30000 0xe00>;
0905 status = "disabled";
0906
0907 u2port1: usb-phy@0 {
0908 reg = <0x0 0x700>;
0909 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
0910 <&clk26m>;
0911 clock-names = "ref", "da_ref";
0912 #phy-cells = <1>;
0913 };
0914
0915 u3port1: usb-phy@700 {
0916 reg = <0x700 0x700>;
0917 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
0918 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
0919 clock-names = "ref", "da_ref";
0920 nvmem-cells = <&comb_intr_p1>,
0921 <&comb_rx_imp_p1>,
0922 <&comb_tx_imp_p1>;
0923 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
0924 #phy-cells = <1>;
0925 };
0926 };
0927
0928 u3phy0: t-phy@11e40000 {
0929 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
0930 #address-cells = <1>;
0931 #size-cells = <1>;
0932 ranges = <0 0 0x11e40000 0xe00>;
0933 status = "disabled";
0934
0935 u2port0: usb-phy@0 {
0936 reg = <0x0 0x700>;
0937 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
0938 <&clk26m>;
0939 clock-names = "ref", "da_ref";
0940 #phy-cells = <1>;
0941 };
0942
0943 u3port0: usb-phy@700 {
0944 reg = <0x700 0x700>;
0945 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
0946 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
0947 clock-names = "ref", "da_ref";
0948 nvmem-cells = <&u3_intr_p0>,
0949 <&u3_rx_imp_p0>,
0950 <&u3_tx_imp_p0>;
0951 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
0952 #phy-cells = <1>;
0953 };
0954 };
0955
0956 ufsphy: ufs-phy@11fa0000 {
0957 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
0958 reg = <0 0x11fa0000 0 0xc000>;
0959 clocks = <&clk26m>, <&clk26m>;
0960 clock-names = "unipro", "mp";
0961 #phy-cells = <0>;
0962 status = "disabled";
0963 };
0964
0965 mfgcfg: clock-controller@13fbf000 {
0966 compatible = "mediatek,mt8195-mfgcfg";
0967 reg = <0 0x13fbf000 0 0x1000>;
0968 #clock-cells = <1>;
0969 };
0970
0971 wpesys: clock-controller@14e00000 {
0972 compatible = "mediatek,mt8195-wpesys";
0973 reg = <0 0x14e00000 0 0x1000>;
0974 #clock-cells = <1>;
0975 };
0976
0977 wpesys_vpp0: clock-controller@14e02000 {
0978 compatible = "mediatek,mt8195-wpesys_vpp0";
0979 reg = <0 0x14e02000 0 0x1000>;
0980 #clock-cells = <1>;
0981 };
0982
0983 wpesys_vpp1: clock-controller@14e03000 {
0984 compatible = "mediatek,mt8195-wpesys_vpp1";
0985 reg = <0 0x14e03000 0 0x1000>;
0986 #clock-cells = <1>;
0987 };
0988
0989 imgsys: clock-controller@15000000 {
0990 compatible = "mediatek,mt8195-imgsys";
0991 reg = <0 0x15000000 0 0x1000>;
0992 #clock-cells = <1>;
0993 };
0994
0995 imgsys1_dip_top: clock-controller@15110000 {
0996 compatible = "mediatek,mt8195-imgsys1_dip_top";
0997 reg = <0 0x15110000 0 0x1000>;
0998 #clock-cells = <1>;
0999 };
1000
1001 imgsys1_dip_nr: clock-controller@15130000 {
1002 compatible = "mediatek,mt8195-imgsys1_dip_nr";
1003 reg = <0 0x15130000 0 0x1000>;
1004 #clock-cells = <1>;
1005 };
1006
1007 imgsys1_wpe: clock-controller@15220000 {
1008 compatible = "mediatek,mt8195-imgsys1_wpe";
1009 reg = <0 0x15220000 0 0x1000>;
1010 #clock-cells = <1>;
1011 };
1012
1013 ipesys: clock-controller@15330000 {
1014 compatible = "mediatek,mt8195-ipesys";
1015 reg = <0 0x15330000 0 0x1000>;
1016 #clock-cells = <1>;
1017 };
1018
1019 camsys: clock-controller@16000000 {
1020 compatible = "mediatek,mt8195-camsys";
1021 reg = <0 0x16000000 0 0x1000>;
1022 #clock-cells = <1>;
1023 };
1024
1025 camsys_rawa: clock-controller@1604f000 {
1026 compatible = "mediatek,mt8195-camsys_rawa";
1027 reg = <0 0x1604f000 0 0x1000>;
1028 #clock-cells = <1>;
1029 };
1030
1031 camsys_yuva: clock-controller@1606f000 {
1032 compatible = "mediatek,mt8195-camsys_yuva";
1033 reg = <0 0x1606f000 0 0x1000>;
1034 #clock-cells = <1>;
1035 };
1036
1037 camsys_rawb: clock-controller@1608f000 {
1038 compatible = "mediatek,mt8195-camsys_rawb";
1039 reg = <0 0x1608f000 0 0x1000>;
1040 #clock-cells = <1>;
1041 };
1042
1043 camsys_yuvb: clock-controller@160af000 {
1044 compatible = "mediatek,mt8195-camsys_yuvb";
1045 reg = <0 0x160af000 0 0x1000>;
1046 #clock-cells = <1>;
1047 };
1048
1049 camsys_mraw: clock-controller@16140000 {
1050 compatible = "mediatek,mt8195-camsys_mraw";
1051 reg = <0 0x16140000 0 0x1000>;
1052 #clock-cells = <1>;
1053 };
1054
1055 ccusys: clock-controller@17200000 {
1056 compatible = "mediatek,mt8195-ccusys";
1057 reg = <0 0x17200000 0 0x1000>;
1058 #clock-cells = <1>;
1059 };
1060
1061 vdecsys_soc: clock-controller@1800f000 {
1062 compatible = "mediatek,mt8195-vdecsys_soc";
1063 reg = <0 0x1800f000 0 0x1000>;
1064 #clock-cells = <1>;
1065 };
1066
1067 vdecsys: clock-controller@1802f000 {
1068 compatible = "mediatek,mt8195-vdecsys";
1069 reg = <0 0x1802f000 0 0x1000>;
1070 #clock-cells = <1>;
1071 };
1072
1073 vdecsys_core1: clock-controller@1803f000 {
1074 compatible = "mediatek,mt8195-vdecsys_core1";
1075 reg = <0 0x1803f000 0 0x1000>;
1076 #clock-cells = <1>;
1077 };
1078
1079 apusys_pll: clock-controller@190f3000 {
1080 compatible = "mediatek,mt8195-apusys_pll";
1081 reg = <0 0x190f3000 0 0x1000>;
1082 #clock-cells = <1>;
1083 };
1084
1085 vencsys: clock-controller@1a000000 {
1086 compatible = "mediatek,mt8195-vencsys";
1087 reg = <0 0x1a000000 0 0x1000>;
1088 #clock-cells = <1>;
1089 };
1090
1091 vencsys_core1: clock-controller@1b000000 {
1092 compatible = "mediatek,mt8195-vencsys_core1";
1093 reg = <0 0x1b000000 0 0x1000>;
1094 #clock-cells = <1>;
1095 };
1096 };
1097 };
