0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2022 BayLibre, SAS.
0004 * Author: Fabien Parent <fparent@baylibre.com>
0005 */
0006 /dts-v1/;
0007
0008 #include "mt8195.dtsi"
0009 #include "mt6359.dtsi"
0010
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/input/input.h>
0013 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
0014 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
0015
0016 / {
0017 model = "MediaTek MT8195 demo board";
0018 compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
0019
0020 aliases {
0021 serial0 = &uart0;
0022 };
0023
0024 chosen {
0025 stdout-path = "serial0:921600n8";
0026 };
0027
0028 firmware {
0029 optee {
0030 compatible = "linaro,optee-tz";
0031 method = "smc";
0032 };
0033 };
0034
0035 gpio-keys {
0036 compatible = "gpio-keys";
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&gpio_keys_pins>;
0039
0040 key-0 {
0041 gpios = <&pio 106 GPIO_ACTIVE_LOW>;
0042 label = "volume_up";
0043 linux,code = <KEY_VOLUMEUP>;
0044 wakeup-source;
0045 debounce-interval = <15>;
0046 };
0047 };
0048
0049 memory@40000000 {
0050 device_type = "memory";
0051 reg = <0 0x40000000 0 0x80000000>;
0052 };
0053
0054 reserved-memory {
0055 #address-cells = <2>;
0056 #size-cells = <2>;
0057 ranges;
0058
0059 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
0060 bl31_secmon_reserved: secmon@54600000 {
0061 no-map;
0062 reg = <0 0x54600000 0x0 0x30000>;
0063 };
0064
0065 /* 12 MiB reserved for OP-TEE (BL32)
0066 * +-----------------------+ 0x43e0_0000
0067 * | SHMEM 2MiB |
0068 * +-----------------------+ 0x43c0_0000
0069 * | | TA_RAM 8MiB |
0070 * + TZDRAM +--------------+ 0x4340_0000
0071 * | | TEE_RAM 2MiB |
0072 * +-----------------------+ 0x4320_0000
0073 */
0074 optee_reserved: optee@43200000 {
0075 no-map;
0076 reg = <0 0x43200000 0 0x00c00000>;
0077 };
0078 };
0079 };
0080
0081 &i2c6 {
0082 clock-frequency = <400000>;
0083 pinctrl-0 = <&i2c6_pins>;
0084 pinctrl-names = "default";
0085 status = "okay";
0086
0087 mt6360: pmic@34 {
0088 compatible = "mediatek,mt6360";
0089 reg = <0x34>;
0090 interrupt-controller;
0091 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
0092 interrupt-names = "IRQB";
0093
0094 charger {
0095 compatible = "mediatek,mt6360-chg";
0096 richtek,vinovp-microvolt = <14500000>;
0097
0098 otg_vbus_regulator: usb-otg-vbus-regulator {
0099 regulator-compatible = "usb-otg-vbus";
0100 regulator-name = "usb-otg-vbus";
0101 regulator-min-microvolt = <4425000>;
0102 regulator-max-microvolt = <5825000>;
0103 };
0104 };
0105
0106 regulator {
0107 compatible = "mediatek,mt6360-regulator";
0108 LDO_VIN3-supply = <&mt6360_buck2>;
0109
0110 mt6360_buck1: buck1 {
0111 regulator-compatible = "BUCK1";
0112 regulator-name = "mt6360,buck1";
0113 regulator-min-microvolt = <300000>;
0114 regulator-max-microvolt = <1300000>;
0115 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0116 MT6360_OPMODE_LP
0117 MT6360_OPMODE_ULP>;
0118 regulator-always-on;
0119 };
0120
0121 mt6360_buck2: buck2 {
0122 regulator-compatible = "BUCK2";
0123 regulator-name = "mt6360,buck2";
0124 regulator-min-microvolt = <300000>;
0125 regulator-max-microvolt = <1300000>;
0126 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0127 MT6360_OPMODE_LP
0128 MT6360_OPMODE_ULP>;
0129 regulator-always-on;
0130 };
0131
0132 mt6360_ldo1: ldo1 {
0133 regulator-compatible = "LDO1";
0134 regulator-name = "mt6360,ldo1";
0135 regulator-min-microvolt = <1200000>;
0136 regulator-max-microvolt = <3600000>;
0137 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0138 MT6360_OPMODE_LP>;
0139 };
0140
0141 mt6360_ldo2: ldo2 {
0142 regulator-compatible = "LDO2";
0143 regulator-name = "mt6360,ldo2";
0144 regulator-min-microvolt = <1200000>;
0145 regulator-max-microvolt = <3600000>;
0146 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0147 MT6360_OPMODE_LP>;
0148 };
0149
0150 mt6360_ldo3: ldo3 {
0151 regulator-compatible = "LDO3";
0152 regulator-name = "mt6360,ldo3";
0153 regulator-min-microvolt = <1200000>;
0154 regulator-max-microvolt = <3600000>;
0155 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0156 MT6360_OPMODE_LP>;
0157 };
0158
0159 mt6360_ldo5: ldo5 {
0160 regulator-compatible = "LDO5";
0161 regulator-name = "mt6360,ldo5";
0162 regulator-min-microvolt = <2700000>;
0163 regulator-max-microvolt = <3600000>;
0164 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0165 MT6360_OPMODE_LP>;
0166 };
0167
0168 mt6360_ldo6: ldo6 {
0169 regulator-compatible = "LDO6";
0170 regulator-name = "mt6360,ldo6";
0171 regulator-min-microvolt = <500000>;
0172 regulator-max-microvolt = <2100000>;
0173 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0174 MT6360_OPMODE_LP>;
0175 };
0176
0177 mt6360_ldo7: ldo7 {
0178 regulator-compatible = "LDO7";
0179 regulator-name = "mt6360,ldo7";
0180 regulator-min-microvolt = <500000>;
0181 regulator-max-microvolt = <2100000>;
0182 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
0183 MT6360_OPMODE_LP>;
0184 regulator-always-on;
0185 };
0186 };
0187 };
0188 };
0189
0190 &mmc0 {
0191 status = "okay";
0192 pinctrl-names = "default", "state_uhs";
0193 pinctrl-0 = <&mmc0_default_pins>;
0194 pinctrl-1 = <&mmc0_uhs_pins>;
0195 bus-width = <8>;
0196 max-frequency = <200000000>;
0197 cap-mmc-highspeed;
0198 mmc-hs200-1_8v;
0199 mmc-hs400-1_8v;
0200 cap-mmc-hw-reset;
0201 no-sdio;
0202 no-sd;
0203 hs400-ds-delay = <0x14c11>;
0204 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
0205 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
0206 non-removable;
0207 };
0208
0209 &mmc1 {
0210 pinctrl-names = "default", "state_uhs";
0211 pinctrl-0 = <&mmc1_default_pins>;
0212 pinctrl-1 = <&mmc1_uhs_pins>;
0213 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
0214 bus-width = <4>;
0215 max-frequency = <200000000>;
0216 cap-sd-highspeed;
0217 sd-uhs-sdr50;
0218 sd-uhs-sdr104;
0219 vmmc-supply = <&mt6360_ldo5>;
0220 vqmmc-supply = <&mt6360_ldo3>;
0221 status = "okay";
0222 };
0223
0224 &mt6359_vbbck_ldo_reg {
0225 regulator-always-on;
0226 };
0227
0228 &mt6359_vcore_buck_reg {
0229 regulator-always-on;
0230 };
0231
0232 &mt6359_vgpu11_buck_reg {
0233 regulator-always-on;
0234 };
0235
0236 &mt6359_vproc1_buck_reg {
0237 regulator-always-on;
0238 };
0239
0240 &mt6359_vproc2_buck_reg {
0241 regulator-always-on;
0242 };
0243
0244 &mt6359_vpu_buck_reg {
0245 regulator-always-on;
0246 };
0247
0248 &mt6359_vrf12_ldo_reg {
0249 regulator-always-on;
0250 };
0251
0252 &mt6359_vsram_md_ldo_reg {
0253 regulator-always-on;
0254 };
0255
0256 &mt6359_vsram_others_ldo_reg {
0257 regulator-always-on;
0258 };
0259
0260 &pio {
0261 gpio_keys_pins: gpio-keys-pins {
0262 pins {
0263 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
0264 input-enable;
0265 };
0266 };
0267
0268 i2c6_pins: i2c6-pins {
0269 pins {
0270 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
0271 <PINMUX_GPIO26__FUNC_SCL6>;
0272 bias-pull-up;
0273 };
0274 };
0275
0276 mmc0_default_pins: mmc0-default-pins {
0277 pins-clk {
0278 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
0279 drive-strength = <MTK_DRIVE_6mA>;
0280 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0281 };
0282
0283 pins-cmd-dat {
0284 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
0285 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
0286 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
0287 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
0288 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
0289 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
0290 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
0291 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
0292 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
0293 input-enable;
0294 drive-strength = <MTK_DRIVE_6mA>;
0295 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0296 };
0297
0298 pins-rst {
0299 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
0300 drive-strength = <MTK_DRIVE_6mA>;
0301 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0302 };
0303 };
0304
0305 mmc0_uhs_pins: mmc0-uhs-pins {
0306 pins-clk {
0307 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
0308 drive-strength = <MTK_DRIVE_8mA>;
0309 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0310 };
0311
0312 pins-cmd-dat {
0313 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
0314 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
0315 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
0316 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
0317 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
0318 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
0319 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
0320 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
0321 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
0322 input-enable;
0323 drive-strength = <MTK_DRIVE_8mA>;
0324 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0325 };
0326
0327 pins-ds {
0328 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
0329 drive-strength = <MTK_DRIVE_8mA>;
0330 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0331 };
0332
0333 pins-rst {
0334 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
0335 drive-strength = <MTK_DRIVE_8mA>;
0336 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0337 };
0338 };
0339
0340 mmc1_default_pins: mmc1-default-pins {
0341 pins-clk {
0342 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
0343 drive-strength = <MTK_DRIVE_8mA>;
0344 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0345 };
0346
0347 pins-cmd-dat {
0348 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
0349 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
0350 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
0351 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
0352 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
0353 input-enable;
0354 drive-strength = <MTK_DRIVE_8mA>;
0355 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0356 };
0357
0358 pins-insert {
0359 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
0360 bias-pull-up;
0361 };
0362 };
0363
0364 mmc1_uhs_pins: mmc1-uhs-pins {
0365 pins-clk {
0366 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
0367 drive-strength = <MTK_DRIVE_8mA>;
0368 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0369 };
0370
0371 pins-cmd-dat {
0372 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
0373 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
0374 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
0375 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
0376 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
0377 input-enable;
0378 drive-strength = <MTK_DRIVE_8mA>;
0379 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0380 };
0381 };
0382
0383 uart0_pins: uart0-pins {
0384 pins {
0385 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
0386 <PINMUX_GPIO99__FUNC_URXD0>;
0387 };
0388 };
0389
0390 uart1_pins: uart1-pins {
0391 pins {
0392 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
0393 <PINMUX_GPIO103__FUNC_URXD1>;
0394 };
0395 };
0396 };
0397
0398
0399 &pmic {
0400 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
0401 };
0402
0403 &uart0 {
0404 pinctrl-names = "default";
0405 pinctrl-0 = <&uart0_pins>;
0406 status = "okay";
0407 };
0408
0409 &uart1 {
0410 pinctrl-names = "default";
0411 pinctrl-0 = <&uart1_pins>;
0412 status = "okay";
0413 };
0414
0415 &u3phy0 {
0416 status = "okay";
0417 };
0418
0419 &u3phy1 {
0420 status = "okay";
0421 };
0422
0423 &u3phy2 {
0424 status = "okay";
0425 };
0426
0427 &u3phy3 {
0428 status = "okay";
0429 };
0430
0431 &xhci0 {
0432 vusb33-supply = <&mt6359_vusb_ldo_reg>;
0433 vbus-supply = <&otg_vbus_regulator>;
0434 status = "okay";
0435 };
0436
0437 &xhci1 {
0438 vusb33-supply = <&mt6359_vusb_ldo_reg>;
0439 status = "okay";
0440 };
0441
0442 &xhci2 {
0443 vusb33-supply = <&mt6359_vusb_ldo_reg>;
0444 status = "okay";
0445 };
0446
0447 &xhci3 {
0448 vusb33-supply = <&mt6359_vusb_ldo_reg>;
0449 status = "okay";
0450 };
