0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2020 MediaTek Inc.
0004 * Author: Seiya Wang <seiya.wang@mediatek.com>
0005 */
0006
0007 /dts-v1/;
0008 #include <dt-bindings/clock/mt8192-clk.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/memory/mt8192-larb-port.h>
0012 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
0013 #include <dt-bindings/phy/phy.h>
0014 #include <dt-bindings/power/mt8192-power.h>
0015
0016 / {
0017 compatible = "mediatek,mt8192";
0018 interrupt-parent = <&gic>;
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 clk26m: oscillator0 {
0023 compatible = "fixed-clock";
0024 #clock-cells = <0>;
0025 clock-frequency = <26000000>;
0026 clock-output-names = "clk26m";
0027 };
0028
0029 clk32k: oscillator1 {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 clock-frequency = <32768>;
0033 clock-output-names = "clk32k";
0034 };
0035
0036 cpus {
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039
0040 cpu0: cpu@0 {
0041 device_type = "cpu";
0042 compatible = "arm,cortex-a55";
0043 reg = <0x000>;
0044 enable-method = "psci";
0045 clock-frequency = <1701000000>;
0046 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
0047 next-level-cache = <&l2_0>;
0048 capacity-dmips-mhz = <530>;
0049 };
0050
0051 cpu1: cpu@100 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a55";
0054 reg = <0x100>;
0055 enable-method = "psci";
0056 clock-frequency = <1701000000>;
0057 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
0058 next-level-cache = <&l2_0>;
0059 capacity-dmips-mhz = <530>;
0060 };
0061
0062 cpu2: cpu@200 {
0063 device_type = "cpu";
0064 compatible = "arm,cortex-a55";
0065 reg = <0x200>;
0066 enable-method = "psci";
0067 clock-frequency = <1701000000>;
0068 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
0069 next-level-cache = <&l2_0>;
0070 capacity-dmips-mhz = <530>;
0071 };
0072
0073 cpu3: cpu@300 {
0074 device_type = "cpu";
0075 compatible = "arm,cortex-a55";
0076 reg = <0x300>;
0077 enable-method = "psci";
0078 clock-frequency = <1701000000>;
0079 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
0080 next-level-cache = <&l2_0>;
0081 capacity-dmips-mhz = <530>;
0082 };
0083
0084 cpu4: cpu@400 {
0085 device_type = "cpu";
0086 compatible = "arm,cortex-a76";
0087 reg = <0x400>;
0088 enable-method = "psci";
0089 clock-frequency = <2171000000>;
0090 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
0091 next-level-cache = <&l2_1>;
0092 capacity-dmips-mhz = <1024>;
0093 };
0094
0095 cpu5: cpu@500 {
0096 device_type = "cpu";
0097 compatible = "arm,cortex-a76";
0098 reg = <0x500>;
0099 enable-method = "psci";
0100 clock-frequency = <2171000000>;
0101 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
0102 next-level-cache = <&l2_1>;
0103 capacity-dmips-mhz = <1024>;
0104 };
0105
0106 cpu6: cpu@600 {
0107 device_type = "cpu";
0108 compatible = "arm,cortex-a76";
0109 reg = <0x600>;
0110 enable-method = "psci";
0111 clock-frequency = <2171000000>;
0112 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
0113 next-level-cache = <&l2_1>;
0114 capacity-dmips-mhz = <1024>;
0115 };
0116
0117 cpu7: cpu@700 {
0118 device_type = "cpu";
0119 compatible = "arm,cortex-a76";
0120 reg = <0x700>;
0121 enable-method = "psci";
0122 clock-frequency = <2171000000>;
0123 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
0124 next-level-cache = <&l2_1>;
0125 capacity-dmips-mhz = <1024>;
0126 };
0127
0128 cpu-map {
0129 cluster0 {
0130 core0 {
0131 cpu = <&cpu0>;
0132 };
0133 core1 {
0134 cpu = <&cpu1>;
0135 };
0136 core2 {
0137 cpu = <&cpu2>;
0138 };
0139 core3 {
0140 cpu = <&cpu3>;
0141 };
0142 };
0143
0144 cluster1 {
0145 core0 {
0146 cpu = <&cpu4>;
0147 };
0148 core1 {
0149 cpu = <&cpu5>;
0150 };
0151 core2 {
0152 cpu = <&cpu6>;
0153 };
0154 core3 {
0155 cpu = <&cpu7>;
0156 };
0157 };
0158 };
0159
0160 l2_0: l2-cache0 {
0161 compatible = "cache";
0162 next-level-cache = <&l3_0>;
0163 };
0164
0165 l2_1: l2-cache1 {
0166 compatible = "cache";
0167 next-level-cache = <&l3_0>;
0168 };
0169
0170 l3_0: l3-cache {
0171 compatible = "cache";
0172 };
0173
0174 idle-states {
0175 entry-method = "psci";
0176 cpu_sleep_l: cpu-sleep-l {
0177 compatible = "arm,idle-state";
0178 arm,psci-suspend-param = <0x00010001>;
0179 local-timer-stop;
0180 entry-latency-us = <55>;
0181 exit-latency-us = <140>;
0182 min-residency-us = <780>;
0183 };
0184 cpu_sleep_b: cpu-sleep-b {
0185 compatible = "arm,idle-state";
0186 arm,psci-suspend-param = <0x00010001>;
0187 local-timer-stop;
0188 entry-latency-us = <35>;
0189 exit-latency-us = <145>;
0190 min-residency-us = <720>;
0191 };
0192 cluster_sleep_l: cluster-sleep-l {
0193 compatible = "arm,idle-state";
0194 arm,psci-suspend-param = <0x01010002>;
0195 local-timer-stop;
0196 entry-latency-us = <60>;
0197 exit-latency-us = <155>;
0198 min-residency-us = <860>;
0199 };
0200 cluster_sleep_b: cluster-sleep-b {
0201 compatible = "arm,idle-state";
0202 arm,psci-suspend-param = <0x01010002>;
0203 local-timer-stop;
0204 entry-latency-us = <40>;
0205 exit-latency-us = <155>;
0206 min-residency-us = <780>;
0207 };
0208 };
0209 };
0210
0211 pmu-a55 {
0212 compatible = "arm,cortex-a55-pmu";
0213 interrupt-parent = <&gic>;
0214 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
0215 };
0216
0217 pmu-a76 {
0218 compatible = "arm,cortex-a76-pmu";
0219 interrupt-parent = <&gic>;
0220 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
0221 };
0222
0223 psci {
0224 compatible = "arm,psci-1.0";
0225 method = "smc";
0226 };
0227
0228 timer: timer {
0229 compatible = "arm,armv8-timer";
0230 interrupt-parent = <&gic>;
0231 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
0232 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
0233 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
0234 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
0235 clock-frequency = <13000000>;
0236 };
0237
0238 soc {
0239 #address-cells = <2>;
0240 #size-cells = <2>;
0241 compatible = "simple-bus";
0242 ranges;
0243
0244 gic: interrupt-controller@c000000 {
0245 compatible = "arm,gic-v3";
0246 #interrupt-cells = <4>;
0247 #redistributor-regions = <1>;
0248 interrupt-parent = <&gic>;
0249 interrupt-controller;
0250 reg = <0 0x0c000000 0 0x40000>,
0251 <0 0x0c040000 0 0x200000>;
0252 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
0253
0254 ppi-partitions {
0255 ppi_cluster0: interrupt-partition-0 {
0256 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
0257 };
0258 ppi_cluster1: interrupt-partition-1 {
0259 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
0260 };
0261 };
0262 };
0263
0264 topckgen: syscon@10000000 {
0265 compatible = "mediatek,mt8192-topckgen", "syscon";
0266 reg = <0 0x10000000 0 0x1000>;
0267 #clock-cells = <1>;
0268 };
0269
0270 infracfg: syscon@10001000 {
0271 compatible = "mediatek,mt8192-infracfg", "syscon";
0272 reg = <0 0x10001000 0 0x1000>;
0273 #clock-cells = <1>;
0274 #reset-cells = <1>;
0275 };
0276
0277 pericfg: syscon@10003000 {
0278 compatible = "mediatek,mt8192-pericfg", "syscon";
0279 reg = <0 0x10003000 0 0x1000>;
0280 #clock-cells = <1>;
0281 };
0282
0283 pio: pinctrl@10005000 {
0284 compatible = "mediatek,mt8192-pinctrl";
0285 reg = <0 0x10005000 0 0x1000>,
0286 <0 0x11c20000 0 0x1000>,
0287 <0 0x11d10000 0 0x1000>,
0288 <0 0x11d30000 0 0x1000>,
0289 <0 0x11d40000 0 0x1000>,
0290 <0 0x11e20000 0 0x1000>,
0291 <0 0x11e70000 0 0x1000>,
0292 <0 0x11ea0000 0 0x1000>,
0293 <0 0x11f20000 0 0x1000>,
0294 <0 0x11f30000 0 0x1000>,
0295 <0 0x1000b000 0 0x1000>;
0296 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
0297 "iocfg_bl", "iocfg_br", "iocfg_lm",
0298 "iocfg_lb", "iocfg_rt", "iocfg_lt",
0299 "iocfg_tl", "eint";
0300 gpio-controller;
0301 #gpio-cells = <2>;
0302 gpio-ranges = <&pio 0 0 220>;
0303 interrupt-controller;
0304 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
0305 #interrupt-cells = <2>;
0306 };
0307
0308 scpsys: syscon@10006000 {
0309 compatible = "syscon", "simple-mfd";
0310 reg = <0 0x10006000 0 0x1000>;
0311 #power-domain-cells = <1>;
0312
0313 /* System Power Manager */
0314 spm: power-controller {
0315 compatible = "mediatek,mt8192-power-controller";
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318 #power-domain-cells = <1>;
0319
0320 /* power domain of the SoC */
0321 power-domain@MT8192_POWER_DOMAIN_AUDIO {
0322 reg = <MT8192_POWER_DOMAIN_AUDIO>;
0323 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
0324 <&infracfg CLK_INFRA_AUDIO_26M_B>,
0325 <&infracfg CLK_INFRA_AUDIO>;
0326 clock-names = "audio", "audio1", "audio2";
0327 mediatek,infracfg = <&infracfg>;
0328 #power-domain-cells = <0>;
0329 };
0330
0331 power-domain@MT8192_POWER_DOMAIN_CONN {
0332 reg = <MT8192_POWER_DOMAIN_CONN>;
0333 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
0334 clock-names = "conn";
0335 mediatek,infracfg = <&infracfg>;
0336 #power-domain-cells = <0>;
0337 };
0338
0339 power-domain@MT8192_POWER_DOMAIN_MFG0 {
0340 reg = <MT8192_POWER_DOMAIN_MFG0>;
0341 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
0342 clock-names = "mfg";
0343 #address-cells = <1>;
0344 #size-cells = <0>;
0345 #power-domain-cells = <1>;
0346
0347 power-domain@MT8192_POWER_DOMAIN_MFG1 {
0348 reg = <MT8192_POWER_DOMAIN_MFG1>;
0349 mediatek,infracfg = <&infracfg>;
0350 #address-cells = <1>;
0351 #size-cells = <0>;
0352 #power-domain-cells = <1>;
0353
0354 power-domain@MT8192_POWER_DOMAIN_MFG2 {
0355 reg = <MT8192_POWER_DOMAIN_MFG2>;
0356 #power-domain-cells = <0>;
0357 };
0358
0359 power-domain@MT8192_POWER_DOMAIN_MFG3 {
0360 reg = <MT8192_POWER_DOMAIN_MFG3>;
0361 #power-domain-cells = <0>;
0362 };
0363
0364 power-domain@MT8192_POWER_DOMAIN_MFG4 {
0365 reg = <MT8192_POWER_DOMAIN_MFG4>;
0366 #power-domain-cells = <0>;
0367 };
0368
0369 power-domain@MT8192_POWER_DOMAIN_MFG5 {
0370 reg = <MT8192_POWER_DOMAIN_MFG5>;
0371 #power-domain-cells = <0>;
0372 };
0373
0374 power-domain@MT8192_POWER_DOMAIN_MFG6 {
0375 reg = <MT8192_POWER_DOMAIN_MFG6>;
0376 #power-domain-cells = <0>;
0377 };
0378 };
0379 };
0380
0381 power-domain@MT8192_POWER_DOMAIN_DISP {
0382 reg = <MT8192_POWER_DOMAIN_DISP>;
0383 clocks = <&topckgen CLK_TOP_DISP_SEL>,
0384 <&mmsys CLK_MM_SMI_INFRA>,
0385 <&mmsys CLK_MM_SMI_COMMON>,
0386 <&mmsys CLK_MM_SMI_GALS>,
0387 <&mmsys CLK_MM_SMI_IOMMU>;
0388 clock-names = "disp", "disp-0", "disp-1", "disp-2",
0389 "disp-3";
0390 mediatek,infracfg = <&infracfg>;
0391 #address-cells = <1>;
0392 #size-cells = <0>;
0393 #power-domain-cells = <1>;
0394
0395 power-domain@MT8192_POWER_DOMAIN_IPE {
0396 reg = <MT8192_POWER_DOMAIN_IPE>;
0397 clocks = <&topckgen CLK_TOP_IPE_SEL>,
0398 <&ipesys CLK_IPE_LARB19>,
0399 <&ipesys CLK_IPE_LARB20>,
0400 <&ipesys CLK_IPE_SMI_SUBCOM>,
0401 <&ipesys CLK_IPE_GALS>;
0402 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
0403 "ipe-3";
0404 mediatek,infracfg = <&infracfg>;
0405 #power-domain-cells = <0>;
0406 };
0407
0408 power-domain@MT8192_POWER_DOMAIN_ISP {
0409 reg = <MT8192_POWER_DOMAIN_ISP>;
0410 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
0411 <&imgsys CLK_IMG_LARB9>,
0412 <&imgsys CLK_IMG_GALS>;
0413 clock-names = "isp", "isp-0", "isp-1";
0414 mediatek,infracfg = <&infracfg>;
0415 #power-domain-cells = <0>;
0416 };
0417
0418 power-domain@MT8192_POWER_DOMAIN_ISP2 {
0419 reg = <MT8192_POWER_DOMAIN_ISP2>;
0420 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
0421 <&imgsys2 CLK_IMG2_LARB11>,
0422 <&imgsys2 CLK_IMG2_GALS>;
0423 clock-names = "isp2", "isp2-0", "isp2-1";
0424 mediatek,infracfg = <&infracfg>;
0425 #power-domain-cells = <0>;
0426 };
0427
0428 power-domain@MT8192_POWER_DOMAIN_MDP {
0429 reg = <MT8192_POWER_DOMAIN_MDP>;
0430 clocks = <&topckgen CLK_TOP_MDP_SEL>,
0431 <&mdpsys CLK_MDP_SMI0>;
0432 clock-names = "mdp", "mdp-0";
0433 mediatek,infracfg = <&infracfg>;
0434 #power-domain-cells = <0>;
0435 };
0436
0437 power-domain@MT8192_POWER_DOMAIN_VENC {
0438 reg = <MT8192_POWER_DOMAIN_VENC>;
0439 clocks = <&topckgen CLK_TOP_VENC_SEL>,
0440 <&vencsys CLK_VENC_SET1_VENC>;
0441 clock-names = "venc", "venc-0";
0442 mediatek,infracfg = <&infracfg>;
0443 #power-domain-cells = <0>;
0444 };
0445
0446 power-domain@MT8192_POWER_DOMAIN_VDEC {
0447 reg = <MT8192_POWER_DOMAIN_VDEC>;
0448 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
0449 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
0450 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
0451 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
0452 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
0453 mediatek,infracfg = <&infracfg>;
0454 #address-cells = <1>;
0455 #size-cells = <0>;
0456 #power-domain-cells = <1>;
0457
0458 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
0459 reg = <MT8192_POWER_DOMAIN_VDEC2>;
0460 clocks = <&vdecsys CLK_VDEC_VDEC>,
0461 <&vdecsys CLK_VDEC_LAT>,
0462 <&vdecsys CLK_VDEC_LARB1>;
0463 clock-names = "vdec2-0", "vdec2-1",
0464 "vdec2-2";
0465 #power-domain-cells = <0>;
0466 };
0467 };
0468
0469 power-domain@MT8192_POWER_DOMAIN_CAM {
0470 reg = <MT8192_POWER_DOMAIN_CAM>;
0471 clocks = <&topckgen CLK_TOP_CAM_SEL>,
0472 <&camsys CLK_CAM_LARB13>,
0473 <&camsys CLK_CAM_LARB14>,
0474 <&camsys CLK_CAM_CCU_GALS>,
0475 <&camsys CLK_CAM_CAM2MM_GALS>;
0476 clock-names = "cam", "cam-0", "cam-1", "cam-2",
0477 "cam-3";
0478 mediatek,infracfg = <&infracfg>;
0479 #address-cells = <1>;
0480 #size-cells = <0>;
0481 #power-domain-cells = <1>;
0482
0483 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
0484 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
0485 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
0486 clock-names = "cam_rawa-0";
0487 #power-domain-cells = <0>;
0488 };
0489
0490 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
0491 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
0492 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
0493 clock-names = "cam_rawb-0";
0494 #power-domain-cells = <0>;
0495 };
0496
0497 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
0498 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
0499 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
0500 clock-names = "cam_rawc-0";
0501 #power-domain-cells = <0>;
0502 };
0503 };
0504 };
0505 };
0506 };
0507
0508 watchdog: watchdog@10007000 {
0509 compatible = "mediatek,mt8192-wdt";
0510 reg = <0 0x10007000 0 0x100>;
0511 #reset-cells = <1>;
0512 };
0513
0514 apmixedsys: syscon@1000c000 {
0515 compatible = "mediatek,mt8192-apmixedsys", "syscon";
0516 reg = <0 0x1000c000 0 0x1000>;
0517 #clock-cells = <1>;
0518 };
0519
0520 systimer: timer@10017000 {
0521 compatible = "mediatek,mt8192-timer",
0522 "mediatek,mt6765-timer";
0523 reg = <0 0x10017000 0 0x1000>;
0524 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
0525 clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
0526 clock-names = "clk13m";
0527 };
0528
0529 pwrap: pwrap@10026000 {
0530 compatible = "mediatek,mt6873-pwrap";
0531 reg = <0 0x10026000 0 0x1000>;
0532 reg-names = "pwrap";
0533 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
0534 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
0535 <&infracfg CLK_INFRA_PMIC_TMR>;
0536 clock-names = "spi", "wrap";
0537 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
0538 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
0539 };
0540
0541 spmi: spmi@10027000 {
0542 compatible = "mediatek,mt6873-spmi";
0543 reg = <0 0x10027000 0 0x000e00>,
0544 <0 0x10029000 0 0x000100>;
0545 reg-names = "pmif", "spmimst";
0546 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
0547 <&infracfg CLK_INFRA_PMIC_TMR>,
0548 <&topckgen CLK_TOP_SPMI_MST_SEL>;
0549 clock-names = "pmif_sys_ck",
0550 "pmif_tmr_ck",
0551 "spmimst_clk_mux";
0552 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
0553 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
0554 };
0555
0556 scp_adsp: clock-controller@10720000 {
0557 compatible = "mediatek,mt8192-scp_adsp";
0558 reg = <0 0x10720000 0 0x1000>;
0559 #clock-cells = <1>;
0560 };
0561
0562 uart0: serial@11002000 {
0563 compatible = "mediatek,mt8192-uart",
0564 "mediatek,mt6577-uart";
0565 reg = <0 0x11002000 0 0x1000>;
0566 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
0567 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
0568 clock-names = "baud", "bus";
0569 status = "disabled";
0570 };
0571
0572 uart1: serial@11003000 {
0573 compatible = "mediatek,mt8192-uart",
0574 "mediatek,mt6577-uart";
0575 reg = <0 0x11003000 0 0x1000>;
0576 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
0577 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
0578 clock-names = "baud", "bus";
0579 status = "disabled";
0580 };
0581
0582 imp_iic_wrap_c: clock-controller@11007000 {
0583 compatible = "mediatek,mt8192-imp_iic_wrap_c";
0584 reg = <0 0x11007000 0 0x1000>;
0585 #clock-cells = <1>;
0586 };
0587
0588 spi0: spi@1100a000 {
0589 compatible = "mediatek,mt8192-spi",
0590 "mediatek,mt6765-spi";
0591 #address-cells = <1>;
0592 #size-cells = <0>;
0593 reg = <0 0x1100a000 0 0x1000>;
0594 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
0595 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0596 <&topckgen CLK_TOP_SPI_SEL>,
0597 <&infracfg CLK_INFRA_SPI0>;
0598 clock-names = "parent-clk", "sel-clk", "spi-clk";
0599 status = "disabled";
0600 };
0601
0602 spi1: spi@11010000 {
0603 compatible = "mediatek,mt8192-spi",
0604 "mediatek,mt6765-spi";
0605 #address-cells = <1>;
0606 #size-cells = <0>;
0607 reg = <0 0x11010000 0 0x1000>;
0608 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
0609 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0610 <&topckgen CLK_TOP_SPI_SEL>,
0611 <&infracfg CLK_INFRA_SPI1>;
0612 clock-names = "parent-clk", "sel-clk", "spi-clk";
0613 status = "disabled";
0614 };
0615
0616 spi2: spi@11012000 {
0617 compatible = "mediatek,mt8192-spi",
0618 "mediatek,mt6765-spi";
0619 #address-cells = <1>;
0620 #size-cells = <0>;
0621 reg = <0 0x11012000 0 0x1000>;
0622 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
0623 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0624 <&topckgen CLK_TOP_SPI_SEL>,
0625 <&infracfg CLK_INFRA_SPI2>;
0626 clock-names = "parent-clk", "sel-clk", "spi-clk";
0627 status = "disabled";
0628 };
0629
0630 spi3: spi@11013000 {
0631 compatible = "mediatek,mt8192-spi",
0632 "mediatek,mt6765-spi";
0633 #address-cells = <1>;
0634 #size-cells = <0>;
0635 reg = <0 0x11013000 0 0x1000>;
0636 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
0637 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0638 <&topckgen CLK_TOP_SPI_SEL>,
0639 <&infracfg CLK_INFRA_SPI3>;
0640 clock-names = "parent-clk", "sel-clk", "spi-clk";
0641 status = "disabled";
0642 };
0643
0644 spi4: spi@11018000 {
0645 compatible = "mediatek,mt8192-spi",
0646 "mediatek,mt6765-spi";
0647 #address-cells = <1>;
0648 #size-cells = <0>;
0649 reg = <0 0x11018000 0 0x1000>;
0650 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
0651 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0652 <&topckgen CLK_TOP_SPI_SEL>,
0653 <&infracfg CLK_INFRA_SPI4>;
0654 clock-names = "parent-clk", "sel-clk", "spi-clk";
0655 status = "disabled";
0656 };
0657
0658 spi5: spi@11019000 {
0659 compatible = "mediatek,mt8192-spi",
0660 "mediatek,mt6765-spi";
0661 #address-cells = <1>;
0662 #size-cells = <0>;
0663 reg = <0 0x11019000 0 0x1000>;
0664 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
0665 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0666 <&topckgen CLK_TOP_SPI_SEL>,
0667 <&infracfg CLK_INFRA_SPI5>;
0668 clock-names = "parent-clk", "sel-clk", "spi-clk";
0669 status = "disabled";
0670 };
0671
0672 spi6: spi@1101d000 {
0673 compatible = "mediatek,mt8192-spi",
0674 "mediatek,mt6765-spi";
0675 #address-cells = <1>;
0676 #size-cells = <0>;
0677 reg = <0 0x1101d000 0 0x1000>;
0678 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
0679 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0680 <&topckgen CLK_TOP_SPI_SEL>,
0681 <&infracfg CLK_INFRA_SPI6>;
0682 clock-names = "parent-clk", "sel-clk", "spi-clk";
0683 status = "disabled";
0684 };
0685
0686 spi7: spi@1101e000 {
0687 compatible = "mediatek,mt8192-spi",
0688 "mediatek,mt6765-spi";
0689 #address-cells = <1>;
0690 #size-cells = <0>;
0691 reg = <0 0x1101e000 0 0x1000>;
0692 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
0693 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
0694 <&topckgen CLK_TOP_SPI_SEL>,
0695 <&infracfg CLK_INFRA_SPI7>;
0696 clock-names = "parent-clk", "sel-clk", "spi-clk";
0697 status = "disabled";
0698 };
0699
0700 scp: scp@10500000 {
0701 compatible = "mediatek,mt8192-scp";
0702 reg = <0 0x10500000 0 0x100000>,
0703 <0 0x10720000 0 0xe0000>,
0704 <0 0x10700000 0 0x8000>;
0705 reg-names = "sram", "cfg", "l1tcm";
0706 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
0707 clocks = <&infracfg CLK_INFRA_SCPSYS>;
0708 clock-names = "main";
0709 status = "disabled";
0710 };
0711
0712 xhci: usb@11200000 {
0713 compatible = "mediatek,mt8192-xhci",
0714 "mediatek,mtk-xhci";
0715 reg = <0 0x11200000 0 0x1000>,
0716 <0 0x11203e00 0 0x0100>;
0717 reg-names = "mac", "ippc";
0718 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
0719 interrupt-names = "host";
0720 phys = <&u2port0 PHY_TYPE_USB2>,
0721 <&u3port0 PHY_TYPE_USB3>;
0722 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
0723 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
0724 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
0725 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
0726 clocks = <&infracfg CLK_INFRA_SSUSB>,
0727 <&infracfg CLK_INFRA_SSUSB_XHCI>,
0728 <&apmixedsys CLK_APMIXED_USBPLL>;
0729 clock-names = "sys_ck", "xhci_ck", "ref_ck";
0730 wakeup-source;
0731 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
0732 status = "disabled";
0733 };
0734
0735 audsys: syscon@11210000 {
0736 compatible = "mediatek,mt8192-audsys", "syscon";
0737 reg = <0 0x11210000 0 0x2000>;
0738 #clock-cells = <1>;
0739
0740 afe: mt8192-afe-pcm {
0741 compatible = "mediatek,mt8192-audio";
0742 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
0743 resets = <&watchdog 17>;
0744 reset-names = "audiosys";
0745 mediatek,apmixedsys = <&apmixedsys>;
0746 mediatek,infracfg = <&infracfg>;
0747 mediatek,topckgen = <&topckgen>;
0748 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
0749 clocks = <&audsys CLK_AUD_AFE>,
0750 <&audsys CLK_AUD_DAC>,
0751 <&audsys CLK_AUD_DAC_PREDIS>,
0752 <&audsys CLK_AUD_ADC>,
0753 <&audsys CLK_AUD_ADDA6_ADC>,
0754 <&audsys CLK_AUD_22M>,
0755 <&audsys CLK_AUD_24M>,
0756 <&audsys CLK_AUD_APLL_TUNER>,
0757 <&audsys CLK_AUD_APLL2_TUNER>,
0758 <&audsys CLK_AUD_TDM>,
0759 <&audsys CLK_AUD_TML>,
0760 <&audsys CLK_AUD_NLE>,
0761 <&audsys CLK_AUD_DAC_HIRES>,
0762 <&audsys CLK_AUD_ADC_HIRES>,
0763 <&audsys CLK_AUD_ADC_HIRES_TML>,
0764 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
0765 <&audsys CLK_AUD_3RD_DAC>,
0766 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
0767 <&audsys CLK_AUD_3RD_DAC_TML>,
0768 <&audsys CLK_AUD_3RD_DAC_HIRES>,
0769 <&infracfg CLK_INFRA_AUDIO>,
0770 <&infracfg CLK_INFRA_AUDIO_26M_B>,
0771 <&topckgen CLK_TOP_AUDIO_SEL>,
0772 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
0773 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
0774 <&topckgen CLK_TOP_AUD_1_SEL>,
0775 <&topckgen CLK_TOP_APLL1>,
0776 <&topckgen CLK_TOP_AUD_2_SEL>,
0777 <&topckgen CLK_TOP_APLL2>,
0778 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
0779 <&topckgen CLK_TOP_APLL1_D4>,
0780 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
0781 <&topckgen CLK_TOP_APLL2_D4>,
0782 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
0783 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
0784 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
0785 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
0786 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
0787 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
0788 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
0789 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
0790 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
0791 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
0792 <&topckgen CLK_TOP_APLL12_DIV0>,
0793 <&topckgen CLK_TOP_APLL12_DIV1>,
0794 <&topckgen CLK_TOP_APLL12_DIV2>,
0795 <&topckgen CLK_TOP_APLL12_DIV3>,
0796 <&topckgen CLK_TOP_APLL12_DIV4>,
0797 <&topckgen CLK_TOP_APLL12_DIVB>,
0798 <&topckgen CLK_TOP_APLL12_DIV5>,
0799 <&topckgen CLK_TOP_APLL12_DIV6>,
0800 <&topckgen CLK_TOP_APLL12_DIV7>,
0801 <&topckgen CLK_TOP_APLL12_DIV8>,
0802 <&topckgen CLK_TOP_APLL12_DIV9>,
0803 <&topckgen CLK_TOP_AUDIO_H_SEL>,
0804 <&clk26m>;
0805 clock-names = "aud_afe_clk",
0806 "aud_dac_clk",
0807 "aud_dac_predis_clk",
0808 "aud_adc_clk",
0809 "aud_adda6_adc_clk",
0810 "aud_apll22m_clk",
0811 "aud_apll24m_clk",
0812 "aud_apll1_tuner_clk",
0813 "aud_apll2_tuner_clk",
0814 "aud_tdm_clk",
0815 "aud_tml_clk",
0816 "aud_nle",
0817 "aud_dac_hires_clk",
0818 "aud_adc_hires_clk",
0819 "aud_adc_hires_tml",
0820 "aud_adda6_adc_hires_clk",
0821 "aud_3rd_dac_clk",
0822 "aud_3rd_dac_predis_clk",
0823 "aud_3rd_dac_tml",
0824 "aud_3rd_dac_hires_clk",
0825 "aud_infra_clk",
0826 "aud_infra_26m_clk",
0827 "top_mux_audio",
0828 "top_mux_audio_int",
0829 "top_mainpll_d4_d4",
0830 "top_mux_aud_1",
0831 "top_apll1_ck",
0832 "top_mux_aud_2",
0833 "top_apll2_ck",
0834 "top_mux_aud_eng1",
0835 "top_apll1_d4",
0836 "top_mux_aud_eng2",
0837 "top_apll2_d4",
0838 "top_i2s0_m_sel",
0839 "top_i2s1_m_sel",
0840 "top_i2s2_m_sel",
0841 "top_i2s3_m_sel",
0842 "top_i2s4_m_sel",
0843 "top_i2s5_m_sel",
0844 "top_i2s6_m_sel",
0845 "top_i2s7_m_sel",
0846 "top_i2s8_m_sel",
0847 "top_i2s9_m_sel",
0848 "top_apll12_div0",
0849 "top_apll12_div1",
0850 "top_apll12_div2",
0851 "top_apll12_div3",
0852 "top_apll12_div4",
0853 "top_apll12_divb",
0854 "top_apll12_div5",
0855 "top_apll12_div6",
0856 "top_apll12_div7",
0857 "top_apll12_div8",
0858 "top_apll12_div9",
0859 "top_mux_audio_h",
0860 "top_clk26m_clk";
0861 };
0862 };
0863
0864 pcie: pcie@11230000 {
0865 compatible = "mediatek,mt8192-pcie";
0866 device_type = "pci";
0867 reg = <0 0x11230000 0 0x2000>;
0868 reg-names = "pcie-mac";
0869 #address-cells = <3>;
0870 #size-cells = <2>;
0871 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
0872 <&infracfg CLK_INFRA_PCIE_TL_26M>,
0873 <&infracfg CLK_INFRA_PCIE_TL_96M>,
0874 <&infracfg CLK_INFRA_PCIE_TL_32K>,
0875 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
0876 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
0877 clock-names = "pl_250m", "tl_26m", "tl_96m",
0878 "tl_32k", "peri_26m", "top_133m";
0879 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
0880 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
0881 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
0882 bus-range = <0x00 0xff>;
0883 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
0884 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
0885 #interrupt-cells = <1>;
0886 interrupt-map-mask = <0 0 0 7>;
0887 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0888 <0 0 0 2 &pcie_intc0 1>,
0889 <0 0 0 3 &pcie_intc0 2>,
0890 <0 0 0 4 &pcie_intc0 3>;
0891
0892 pcie_intc0: interrupt-controller {
0893 interrupt-controller;
0894 #address-cells = <0>;
0895 #interrupt-cells = <1>;
0896 };
0897 };
0898
0899 nor_flash: spi@11234000 {
0900 compatible = "mediatek,mt8192-nor";
0901 reg = <0 0x11234000 0 0xe0>;
0902 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
0903 clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
0904 <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
0905 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
0906 clock-names = "spi", "sf", "axi";
0907 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
0908 assigned-clock-parents = <&clk26m>;
0909 #address-cells = <1>;
0910 #size-cells = <0>;
0911 status = "disabled";
0912 };
0913
0914 efuse: efuse@11c10000 {
0915 compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
0916 reg = <0 0x11c10000 0 0x1000>;
0917 #address-cells = <1>;
0918 #size-cells = <1>;
0919
0920 lvts_e_data1: data1@1c0 {
0921 reg = <0x1c0 0x58>;
0922 };
0923
0924 svs_calibration: calib@580 {
0925 reg = <0x580 0x68>;
0926 };
0927 };
0928
0929 i2c3: i2c@11cb0000 {
0930 compatible = "mediatek,mt8192-i2c";
0931 reg = <0 0x11cb0000 0 0x1000>,
0932 <0 0x10217300 0 0x80>;
0933 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
0934 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
0935 <&infracfg CLK_INFRA_AP_DMA>;
0936 clock-names = "main", "dma";
0937 clock-div = <1>;
0938 #address-cells = <1>;
0939 #size-cells = <0>;
0940 status = "disabled";
0941 };
0942
0943 imp_iic_wrap_e: clock-controller@11cb1000 {
0944 compatible = "mediatek,mt8192-imp_iic_wrap_e";
0945 reg = <0 0x11cb1000 0 0x1000>;
0946 #clock-cells = <1>;
0947 };
0948
0949 i2c7: i2c@11d00000 {
0950 compatible = "mediatek,mt8192-i2c";
0951 reg = <0 0x11d00000 0 0x1000>,
0952 <0 0x10217600 0 0x180>;
0953 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
0954 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
0955 <&infracfg CLK_INFRA_AP_DMA>;
0956 clock-names = "main", "dma";
0957 clock-div = <1>;
0958 #address-cells = <1>;
0959 #size-cells = <0>;
0960 status = "disabled";
0961 };
0962
0963 i2c8: i2c@11d01000 {
0964 compatible = "mediatek,mt8192-i2c";
0965 reg = <0 0x11d01000 0 0x1000>,
0966 <0 0x10217780 0 0x180>;
0967 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
0968 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
0969 <&infracfg CLK_INFRA_AP_DMA>;
0970 clock-names = "main", "dma";
0971 clock-div = <1>;
0972 #address-cells = <1>;
0973 #size-cells = <0>;
0974 status = "disabled";
0975 };
0976
0977 i2c9: i2c@11d02000 {
0978 compatible = "mediatek,mt8192-i2c";
0979 reg = <0 0x11d02000 0 0x1000>,
0980 <0 0x10217900 0 0x180>;
0981 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
0982 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
0983 <&infracfg CLK_INFRA_AP_DMA>;
0984 clock-names = "main", "dma";
0985 clock-div = <1>;
0986 #address-cells = <1>;
0987 #size-cells = <0>;
0988 status = "disabled";
0989 };
0990
0991 imp_iic_wrap_s: clock-controller@11d03000 {
0992 compatible = "mediatek,mt8192-imp_iic_wrap_s";
0993 reg = <0 0x11d03000 0 0x1000>;
0994 #clock-cells = <1>;
0995 };
0996
0997 i2c1: i2c@11d20000 {
0998 compatible = "mediatek,mt8192-i2c";
0999 reg = <0 0x11d20000 0 0x1000>,
1000 <0 0x10217100 0 0x80>;
1001 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1002 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
1003 <&infracfg CLK_INFRA_AP_DMA>;
1004 clock-names = "main", "dma";
1005 clock-div = <1>;
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 status = "disabled";
1009 };
1010
1011 i2c2: i2c@11d21000 {
1012 compatible = "mediatek,mt8192-i2c";
1013 reg = <0 0x11d21000 0 0x1000>,
1014 <0 0x10217180 0 0x180>;
1015 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1016 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
1017 <&infracfg CLK_INFRA_AP_DMA>;
1018 clock-names = "main", "dma";
1019 clock-div = <1>;
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 status = "disabled";
1023 };
1024
1025 i2c4: i2c@11d22000 {
1026 compatible = "mediatek,mt8192-i2c";
1027 reg = <0 0x11d22000 0 0x1000>,
1028 <0 0x10217380 0 0x180>;
1029 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1030 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
1031 <&infracfg CLK_INFRA_AP_DMA>;
1032 clock-names = "main", "dma";
1033 clock-div = <1>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 status = "disabled";
1037 };
1038
1039 imp_iic_wrap_ws: clock-controller@11d23000 {
1040 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1041 reg = <0 0x11d23000 0 0x1000>;
1042 #clock-cells = <1>;
1043 };
1044
1045 i2c5: i2c@11e00000 {
1046 compatible = "mediatek,mt8192-i2c";
1047 reg = <0 0x11e00000 0 0x1000>,
1048 <0 0x10217500 0 0x80>;
1049 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1050 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
1051 <&infracfg CLK_INFRA_AP_DMA>;
1052 clock-names = "main", "dma";
1053 clock-div = <1>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 status = "disabled";
1057 };
1058
1059 imp_iic_wrap_w: clock-controller@11e01000 {
1060 compatible = "mediatek,mt8192-imp_iic_wrap_w";
1061 reg = <0 0x11e01000 0 0x1000>;
1062 #clock-cells = <1>;
1063 };
1064
1065 u3phy0: t-phy@11e40000 {
1066 compatible = "mediatek,mt8192-tphy",
1067 "mediatek,generic-tphy-v2";
1068 #address-cells = <1>;
1069 #size-cells = <1>;
1070 ranges = <0x0 0x0 0x11e40000 0x1000>;
1071
1072 u2port0: usb-phy@0 {
1073 reg = <0x0 0x700>;
1074 clocks = <&clk26m>;
1075 clock-names = "ref";
1076 #phy-cells = <1>;
1077 };
1078
1079 u3port0: usb-phy@700 {
1080 reg = <0x700 0x900>;
1081 clocks = <&clk26m>;
1082 clock-names = "ref";
1083 #phy-cells = <1>;
1084 };
1085 };
1086
1087 i2c0: i2c@11f00000 {
1088 compatible = "mediatek,mt8192-i2c";
1089 reg = <0 0x11f00000 0 0x1000>,
1090 <0 0x10217080 0 0x80>;
1091 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1092 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1093 <&infracfg CLK_INFRA_AP_DMA>;
1094 clock-names = "main", "dma";
1095 clock-div = <1>;
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1098 status = "disabled";
1099 };
1100
1101 i2c6: i2c@11f01000 {
1102 compatible = "mediatek,mt8192-i2c";
1103 reg = <0 0x11f01000 0 0x1000>,
1104 <0 0x10217580 0 0x80>;
1105 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1106 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
1107 <&infracfg CLK_INFRA_AP_DMA>;
1108 clock-names = "main", "dma";
1109 clock-div = <1>;
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1112 status = "disabled";
1113 };
1114
1115 imp_iic_wrap_n: clock-controller@11f02000 {
1116 compatible = "mediatek,mt8192-imp_iic_wrap_n";
1117 reg = <0 0x11f02000 0 0x1000>;
1118 #clock-cells = <1>;
1119 };
1120
1121 msdc_top: clock-controller@11f10000 {
1122 compatible = "mediatek,mt8192-msdc_top";
1123 reg = <0 0x11f10000 0 0x1000>;
1124 #clock-cells = <1>;
1125 };
1126
1127 mmc0: mmc@11f60000 {
1128 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1129 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
1130 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
1131 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1132 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
1133 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
1134 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1135 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
1136 <&msdc_top CLK_MSDC_TOP_AXI>,
1137 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1138 clock-names = "source", "hclk", "source_cg", "sys_cg",
1139 "pclk_cg", "axi_cg", "ahb_cg";
1140 status = "disabled";
1141 };
1142
1143 mmc1: mmc@11f70000 {
1144 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1145 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
1146 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
1147 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1148 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
1149 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
1150 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1151 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
1152 <&msdc_top CLK_MSDC_TOP_AXI>,
1153 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1154 clock-names = "source", "hclk", "source_cg", "sys_cg",
1155 "pclk_cg", "axi_cg", "ahb_cg";
1156 status = "disabled";
1157 };
1158
1159 mfgcfg: clock-controller@13fbf000 {
1160 compatible = "mediatek,mt8192-mfgcfg";
1161 reg = <0 0x13fbf000 0 0x1000>;
1162 #clock-cells = <1>;
1163 };
1164
1165 mmsys: syscon@14000000 {
1166 compatible = "mediatek,mt8192-mmsys", "syscon";
1167 reg = <0 0x14000000 0 0x1000>;
1168 #clock-cells = <1>;
1169 };
1170
1171 smi_common: smi@14002000 {
1172 compatible = "mediatek,mt8192-smi-common";
1173 reg = <0 0x14002000 0 0x1000>;
1174 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1175 <&mmsys CLK_MM_SMI_INFRA>,
1176 <&mmsys CLK_MM_SMI_GALS>,
1177 <&mmsys CLK_MM_SMI_GALS>;
1178 clock-names = "apb", "smi", "gals0", "gals1";
1179 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1180 };
1181
1182 larb0: larb@14003000 {
1183 compatible = "mediatek,mt8192-smi-larb";
1184 reg = <0 0x14003000 0 0x1000>;
1185 mediatek,larb-id = <0>;
1186 mediatek,smi = <&smi_common>;
1187 clocks = <&clk26m>, <&clk26m>;
1188 clock-names = "apb", "smi";
1189 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1190 };
1191
1192 larb1: larb@14004000 {
1193 compatible = "mediatek,mt8192-smi-larb";
1194 reg = <0 0x14004000 0 0x1000>;
1195 mediatek,larb-id = <1>;
1196 mediatek,smi = <&smi_common>;
1197 clocks = <&clk26m>, <&clk26m>;
1198 clock-names = "apb", "smi";
1199 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1200 };
1201
1202 dpi0: dpi@14016000 {
1203 compatible = "mediatek,mt8192-dpi";
1204 reg = <0 0x14016000 0 0x1000>;
1205 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1206 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1207 <&mmsys CLK_MM_DISP_DPI0>,
1208 <&apmixedsys CLK_APMIXED_TVDPLL>;
1209 clock-names = "pixel", "engine", "pll";
1210 status = "disabled";
1211 };
1212
1213 iommu0: m4u@1401d000 {
1214 compatible = "mediatek,mt8192-m4u";
1215 reg = <0 0x1401d000 0 0x1000>;
1216 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
1217 <&larb4>, <&larb5>, <&larb7>,
1218 <&larb9>, <&larb11>, <&larb13>,
1219 <&larb14>, <&larb16>, <&larb17>,
1220 <&larb18>, <&larb19>, <&larb20>;
1221 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1222 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1223 clock-names = "bclk";
1224 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1225 #iommu-cells = <1>;
1226 };
1227
1228 imgsys: clock-controller@15020000 {
1229 compatible = "mediatek,mt8192-imgsys";
1230 reg = <0 0x15020000 0 0x1000>;
1231 #clock-cells = <1>;
1232 };
1233
1234 larb9: larb@1502e000 {
1235 compatible = "mediatek,mt8192-smi-larb";
1236 reg = <0 0x1502e000 0 0x1000>;
1237 mediatek,larb-id = <9>;
1238 mediatek,smi = <&smi_common>;
1239 clocks = <&imgsys CLK_IMG_LARB9>,
1240 <&imgsys CLK_IMG_LARB9>;
1241 clock-names = "apb", "smi";
1242 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1243 };
1244
1245 imgsys2: clock-controller@15820000 {
1246 compatible = "mediatek,mt8192-imgsys2";
1247 reg = <0 0x15820000 0 0x1000>;
1248 #clock-cells = <1>;
1249 };
1250
1251 larb11: larb@1582e000 {
1252 compatible = "mediatek,mt8192-smi-larb";
1253 reg = <0 0x1582e000 0 0x1000>;
1254 mediatek,larb-id = <11>;
1255 mediatek,smi = <&smi_common>;
1256 clocks = <&imgsys2 CLK_IMG2_LARB11>,
1257 <&imgsys2 CLK_IMG2_LARB11>;
1258 clock-names = "apb", "smi";
1259 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1260 };
1261
1262 larb5: larb@1600d000 {
1263 compatible = "mediatek,mt8192-smi-larb";
1264 reg = <0 0x1600d000 0 0x1000>;
1265 mediatek,larb-id = <5>;
1266 mediatek,smi = <&smi_common>;
1267 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1268 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1269 clock-names = "apb", "smi";
1270 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1271 };
1272
1273 vdecsys_soc: clock-controller@1600f000 {
1274 compatible = "mediatek,mt8192-vdecsys_soc";
1275 reg = <0 0x1600f000 0 0x1000>;
1276 #clock-cells = <1>;
1277 };
1278
1279 larb4: larb@1602e000 {
1280 compatible = "mediatek,mt8192-smi-larb";
1281 reg = <0 0x1602e000 0 0x1000>;
1282 mediatek,larb-id = <4>;
1283 mediatek,smi = <&smi_common>;
1284 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
1285 <&vdecsys CLK_VDEC_SOC_LARB1>;
1286 clock-names = "apb", "smi";
1287 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1288 };
1289
1290 vdecsys: clock-controller@1602f000 {
1291 compatible = "mediatek,mt8192-vdecsys";
1292 reg = <0 0x1602f000 0 0x1000>;
1293 #clock-cells = <1>;
1294 };
1295
1296 vencsys: clock-controller@17000000 {
1297 compatible = "mediatek,mt8192-vencsys";
1298 reg = <0 0x17000000 0 0x1000>;
1299 #clock-cells = <1>;
1300 };
1301
1302 larb7: larb@17010000 {
1303 compatible = "mediatek,mt8192-smi-larb";
1304 reg = <0 0x17010000 0 0x1000>;
1305 mediatek,larb-id = <7>;
1306 mediatek,smi = <&smi_common>;
1307 clocks = <&vencsys CLK_VENC_SET0_LARB>,
1308 <&vencsys CLK_VENC_SET1_VENC>;
1309 clock-names = "apb", "smi";
1310 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1311 };
1312
1313 vcodec_enc: vcodec@17020000 {
1314 compatible = "mediatek,mt8192-vcodec-enc";
1315 reg = <0 0x17020000 0 0x2000>;
1316 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1317 <&iommu0 M4U_PORT_L7_VENC_REC>,
1318 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1319 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1320 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1321 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1322 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1323 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1324 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1325 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1326 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
1327 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1328 mediatek,scp = <&scp>;
1329 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1330 clocks = <&vencsys CLK_VENC_SET1_VENC>;
1331 clock-names = "venc-set1";
1332 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1333 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1334 };
1335
1336 camsys: clock-controller@1a000000 {
1337 compatible = "mediatek,mt8192-camsys";
1338 reg = <0 0x1a000000 0 0x1000>;
1339 #clock-cells = <1>;
1340 };
1341
1342 larb13: larb@1a001000 {
1343 compatible = "mediatek,mt8192-smi-larb";
1344 reg = <0 0x1a001000 0 0x1000>;
1345 mediatek,larb-id = <13>;
1346 mediatek,smi = <&smi_common>;
1347 clocks = <&camsys CLK_CAM_CAM>,
1348 <&camsys CLK_CAM_LARB13>;
1349 clock-names = "apb", "smi";
1350 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1351 };
1352
1353 larb14: larb@1a002000 {
1354 compatible = "mediatek,mt8192-smi-larb";
1355 reg = <0 0x1a002000 0 0x1000>;
1356 mediatek,larb-id = <14>;
1357 mediatek,smi = <&smi_common>;
1358 clocks = <&camsys CLK_CAM_CAM>,
1359 <&camsys CLK_CAM_LARB14>;
1360 clock-names = "apb", "smi";
1361 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1362 };
1363
1364 larb16: larb@1a00f000 {
1365 compatible = "mediatek,mt8192-smi-larb";
1366 reg = <0 0x1a00f000 0 0x1000>;
1367 mediatek,larb-id = <16>;
1368 mediatek,smi = <&smi_common>;
1369 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
1370 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1371 clock-names = "apb", "smi";
1372 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1373 };
1374
1375 larb17: larb@1a010000 {
1376 compatible = "mediatek,mt8192-smi-larb";
1377 reg = <0 0x1a010000 0 0x1000>;
1378 mediatek,larb-id = <17>;
1379 mediatek,smi = <&smi_common>;
1380 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
1381 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1382 clock-names = "apb", "smi";
1383 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1384 };
1385
1386 larb18: larb@1a011000 {
1387 compatible = "mediatek,mt8192-smi-larb";
1388 reg = <0 0x1a011000 0 0x1000>;
1389 mediatek,larb-id = <18>;
1390 mediatek,smi = <&smi_common>;
1391 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
1392 <&camsys_rawc CLK_CAM_RAWC_CAM>;
1393 clock-names = "apb", "smi";
1394 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1395 };
1396
1397 camsys_rawa: clock-controller@1a04f000 {
1398 compatible = "mediatek,mt8192-camsys_rawa";
1399 reg = <0 0x1a04f000 0 0x1000>;
1400 #clock-cells = <1>;
1401 };
1402
1403 camsys_rawb: clock-controller@1a06f000 {
1404 compatible = "mediatek,mt8192-camsys_rawb";
1405 reg = <0 0x1a06f000 0 0x1000>;
1406 #clock-cells = <1>;
1407 };
1408
1409 camsys_rawc: clock-controller@1a08f000 {
1410 compatible = "mediatek,mt8192-camsys_rawc";
1411 reg = <0 0x1a08f000 0 0x1000>;
1412 #clock-cells = <1>;
1413 };
1414
1415 ipesys: clock-controller@1b000000 {
1416 compatible = "mediatek,mt8192-ipesys";
1417 reg = <0 0x1b000000 0 0x1000>;
1418 #clock-cells = <1>;
1419 };
1420
1421 larb20: larb@1b00f000 {
1422 compatible = "mediatek,mt8192-smi-larb";
1423 reg = <0 0x1b00f000 0 0x1000>;
1424 mediatek,larb-id = <20>;
1425 mediatek,smi = <&smi_common>;
1426 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1427 <&ipesys CLK_IPE_LARB20>;
1428 clock-names = "apb", "smi";
1429 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1430 };
1431
1432 larb19: larb@1b10f000 {
1433 compatible = "mediatek,mt8192-smi-larb";
1434 reg = <0 0x1b10f000 0 0x1000>;
1435 mediatek,larb-id = <19>;
1436 mediatek,smi = <&smi_common>;
1437 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1438 <&ipesys CLK_IPE_LARB19>;
1439 clock-names = "apb", "smi";
1440 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1441 };
1442
1443 mdpsys: clock-controller@1f000000 {
1444 compatible = "mediatek,mt8192-mdpsys";
1445 reg = <0 0x1f000000 0 0x1000>;
1446 #clock-cells = <1>;
1447 };
1448
1449 larb2: larb@1f002000 {
1450 compatible = "mediatek,mt8192-smi-larb";
1451 reg = <0 0x1f002000 0 0x1000>;
1452 mediatek,larb-id = <2>;
1453 mediatek,smi = <&smi_common>;
1454 clocks = <&mdpsys CLK_MDP_SMI0>,
1455 <&mdpsys CLK_MDP_SMI0>;
1456 clock-names = "apb", "smi";
1457 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
1458 };
1459 };
1460 };
