0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (c) 2018 MediaTek Inc.
0004 * Author: Ben Ho <ben.ho@mediatek.com>
0005 * Erin Lo <erin.lo@mediatek.com>
0006 */
0007
0008 /dts-v1/;
0009 #include "mt8183.dtsi"
0010 #include "mt6358.dtsi"
0011
0012 / {
0013 model = "MediaTek MT8183 evaluation board";
0014 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
0015
0016 aliases {
0017 serial0 = &uart0;
0018 };
0019
0020 memory@40000000 {
0021 device_type = "memory";
0022 reg = <0 0x40000000 0 0x80000000>;
0023 };
0024
0025 chosen {
0026 stdout-path = "serial0:921600n8";
0027 };
0028
0029 reserved-memory {
0030 #address-cells = <2>;
0031 #size-cells = <2>;
0032 ranges;
0033 scp_mem_reserved: scp_mem_region {
0034 compatible = "shared-dma-pool";
0035 reg = <0 0x50000000 0 0x2900000>;
0036 no-map;
0037 };
0038 };
0039
0040 ntc@0 {
0041 compatible = "murata,ncp03wf104";
0042 pullup-uv = <1800000>;
0043 pullup-ohm = <390000>;
0044 pulldown-ohm = <0>;
0045 io-channels = <&auxadc 0>;
0046 };
0047 };
0048
0049 &auxadc {
0050 status = "okay";
0051 };
0052
0053 &gpu {
0054 mali-supply = <&mt6358_vgpu_reg>;
0055 sram-supply = <&mt6358_vsram_gpu_reg>;
0056 };
0057
0058 &i2c0 {
0059 pinctrl-names = "default";
0060 pinctrl-0 = <&i2c_pins_0>;
0061 status = "okay";
0062 clock-frequency = <100000>;
0063 };
0064
0065 &i2c1 {
0066 pinctrl-names = "default";
0067 pinctrl-0 = <&i2c_pins_1>;
0068 status = "okay";
0069 clock-frequency = <100000>;
0070 };
0071
0072 &i2c2 {
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&i2c_pins_2>;
0075 status = "okay";
0076 clock-frequency = <100000>;
0077 };
0078
0079 &i2c3 {
0080 pinctrl-names = "default";
0081 pinctrl-0 = <&i2c_pins_3>;
0082 status = "okay";
0083 clock-frequency = <100000>;
0084 };
0085
0086 &i2c4 {
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&i2c_pins_4>;
0089 status = "okay";
0090 clock-frequency = <1000000>;
0091 };
0092
0093 &i2c5 {
0094 pinctrl-names = "default";
0095 pinctrl-0 = <&i2c_pins_5>;
0096 status = "okay";
0097 clock-frequency = <1000000>;
0098 };
0099
0100 &mmc0 {
0101 status = "okay";
0102 pinctrl-names = "default", "state_uhs";
0103 pinctrl-0 = <&mmc0_pins_default>;
0104 pinctrl-1 = <&mmc0_pins_uhs>;
0105 bus-width = <8>;
0106 max-frequency = <200000000>;
0107 cap-mmc-highspeed;
0108 mmc-hs200-1_8v;
0109 mmc-hs400-1_8v;
0110 cap-mmc-hw-reset;
0111 no-sdio;
0112 no-sd;
0113 hs400-ds-delay = <0x12814>;
0114 vmmc-supply = <&mt6358_vemc_reg>;
0115 vqmmc-supply = <&mt6358_vio18_reg>;
0116 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
0117 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
0118 non-removable;
0119 };
0120
0121 &mmc1 {
0122 status = "okay";
0123 pinctrl-names = "default", "state_uhs";
0124 pinctrl-0 = <&mmc1_pins_default>;
0125 pinctrl-1 = <&mmc1_pins_uhs>;
0126 bus-width = <4>;
0127 max-frequency = <200000000>;
0128 cap-sd-highspeed;
0129 sd-uhs-sdr50;
0130 sd-uhs-sdr104;
0131 cap-sdio-irq;
0132 no-mmc;
0133 no-sd;
0134 vmmc-supply = <&mt6358_vmch_reg>;
0135 vqmmc-supply = <&mt6358_vmc_reg>;
0136 keep-power-in-suspend;
0137 wakeup-source;
0138 non-removable;
0139 };
0140
0141 &pio {
0142 i2c_pins_0: i2c0{
0143 pins_i2c{
0144 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
0145 <PINMUX_GPIO83__FUNC_SCL0>;
0146 mediatek,pull-up-adv = <3>;
0147 mediatek,drive-strength-adv = <00>;
0148 };
0149 };
0150
0151 i2c_pins_1: i2c1{
0152 pins_i2c{
0153 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
0154 <PINMUX_GPIO84__FUNC_SCL1>;
0155 mediatek,pull-up-adv = <3>;
0156 mediatek,drive-strength-adv = <00>;
0157 };
0158 };
0159
0160 i2c_pins_2: i2c2{
0161 pins_i2c{
0162 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
0163 <PINMUX_GPIO104__FUNC_SDA2>;
0164 mediatek,pull-up-adv = <3>;
0165 mediatek,drive-strength-adv = <00>;
0166 };
0167 };
0168
0169 i2c_pins_3: i2c3{
0170 pins_i2c{
0171 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
0172 <PINMUX_GPIO51__FUNC_SDA3>;
0173 mediatek,pull-up-adv = <3>;
0174 mediatek,drive-strength-adv = <00>;
0175 };
0176 };
0177
0178 i2c_pins_4: i2c4{
0179 pins_i2c{
0180 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
0181 <PINMUX_GPIO106__FUNC_SDA4>;
0182 mediatek,pull-up-adv = <3>;
0183 mediatek,drive-strength-adv = <00>;
0184 };
0185 };
0186
0187 i2c_pins_5: i2c5{
0188 pins_i2c{
0189 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
0190 <PINMUX_GPIO49__FUNC_SDA5>;
0191 mediatek,pull-up-adv = <3>;
0192 mediatek,drive-strength-adv = <00>;
0193 };
0194 };
0195
0196 spi_pins_0: spi0{
0197 pins_spi{
0198 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
0199 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
0200 <PINMUX_GPIO87__FUNC_SPI0_MO>,
0201 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
0202 bias-disable;
0203 };
0204 };
0205
0206 mmc0_pins_default: mmc0default {
0207 pins_cmd_dat {
0208 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
0209 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
0210 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
0211 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
0212 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
0213 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
0214 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
0215 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
0216 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
0217 input-enable;
0218 bias-pull-up;
0219 };
0220
0221 pins_clk {
0222 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
0223 bias-pull-down;
0224 };
0225
0226 pins_rst {
0227 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
0228 bias-pull-up;
0229 };
0230 };
0231
0232 mmc0_pins_uhs: mmc0 {
0233 pins_cmd_dat {
0234 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
0235 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
0236 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
0237 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
0238 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
0239 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
0240 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
0241 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
0242 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
0243 input-enable;
0244 drive-strength = <MTK_DRIVE_10mA>;
0245 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0246 };
0247
0248 pins_clk {
0249 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
0250 drive-strength = <MTK_DRIVE_10mA>;
0251 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0252 };
0253
0254 pins_ds {
0255 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
0256 drive-strength = <MTK_DRIVE_10mA>;
0257 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0258 };
0259
0260 pins_rst {
0261 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
0262 drive-strength = <MTK_DRIVE_10mA>;
0263 bias-pull-up;
0264 };
0265 };
0266
0267 mmc1_pins_default: mmc1default {
0268 pins_cmd_dat {
0269 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
0270 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
0271 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
0272 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
0273 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
0274 input-enable;
0275 bias-pull-up;
0276 };
0277
0278 pins_clk {
0279 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
0280 input-enable;
0281 bias-pull-down;
0282 };
0283
0284 pins_pmu {
0285 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
0286 <PINMUX_GPIO166__FUNC_GPIO166>;
0287 output-high;
0288 };
0289 };
0290
0291 mmc1_pins_uhs: mmc1 {
0292 pins_cmd_dat {
0293 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
0294 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
0295 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
0296 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
0297 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
0298 drive-strength = <MTK_DRIVE_6mA>;
0299 input-enable;
0300 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
0301 };
0302
0303 pins_clk {
0304 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
0305 drive-strength = <MTK_DRIVE_6mA>;
0306 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
0307 input-enable;
0308 };
0309 };
0310
0311 spi_pins_1: spi1{
0312 pins_spi{
0313 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
0314 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
0315 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
0316 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
0317 bias-disable;
0318 };
0319 };
0320
0321 spi_pins_2: spi2{
0322 pins_spi{
0323 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
0324 <PINMUX_GPIO1__FUNC_SPI2_MO>,
0325 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
0326 <PINMUX_GPIO94__FUNC_SPI2_MI>;
0327 bias-disable;
0328 };
0329 };
0330
0331 spi_pins_3: spi3{
0332 pins_spi{
0333 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
0334 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
0335 <PINMUX_GPIO23__FUNC_SPI3_MO>,
0336 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
0337 bias-disable;
0338 };
0339 };
0340
0341 spi_pins_4: spi4{
0342 pins_spi{
0343 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
0344 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
0345 <PINMUX_GPIO19__FUNC_SPI4_MO>,
0346 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
0347 bias-disable;
0348 };
0349 };
0350
0351 spi_pins_5: spi5{
0352 pins_spi{
0353 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
0354 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
0355 <PINMUX_GPIO15__FUNC_SPI5_MO>,
0356 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
0357 bias-disable;
0358 };
0359 };
0360
0361 pwm_pins_1: pwm1 {
0362 pins_pwm {
0363 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
0364 };
0365 };
0366 };
0367
0368 &mfg {
0369 domain-supply = <&mt6358_vgpu_reg>;
0370 };
0371
0372 &spi0 {
0373 pinctrl-names = "default";
0374 pinctrl-0 = <&spi_pins_0>;
0375 mediatek,pad-select = <0>;
0376 status = "okay";
0377 };
0378
0379 &spi1 {
0380 pinctrl-names = "default";
0381 pinctrl-0 = <&spi_pins_1>;
0382 mediatek,pad-select = <0>;
0383 status = "okay";
0384 };
0385
0386 &spi2 {
0387 pinctrl-names = "default";
0388 pinctrl-0 = <&spi_pins_2>;
0389 mediatek,pad-select = <0>;
0390 status = "okay";
0391 };
0392
0393 &spi3 {
0394 pinctrl-names = "default";
0395 pinctrl-0 = <&spi_pins_3>;
0396 mediatek,pad-select = <0>;
0397 status = "okay";
0398 };
0399
0400 &spi4 {
0401 pinctrl-names = "default";
0402 pinctrl-0 = <&spi_pins_4>;
0403 mediatek,pad-select = <0>;
0404 status = "okay";
0405 };
0406
0407 &spi5 {
0408 pinctrl-names = "default";
0409 pinctrl-0 = <&spi_pins_5>;
0410 mediatek,pad-select = <0>;
0411 status = "okay";
0412
0413 };
0414
0415 &cci {
0416 proc-supply = <&mt6358_vproc12_reg>;
0417 };
0418
0419 &cpu0 {
0420 proc-supply = <&mt6358_vproc12_reg>;
0421 };
0422
0423 &cpu1 {
0424 proc-supply = <&mt6358_vproc12_reg>;
0425 };
0426
0427 &cpu2 {
0428 proc-supply = <&mt6358_vproc12_reg>;
0429 };
0430
0431 &cpu3 {
0432 proc-supply = <&mt6358_vproc12_reg>;
0433 };
0434
0435 &cpu4 {
0436 proc-supply = <&mt6358_vproc11_reg>;
0437 };
0438
0439 &cpu5 {
0440 proc-supply = <&mt6358_vproc11_reg>;
0441 };
0442
0443 &cpu6 {
0444 proc-supply = <&mt6358_vproc11_reg>;
0445 };
0446
0447 &cpu7 {
0448 proc-supply = <&mt6358_vproc11_reg>;
0449 };
0450
0451 &uart0 {
0452 status = "okay";
0453 };
0454
0455 &pwm1 {
0456 status = "okay";
0457 pinctrl-0 = <&pwm_pins_1>;
0458 pinctrl-names = "default";
0459 };
