0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2014 MediaTek Inc.
0004 * Author: Eddie Huang <eddie.huang@mediatek.com>
0005 */
0006
0007 #include <dt-bindings/clock/mt8173-clk.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/memory/mt8173-larb-port.h>
0011 #include <dt-bindings/phy/phy.h>
0012 #include <dt-bindings/power/mt8173-power.h>
0013 #include <dt-bindings/reset/mt8173-resets.h>
0014 #include <dt-bindings/gce/mt8173-gce.h>
0015 #include <dt-bindings/thermal/thermal.h>
0016 #include "mt8173-pinfunc.h"
0017
0018 / {
0019 compatible = "mediatek,mt8173";
0020 interrupt-parent = <&sysirq>;
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023
0024 aliases {
0025 ovl0 = &ovl0;
0026 ovl1 = &ovl1;
0027 rdma0 = &rdma0;
0028 rdma1 = &rdma1;
0029 rdma2 = &rdma2;
0030 wdma0 = &wdma0;
0031 wdma1 = &wdma1;
0032 color0 = &color0;
0033 color1 = &color1;
0034 split0 = &split0;
0035 split1 = &split1;
0036 dpi0 = &dpi0;
0037 dsi0 = &dsi0;
0038 dsi1 = &dsi1;
0039 mdp-rdma0 = &mdp_rdma0;
0040 mdp-rdma1 = &mdp_rdma1;
0041 mdp-rsz0 = &mdp_rsz0;
0042 mdp-rsz1 = &mdp_rsz1;
0043 mdp-rsz2 = &mdp_rsz2;
0044 mdp-wdma0 = &mdp_wdma0;
0045 mdp-wrot0 = &mdp_wrot0;
0046 mdp-wrot1 = &mdp_wrot1;
0047 serial0 = &uart0;
0048 serial1 = &uart1;
0049 serial2 = &uart2;
0050 serial3 = &uart3;
0051 };
0052
0053 cluster0_opp: opp-table-0 {
0054 compatible = "operating-points-v2";
0055 opp-shared;
0056 opp-507000000 {
0057 opp-hz = /bits/ 64 <507000000>;
0058 opp-microvolt = <859000>;
0059 };
0060 opp-702000000 {
0061 opp-hz = /bits/ 64 <702000000>;
0062 opp-microvolt = <908000>;
0063 };
0064 opp-1001000000 {
0065 opp-hz = /bits/ 64 <1001000000>;
0066 opp-microvolt = <983000>;
0067 };
0068 opp-1105000000 {
0069 opp-hz = /bits/ 64 <1105000000>;
0070 opp-microvolt = <1009000>;
0071 };
0072 opp-1209000000 {
0073 opp-hz = /bits/ 64 <1209000000>;
0074 opp-microvolt = <1034000>;
0075 };
0076 opp-1300000000 {
0077 opp-hz = /bits/ 64 <1300000000>;
0078 opp-microvolt = <1057000>;
0079 };
0080 opp-1508000000 {
0081 opp-hz = /bits/ 64 <1508000000>;
0082 opp-microvolt = <1109000>;
0083 };
0084 opp-1703000000 {
0085 opp-hz = /bits/ 64 <1703000000>;
0086 opp-microvolt = <1125000>;
0087 };
0088 };
0089
0090 cluster1_opp: opp-table-1 {
0091 compatible = "operating-points-v2";
0092 opp-shared;
0093 opp-507000000 {
0094 opp-hz = /bits/ 64 <507000000>;
0095 opp-microvolt = <828000>;
0096 };
0097 opp-702000000 {
0098 opp-hz = /bits/ 64 <702000000>;
0099 opp-microvolt = <867000>;
0100 };
0101 opp-1001000000 {
0102 opp-hz = /bits/ 64 <1001000000>;
0103 opp-microvolt = <927000>;
0104 };
0105 opp-1209000000 {
0106 opp-hz = /bits/ 64 <1209000000>;
0107 opp-microvolt = <968000>;
0108 };
0109 opp-1404000000 {
0110 opp-hz = /bits/ 64 <1404000000>;
0111 opp-microvolt = <1007000>;
0112 };
0113 opp-1612000000 {
0114 opp-hz = /bits/ 64 <1612000000>;
0115 opp-microvolt = <1049000>;
0116 };
0117 opp-1807000000 {
0118 opp-hz = /bits/ 64 <1807000000>;
0119 opp-microvolt = <1089000>;
0120 };
0121 opp-2106000000 {
0122 opp-hz = /bits/ 64 <2106000000>;
0123 opp-microvolt = <1125000>;
0124 };
0125 };
0126
0127 cpus {
0128 #address-cells = <1>;
0129 #size-cells = <0>;
0130
0131 cpu-map {
0132 cluster0 {
0133 core0 {
0134 cpu = <&cpu0>;
0135 };
0136 core1 {
0137 cpu = <&cpu1>;
0138 };
0139 };
0140
0141 cluster1 {
0142 core0 {
0143 cpu = <&cpu2>;
0144 };
0145 core1 {
0146 cpu = <&cpu3>;
0147 };
0148 };
0149 };
0150
0151 cpu0: cpu@0 {
0152 device_type = "cpu";
0153 compatible = "arm,cortex-a53";
0154 reg = <0x000>;
0155 enable-method = "psci";
0156 cpu-idle-states = <&CPU_SLEEP_0>;
0157 #cooling-cells = <2>;
0158 dynamic-power-coefficient = <263>;
0159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
0160 <&apmixedsys CLK_APMIXED_MAINPLL>;
0161 clock-names = "cpu", "intermediate";
0162 operating-points-v2 = <&cluster0_opp>;
0163 capacity-dmips-mhz = <740>;
0164 };
0165
0166 cpu1: cpu@1 {
0167 device_type = "cpu";
0168 compatible = "arm,cortex-a53";
0169 reg = <0x001>;
0170 enable-method = "psci";
0171 cpu-idle-states = <&CPU_SLEEP_0>;
0172 #cooling-cells = <2>;
0173 dynamic-power-coefficient = <263>;
0174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
0175 <&apmixedsys CLK_APMIXED_MAINPLL>;
0176 clock-names = "cpu", "intermediate";
0177 operating-points-v2 = <&cluster0_opp>;
0178 capacity-dmips-mhz = <740>;
0179 };
0180
0181 cpu2: cpu@100 {
0182 device_type = "cpu";
0183 compatible = "arm,cortex-a72";
0184 reg = <0x100>;
0185 enable-method = "psci";
0186 cpu-idle-states = <&CPU_SLEEP_0>;
0187 #cooling-cells = <2>;
0188 dynamic-power-coefficient = <530>;
0189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
0190 <&apmixedsys CLK_APMIXED_MAINPLL>;
0191 clock-names = "cpu", "intermediate";
0192 operating-points-v2 = <&cluster1_opp>;
0193 capacity-dmips-mhz = <1024>;
0194 };
0195
0196 cpu3: cpu@101 {
0197 device_type = "cpu";
0198 compatible = "arm,cortex-a72";
0199 reg = <0x101>;
0200 enable-method = "psci";
0201 cpu-idle-states = <&CPU_SLEEP_0>;
0202 #cooling-cells = <2>;
0203 dynamic-power-coefficient = <530>;
0204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
0205 <&apmixedsys CLK_APMIXED_MAINPLL>;
0206 clock-names = "cpu", "intermediate";
0207 operating-points-v2 = <&cluster1_opp>;
0208 capacity-dmips-mhz = <1024>;
0209 };
0210
0211 idle-states {
0212 entry-method = "psci";
0213
0214 CPU_SLEEP_0: cpu-sleep-0 {
0215 compatible = "arm,idle-state";
0216 local-timer-stop;
0217 entry-latency-us = <639>;
0218 exit-latency-us = <680>;
0219 min-residency-us = <1088>;
0220 arm,psci-suspend-param = <0x0010000>;
0221 };
0222 };
0223 };
0224
0225 pmu_a53 {
0226 compatible = "arm,cortex-a53-pmu";
0227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
0228 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
0229 interrupt-affinity = <&cpu0>, <&cpu1>;
0230 };
0231
0232 pmu_a72 {
0233 compatible = "arm,cortex-a72-pmu";
0234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
0235 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
0236 interrupt-affinity = <&cpu2>, <&cpu3>;
0237 };
0238
0239 psci {
0240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
0241 method = "smc";
0242 cpu_suspend = <0x84000001>;
0243 cpu_off = <0x84000002>;
0244 cpu_on = <0x84000003>;
0245 };
0246
0247 clk26m: oscillator0 {
0248 compatible = "fixed-clock";
0249 #clock-cells = <0>;
0250 clock-frequency = <26000000>;
0251 clock-output-names = "clk26m";
0252 };
0253
0254 clk32k: oscillator1 {
0255 compatible = "fixed-clock";
0256 #clock-cells = <0>;
0257 clock-frequency = <32000>;
0258 clock-output-names = "clk32k";
0259 };
0260
0261 cpum_ck: oscillator2 {
0262 compatible = "fixed-clock";
0263 #clock-cells = <0>;
0264 clock-frequency = <0>;
0265 clock-output-names = "cpum_ck";
0266 };
0267
0268 thermal-zones {
0269 cpu_thermal: cpu-thermal {
0270 polling-delay-passive = <1000>; /* milliseconds */
0271 polling-delay = <1000>; /* milliseconds */
0272
0273 thermal-sensors = <&thermal>;
0274 sustainable-power = <1500>; /* milliwatts */
0275
0276 trips {
0277 threshold: trip-point0 {
0278 temperature = <68000>;
0279 hysteresis = <2000>;
0280 type = "passive";
0281 };
0282
0283 target: trip-point1 {
0284 temperature = <85000>;
0285 hysteresis = <2000>;
0286 type = "passive";
0287 };
0288
0289 cpu_crit: cpu_crit0 {
0290 temperature = <115000>;
0291 hysteresis = <2000>;
0292 type = "critical";
0293 };
0294 };
0295
0296 cooling-maps {
0297 map0 {
0298 trip = <&target>;
0299 cooling-device = <&cpu0 THERMAL_NO_LIMIT
0300 THERMAL_NO_LIMIT>,
0301 <&cpu1 THERMAL_NO_LIMIT
0302 THERMAL_NO_LIMIT>;
0303 contribution = <3072>;
0304 };
0305 map1 {
0306 trip = <&target>;
0307 cooling-device = <&cpu2 THERMAL_NO_LIMIT
0308 THERMAL_NO_LIMIT>,
0309 <&cpu3 THERMAL_NO_LIMIT
0310 THERMAL_NO_LIMIT>;
0311 contribution = <1024>;
0312 };
0313 };
0314 };
0315 };
0316
0317 reserved-memory {
0318 #address-cells = <2>;
0319 #size-cells = <2>;
0320 ranges;
0321 vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
0322 compatible = "shared-dma-pool";
0323 reg = <0 0xb7000000 0 0x500000>;
0324 alignment = <0x1000>;
0325 no-map;
0326 };
0327 };
0328
0329 timer {
0330 compatible = "arm,armv8-timer";
0331 interrupt-parent = <&gic>;
0332 interrupts = <GIC_PPI 13
0333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0334 <GIC_PPI 14
0335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0336 <GIC_PPI 11
0337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0338 <GIC_PPI 10
0339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0340 arm,no-tick-in-suspend;
0341 };
0342
0343 soc {
0344 #address-cells = <2>;
0345 #size-cells = <2>;
0346 compatible = "simple-bus";
0347 ranges;
0348
0349 topckgen: clock-controller@10000000 {
0350 compatible = "mediatek,mt8173-topckgen";
0351 reg = <0 0x10000000 0 0x1000>;
0352 #clock-cells = <1>;
0353 };
0354
0355 infracfg: power-controller@10001000 {
0356 compatible = "mediatek,mt8173-infracfg", "syscon";
0357 reg = <0 0x10001000 0 0x1000>;
0358 #clock-cells = <1>;
0359 #reset-cells = <1>;
0360 };
0361
0362 pericfg: power-controller@10003000 {
0363 compatible = "mediatek,mt8173-pericfg", "syscon";
0364 reg = <0 0x10003000 0 0x1000>;
0365 #clock-cells = <1>;
0366 #reset-cells = <1>;
0367 };
0368
0369 syscfg_pctl_a: syscfg_pctl_a@10005000 {
0370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
0371 reg = <0 0x10005000 0 0x1000>;
0372 };
0373
0374 pio: pinctrl@1000b000 {
0375 compatible = "mediatek,mt8173-pinctrl";
0376 reg = <0 0x1000b000 0 0x1000>;
0377 mediatek,pctl-regmap = <&syscfg_pctl_a>;
0378 pins-are-numbered;
0379 gpio-controller;
0380 #gpio-cells = <2>;
0381 interrupt-controller;
0382 #interrupt-cells = <2>;
0383 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0384 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0385 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0386
0387 hdmi_pin: xxx {
0388
0389 /*hdmi htplg pin*/
0390 pins1 {
0391 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
0392 input-enable;
0393 bias-pull-down;
0394 };
0395 };
0396
0397 i2c0_pins_a: i2c0 {
0398 pins1 {
0399 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
0400 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
0401 bias-disable;
0402 };
0403 };
0404
0405 i2c1_pins_a: i2c1 {
0406 pins1 {
0407 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
0408 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
0409 bias-disable;
0410 };
0411 };
0412
0413 i2c2_pins_a: i2c2 {
0414 pins1 {
0415 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
0416 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
0417 bias-disable;
0418 };
0419 };
0420
0421 i2c3_pins_a: i2c3 {
0422 pins1 {
0423 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
0424 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
0425 bias-disable;
0426 };
0427 };
0428
0429 i2c4_pins_a: i2c4 {
0430 pins1 {
0431 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
0432 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
0433 bias-disable;
0434 };
0435 };
0436
0437 i2c6_pins_a: i2c6 {
0438 pins1 {
0439 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
0440 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
0441 bias-disable;
0442 };
0443 };
0444 };
0445
0446 scpsys: syscon@10006000 {
0447 compatible = "syscon", "simple-mfd";
0448 reg = <0 0x10006000 0 0x1000>;
0449 #power-domain-cells = <1>;
0450
0451 /* System Power Manager */
0452 spm: power-controller {
0453 compatible = "mediatek,mt8173-power-controller";
0454 #address-cells = <1>;
0455 #size-cells = <0>;
0456 #power-domain-cells = <1>;
0457
0458 /* power domains of the SoC */
0459 power-domain@MT8173_POWER_DOMAIN_VDEC {
0460 reg = <MT8173_POWER_DOMAIN_VDEC>;
0461 clocks = <&topckgen CLK_TOP_MM_SEL>;
0462 clock-names = "mm";
0463 #power-domain-cells = <0>;
0464 };
0465 power-domain@MT8173_POWER_DOMAIN_VENC {
0466 reg = <MT8173_POWER_DOMAIN_VENC>;
0467 clocks = <&topckgen CLK_TOP_MM_SEL>,
0468 <&topckgen CLK_TOP_VENC_SEL>;
0469 clock-names = "mm", "venc";
0470 #power-domain-cells = <0>;
0471 };
0472 power-domain@MT8173_POWER_DOMAIN_ISP {
0473 reg = <MT8173_POWER_DOMAIN_ISP>;
0474 clocks = <&topckgen CLK_TOP_MM_SEL>;
0475 clock-names = "mm";
0476 #power-domain-cells = <0>;
0477 };
0478 power-domain@MT8173_POWER_DOMAIN_MM {
0479 reg = <MT8173_POWER_DOMAIN_MM>;
0480 clocks = <&topckgen CLK_TOP_MM_SEL>;
0481 clock-names = "mm";
0482 #power-domain-cells = <0>;
0483 mediatek,infracfg = <&infracfg>;
0484 };
0485 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
0486 reg = <MT8173_POWER_DOMAIN_VENC_LT>;
0487 clocks = <&topckgen CLK_TOP_MM_SEL>,
0488 <&topckgen CLK_TOP_VENC_LT_SEL>;
0489 clock-names = "mm", "venclt";
0490 #power-domain-cells = <0>;
0491 };
0492 power-domain@MT8173_POWER_DOMAIN_AUDIO {
0493 reg = <MT8173_POWER_DOMAIN_AUDIO>;
0494 #power-domain-cells = <0>;
0495 };
0496 power-domain@MT8173_POWER_DOMAIN_USB {
0497 reg = <MT8173_POWER_DOMAIN_USB>;
0498 #power-domain-cells = <0>;
0499 };
0500 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
0501 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
0502 clocks = <&clk26m>;
0503 clock-names = "mfg";
0504 #address-cells = <1>;
0505 #size-cells = <0>;
0506 #power-domain-cells = <1>;
0507
0508 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
0509 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
0510 #address-cells = <1>;
0511 #size-cells = <0>;
0512 #power-domain-cells = <1>;
0513
0514 power-domain@MT8173_POWER_DOMAIN_MFG {
0515 reg = <MT8173_POWER_DOMAIN_MFG>;
0516 #power-domain-cells = <0>;
0517 mediatek,infracfg = <&infracfg>;
0518 };
0519 };
0520 };
0521 };
0522 };
0523
0524 watchdog: watchdog@10007000 {
0525 compatible = "mediatek,mt8173-wdt",
0526 "mediatek,mt6589-wdt";
0527 reg = <0 0x10007000 0 0x100>;
0528 };
0529
0530 timer: timer@10008000 {
0531 compatible = "mediatek,mt8173-timer",
0532 "mediatek,mt6577-timer";
0533 reg = <0 0x10008000 0 0x1000>;
0534 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
0535 clocks = <&infracfg CLK_INFRA_CLK_13M>,
0536 <&topckgen CLK_TOP_RTC_SEL>;
0537 };
0538
0539 pwrap: pwrap@1000d000 {
0540 compatible = "mediatek,mt8173-pwrap";
0541 reg = <0 0x1000d000 0 0x1000>;
0542 reg-names = "pwrap";
0543 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0544 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
0545 reset-names = "pwrap";
0546 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
0547 clock-names = "spi", "wrap";
0548 };
0549
0550 cec: cec@10013000 {
0551 compatible = "mediatek,mt8173-cec";
0552 reg = <0 0x10013000 0 0xbc>;
0553 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
0554 clocks = <&infracfg CLK_INFRA_CEC>;
0555 status = "disabled";
0556 };
0557
0558 vpu: vpu@10020000 {
0559 compatible = "mediatek,mt8173-vpu";
0560 reg = <0 0x10020000 0 0x30000>,
0561 <0 0x10050000 0 0x100>;
0562 reg-names = "tcm", "cfg_reg";
0563 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
0564 clocks = <&topckgen CLK_TOP_SCP_SEL>;
0565 clock-names = "main";
0566 memory-region = <&vpu_dma_reserved>;
0567 };
0568
0569 sysirq: intpol-controller@10200620 {
0570 compatible = "mediatek,mt8173-sysirq",
0571 "mediatek,mt6577-sysirq";
0572 interrupt-controller;
0573 #interrupt-cells = <3>;
0574 interrupt-parent = <&gic>;
0575 reg = <0 0x10200620 0 0x20>;
0576 };
0577
0578 iommu: iommu@10205000 {
0579 compatible = "mediatek,mt8173-m4u";
0580 reg = <0 0x10205000 0 0x1000>;
0581 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
0582 clocks = <&infracfg CLK_INFRA_M4U>;
0583 clock-names = "bclk";
0584 mediatek,infracfg = <&infracfg>;
0585 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
0586 <&larb3>, <&larb4>, <&larb5>;
0587 #iommu-cells = <1>;
0588 };
0589
0590 efuse: efuse@10206000 {
0591 compatible = "mediatek,mt8173-efuse";
0592 reg = <0 0x10206000 0 0x1000>;
0593 #address-cells = <1>;
0594 #size-cells = <1>;
0595 thermal_calibration: calib@528 {
0596 reg = <0x528 0xc>;
0597 };
0598 };
0599
0600 apmixedsys: clock-controller@10209000 {
0601 compatible = "mediatek,mt8173-apmixedsys";
0602 reg = <0 0x10209000 0 0x1000>;
0603 #clock-cells = <1>;
0604 };
0605
0606 hdmi_phy: hdmi-phy@10209100 {
0607 compatible = "mediatek,mt8173-hdmi-phy";
0608 reg = <0 0x10209100 0 0x24>;
0609 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
0610 clock-names = "pll_ref";
0611 clock-output-names = "hdmitx_dig_cts";
0612 mediatek,ibias = <0xa>;
0613 mediatek,ibias_up = <0x1c>;
0614 #clock-cells = <0>;
0615 #phy-cells = <0>;
0616 status = "disabled";
0617 };
0618
0619 gce: mailbox@10212000 {
0620 compatible = "mediatek,mt8173-gce";
0621 reg = <0 0x10212000 0 0x1000>;
0622 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
0623 clocks = <&infracfg CLK_INFRA_GCE>;
0624 clock-names = "gce";
0625 #mbox-cells = <2>;
0626 };
0627
0628 mipi_tx0: dsi-phy@10215000 {
0629 compatible = "mediatek,mt8173-mipi-tx";
0630 reg = <0 0x10215000 0 0x1000>;
0631 clocks = <&clk26m>;
0632 clock-output-names = "mipi_tx0_pll";
0633 #clock-cells = <0>;
0634 #phy-cells = <0>;
0635 status = "disabled";
0636 };
0637
0638 mipi_tx1: dsi-phy@10216000 {
0639 compatible = "mediatek,mt8173-mipi-tx";
0640 reg = <0 0x10216000 0 0x1000>;
0641 clocks = <&clk26m>;
0642 clock-output-names = "mipi_tx1_pll";
0643 #clock-cells = <0>;
0644 #phy-cells = <0>;
0645 status = "disabled";
0646 };
0647
0648 gic: interrupt-controller@10221000 {
0649 compatible = "arm,gic-400";
0650 #interrupt-cells = <3>;
0651 interrupt-parent = <&gic>;
0652 interrupt-controller;
0653 reg = <0 0x10221000 0 0x1000>,
0654 <0 0x10222000 0 0x2000>,
0655 <0 0x10224000 0 0x2000>,
0656 <0 0x10226000 0 0x2000>;
0657 interrupts = <GIC_PPI 9
0658 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0659 };
0660
0661 auxadc: auxadc@11001000 {
0662 compatible = "mediatek,mt8173-auxadc";
0663 reg = <0 0x11001000 0 0x1000>;
0664 clocks = <&pericfg CLK_PERI_AUXADC>;
0665 clock-names = "main";
0666 #io-channel-cells = <1>;
0667 };
0668
0669 uart0: serial@11002000 {
0670 compatible = "mediatek,mt8173-uart",
0671 "mediatek,mt6577-uart";
0672 reg = <0 0x11002000 0 0x400>;
0673 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
0674 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
0675 clock-names = "baud", "bus";
0676 status = "disabled";
0677 };
0678
0679 uart1: serial@11003000 {
0680 compatible = "mediatek,mt8173-uart",
0681 "mediatek,mt6577-uart";
0682 reg = <0 0x11003000 0 0x400>;
0683 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
0684 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
0685 clock-names = "baud", "bus";
0686 status = "disabled";
0687 };
0688
0689 uart2: serial@11004000 {
0690 compatible = "mediatek,mt8173-uart",
0691 "mediatek,mt6577-uart";
0692 reg = <0 0x11004000 0 0x400>;
0693 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
0694 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
0695 clock-names = "baud", "bus";
0696 status = "disabled";
0697 };
0698
0699 uart3: serial@11005000 {
0700 compatible = "mediatek,mt8173-uart",
0701 "mediatek,mt6577-uart";
0702 reg = <0 0x11005000 0 0x400>;
0703 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
0704 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
0705 clock-names = "baud", "bus";
0706 status = "disabled";
0707 };
0708
0709 i2c0: i2c@11007000 {
0710 compatible = "mediatek,mt8173-i2c";
0711 reg = <0 0x11007000 0 0x70>,
0712 <0 0x11000100 0 0x80>;
0713 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
0714 clock-div = <16>;
0715 clocks = <&pericfg CLK_PERI_I2C0>,
0716 <&pericfg CLK_PERI_AP_DMA>;
0717 clock-names = "main", "dma";
0718 pinctrl-names = "default";
0719 pinctrl-0 = <&i2c0_pins_a>;
0720 #address-cells = <1>;
0721 #size-cells = <0>;
0722 status = "disabled";
0723 };
0724
0725 i2c1: i2c@11008000 {
0726 compatible = "mediatek,mt8173-i2c";
0727 reg = <0 0x11008000 0 0x70>,
0728 <0 0x11000180 0 0x80>;
0729 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
0730 clock-div = <16>;
0731 clocks = <&pericfg CLK_PERI_I2C1>,
0732 <&pericfg CLK_PERI_AP_DMA>;
0733 clock-names = "main", "dma";
0734 pinctrl-names = "default";
0735 pinctrl-0 = <&i2c1_pins_a>;
0736 #address-cells = <1>;
0737 #size-cells = <0>;
0738 status = "disabled";
0739 };
0740
0741 i2c2: i2c@11009000 {
0742 compatible = "mediatek,mt8173-i2c";
0743 reg = <0 0x11009000 0 0x70>,
0744 <0 0x11000200 0 0x80>;
0745 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
0746 clock-div = <16>;
0747 clocks = <&pericfg CLK_PERI_I2C2>,
0748 <&pericfg CLK_PERI_AP_DMA>;
0749 clock-names = "main", "dma";
0750 pinctrl-names = "default";
0751 pinctrl-0 = <&i2c2_pins_a>;
0752 #address-cells = <1>;
0753 #size-cells = <0>;
0754 status = "disabled";
0755 };
0756
0757 spi: spi@1100a000 {
0758 compatible = "mediatek,mt8173-spi";
0759 #address-cells = <1>;
0760 #size-cells = <0>;
0761 reg = <0 0x1100a000 0 0x1000>;
0762 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
0763 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0764 <&topckgen CLK_TOP_SPI_SEL>,
0765 <&pericfg CLK_PERI_SPI0>;
0766 clock-names = "parent-clk", "sel-clk", "spi-clk";
0767 status = "disabled";
0768 };
0769
0770 thermal: thermal@1100b000 {
0771 #thermal-sensor-cells = <0>;
0772 compatible = "mediatek,mt8173-thermal";
0773 reg = <0 0x1100b000 0 0x1000>;
0774 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
0775 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
0776 clock-names = "therm", "auxadc";
0777 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
0778 mediatek,auxadc = <&auxadc>;
0779 mediatek,apmixedsys = <&apmixedsys>;
0780 nvmem-cells = <&thermal_calibration>;
0781 nvmem-cell-names = "calibration-data";
0782 };
0783
0784 nor_flash: spi@1100d000 {
0785 compatible = "mediatek,mt8173-nor";
0786 reg = <0 0x1100d000 0 0xe0>;
0787 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
0788 assigned-clock-parents = <&clk26m>;
0789 clocks = <&pericfg CLK_PERI_SPI>,
0790 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
0791 <&pericfg CLK_PERI_NFI>;
0792 clock-names = "spi", "sf", "axi";
0793 #address-cells = <1>;
0794 #size-cells = <0>;
0795 status = "disabled";
0796 };
0797
0798 i2c3: i2c@11010000 {
0799 compatible = "mediatek,mt8173-i2c";
0800 reg = <0 0x11010000 0 0x70>,
0801 <0 0x11000280 0 0x80>;
0802 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
0803 clock-div = <16>;
0804 clocks = <&pericfg CLK_PERI_I2C3>,
0805 <&pericfg CLK_PERI_AP_DMA>;
0806 clock-names = "main", "dma";
0807 pinctrl-names = "default";
0808 pinctrl-0 = <&i2c3_pins_a>;
0809 #address-cells = <1>;
0810 #size-cells = <0>;
0811 status = "disabled";
0812 };
0813
0814 i2c4: i2c@11011000 {
0815 compatible = "mediatek,mt8173-i2c";
0816 reg = <0 0x11011000 0 0x70>,
0817 <0 0x11000300 0 0x80>;
0818 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
0819 clock-div = <16>;
0820 clocks = <&pericfg CLK_PERI_I2C4>,
0821 <&pericfg CLK_PERI_AP_DMA>;
0822 clock-names = "main", "dma";
0823 pinctrl-names = "default";
0824 pinctrl-0 = <&i2c4_pins_a>;
0825 #address-cells = <1>;
0826 #size-cells = <0>;
0827 status = "disabled";
0828 };
0829
0830 hdmiddc0: i2c@11012000 {
0831 compatible = "mediatek,mt8173-hdmi-ddc";
0832 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
0833 reg = <0 0x11012000 0 0x1C>;
0834 clocks = <&pericfg CLK_PERI_I2C5>;
0835 clock-names = "ddc-i2c";
0836 };
0837
0838 i2c6: i2c@11013000 {
0839 compatible = "mediatek,mt8173-i2c";
0840 reg = <0 0x11013000 0 0x70>,
0841 <0 0x11000080 0 0x80>;
0842 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
0843 clock-div = <16>;
0844 clocks = <&pericfg CLK_PERI_I2C6>,
0845 <&pericfg CLK_PERI_AP_DMA>;
0846 clock-names = "main", "dma";
0847 pinctrl-names = "default";
0848 pinctrl-0 = <&i2c6_pins_a>;
0849 #address-cells = <1>;
0850 #size-cells = <0>;
0851 status = "disabled";
0852 };
0853
0854 afe: audio-controller@11220000 {
0855 compatible = "mediatek,mt8173-afe-pcm";
0856 reg = <0 0x11220000 0 0x1000>;
0857 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
0858 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
0859 clocks = <&infracfg CLK_INFRA_AUDIO>,
0860 <&topckgen CLK_TOP_AUDIO_SEL>,
0861 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
0862 <&topckgen CLK_TOP_APLL1_DIV0>,
0863 <&topckgen CLK_TOP_APLL2_DIV0>,
0864 <&topckgen CLK_TOP_I2S0_M_SEL>,
0865 <&topckgen CLK_TOP_I2S1_M_SEL>,
0866 <&topckgen CLK_TOP_I2S2_M_SEL>,
0867 <&topckgen CLK_TOP_I2S3_M_SEL>,
0868 <&topckgen CLK_TOP_I2S3_B_SEL>;
0869 clock-names = "infra_sys_audio_clk",
0870 "top_pdn_audio",
0871 "top_pdn_aud_intbus",
0872 "bck0",
0873 "bck1",
0874 "i2s0_m",
0875 "i2s1_m",
0876 "i2s2_m",
0877 "i2s3_m",
0878 "i2s3_b";
0879 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
0880 <&topckgen CLK_TOP_AUD_2_SEL>;
0881 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
0882 <&topckgen CLK_TOP_APLL2>;
0883 };
0884
0885 mmc0: mmc@11230000 {
0886 compatible = "mediatek,mt8173-mmc";
0887 reg = <0 0x11230000 0 0x1000>;
0888 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
0889 clocks = <&pericfg CLK_PERI_MSDC30_0>,
0890 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
0891 clock-names = "source", "hclk";
0892 status = "disabled";
0893 };
0894
0895 mmc1: mmc@11240000 {
0896 compatible = "mediatek,mt8173-mmc";
0897 reg = <0 0x11240000 0 0x1000>;
0898 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
0899 clocks = <&pericfg CLK_PERI_MSDC30_1>,
0900 <&topckgen CLK_TOP_AXI_SEL>;
0901 clock-names = "source", "hclk";
0902 status = "disabled";
0903 };
0904
0905 mmc2: mmc@11250000 {
0906 compatible = "mediatek,mt8173-mmc";
0907 reg = <0 0x11250000 0 0x1000>;
0908 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
0909 clocks = <&pericfg CLK_PERI_MSDC30_2>,
0910 <&topckgen CLK_TOP_AXI_SEL>;
0911 clock-names = "source", "hclk";
0912 status = "disabled";
0913 };
0914
0915 mmc3: mmc@11260000 {
0916 compatible = "mediatek,mt8173-mmc";
0917 reg = <0 0x11260000 0 0x1000>;
0918 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
0919 clocks = <&pericfg CLK_PERI_MSDC30_3>,
0920 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
0921 clock-names = "source", "hclk";
0922 status = "disabled";
0923 };
0924
0925 ssusb: usb@11271000 {
0926 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
0927 reg = <0 0x11271000 0 0x3000>,
0928 <0 0x11280700 0 0x0100>;
0929 reg-names = "mac", "ippc";
0930 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
0931 phys = <&u2port0 PHY_TYPE_USB2>,
0932 <&u3port0 PHY_TYPE_USB3>,
0933 <&u2port1 PHY_TYPE_USB2>;
0934 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
0935 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
0936 clock-names = "sys_ck", "ref_ck";
0937 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
0938 #address-cells = <2>;
0939 #size-cells = <2>;
0940 ranges;
0941 status = "disabled";
0942
0943 usb_host: usb@11270000 {
0944 compatible = "mediatek,mt8173-xhci",
0945 "mediatek,mtk-xhci";
0946 reg = <0 0x11270000 0 0x1000>;
0947 reg-names = "mac";
0948 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
0949 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
0950 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
0951 clock-names = "sys_ck", "ref_ck";
0952 status = "disabled";
0953 };
0954 };
0955
0956 u3phy: t-phy@11290000 {
0957 compatible = "mediatek,mt8173-u3phy";
0958 reg = <0 0x11290000 0 0x800>;
0959 #address-cells = <2>;
0960 #size-cells = <2>;
0961 ranges;
0962 status = "okay";
0963
0964 u2port0: usb-phy@11290800 {
0965 reg = <0 0x11290800 0 0x100>;
0966 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
0967 clock-names = "ref";
0968 #phy-cells = <1>;
0969 status = "okay";
0970 };
0971
0972 u3port0: usb-phy@11290900 {
0973 reg = <0 0x11290900 0 0x700>;
0974 clocks = <&clk26m>;
0975 clock-names = "ref";
0976 #phy-cells = <1>;
0977 status = "okay";
0978 };
0979
0980 u2port1: usb-phy@11291000 {
0981 reg = <0 0x11291000 0 0x100>;
0982 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
0983 clock-names = "ref";
0984 #phy-cells = <1>;
0985 status = "okay";
0986 };
0987 };
0988
0989 mmsys: syscon@14000000 {
0990 compatible = "mediatek,mt8173-mmsys", "syscon";
0991 reg = <0 0x14000000 0 0x1000>;
0992 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
0993 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
0994 assigned-clock-rates = <400000000>;
0995 #clock-cells = <1>;
0996 #reset-cells = <1>;
0997 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
0998 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
0999 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1000 };
1001
1002 mdp_rdma0: rdma@14001000 {
1003 compatible = "mediatek,mt8173-mdp-rdma",
1004 "mediatek,mt8173-mdp";
1005 reg = <0 0x14001000 0 0x1000>;
1006 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1007 <&mmsys CLK_MM_MUTEX_32K>;
1008 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1009 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1010 mediatek,vpu = <&vpu>;
1011 };
1012
1013 mdp_rdma1: rdma@14002000 {
1014 compatible = "mediatek,mt8173-mdp-rdma";
1015 reg = <0 0x14002000 0 0x1000>;
1016 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1017 <&mmsys CLK_MM_MUTEX_32K>;
1018 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1019 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1020 };
1021
1022 mdp_rsz0: rsz@14003000 {
1023 compatible = "mediatek,mt8173-mdp-rsz";
1024 reg = <0 0x14003000 0 0x1000>;
1025 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1026 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1027 };
1028
1029 mdp_rsz1: rsz@14004000 {
1030 compatible = "mediatek,mt8173-mdp-rsz";
1031 reg = <0 0x14004000 0 0x1000>;
1032 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1033 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1034 };
1035
1036 mdp_rsz2: rsz@14005000 {
1037 compatible = "mediatek,mt8173-mdp-rsz";
1038 reg = <0 0x14005000 0 0x1000>;
1039 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1040 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1041 };
1042
1043 mdp_wdma0: wdma@14006000 {
1044 compatible = "mediatek,mt8173-mdp-wdma";
1045 reg = <0 0x14006000 0 0x1000>;
1046 clocks = <&mmsys CLK_MM_MDP_WDMA>;
1047 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1048 iommus = <&iommu M4U_PORT_MDP_WDMA>;
1049 };
1050
1051 mdp_wrot0: wrot@14007000 {
1052 compatible = "mediatek,mt8173-mdp-wrot";
1053 reg = <0 0x14007000 0 0x1000>;
1054 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1055 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1056 iommus = <&iommu M4U_PORT_MDP_WROT0>;
1057 };
1058
1059 mdp_wrot1: wrot@14008000 {
1060 compatible = "mediatek,mt8173-mdp-wrot";
1061 reg = <0 0x14008000 0 0x1000>;
1062 clocks = <&mmsys CLK_MM_MDP_WROT1>;
1063 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1064 iommus = <&iommu M4U_PORT_MDP_WROT1>;
1065 };
1066
1067 ovl0: ovl@1400c000 {
1068 compatible = "mediatek,mt8173-disp-ovl";
1069 reg = <0 0x1400c000 0 0x1000>;
1070 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1071 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1072 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1073 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1074 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1075 };
1076
1077 ovl1: ovl@1400d000 {
1078 compatible = "mediatek,mt8173-disp-ovl";
1079 reg = <0 0x1400d000 0 0x1000>;
1080 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1081 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1082 clocks = <&mmsys CLK_MM_DISP_OVL1>;
1083 iommus = <&iommu M4U_PORT_DISP_OVL1>;
1084 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1085 };
1086
1087 rdma0: rdma@1400e000 {
1088 compatible = "mediatek,mt8173-disp-rdma";
1089 reg = <0 0x1400e000 0 0x1000>;
1090 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1091 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1092 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1093 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1094 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1095 };
1096
1097 rdma1: rdma@1400f000 {
1098 compatible = "mediatek,mt8173-disp-rdma";
1099 reg = <0 0x1400f000 0 0x1000>;
1100 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1101 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1102 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1103 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1104 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1105 };
1106
1107 rdma2: rdma@14010000 {
1108 compatible = "mediatek,mt8173-disp-rdma";
1109 reg = <0 0x14010000 0 0x1000>;
1110 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1111 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1112 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1113 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1114 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1115 };
1116
1117 wdma0: wdma@14011000 {
1118 compatible = "mediatek,mt8173-disp-wdma";
1119 reg = <0 0x14011000 0 0x1000>;
1120 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1121 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1122 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1123 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1124 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1125 };
1126
1127 wdma1: wdma@14012000 {
1128 compatible = "mediatek,mt8173-disp-wdma";
1129 reg = <0 0x14012000 0 0x1000>;
1130 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1131 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1132 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1133 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1134 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1135 };
1136
1137 color0: color@14013000 {
1138 compatible = "mediatek,mt8173-disp-color";
1139 reg = <0 0x14013000 0 0x1000>;
1140 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1141 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1142 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1143 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1144 };
1145
1146 color1: color@14014000 {
1147 compatible = "mediatek,mt8173-disp-color";
1148 reg = <0 0x14014000 0 0x1000>;
1149 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1150 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1151 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1152 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1153 };
1154
1155 aal@14015000 {
1156 compatible = "mediatek,mt8173-disp-aal";
1157 reg = <0 0x14015000 0 0x1000>;
1158 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1159 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1160 clocks = <&mmsys CLK_MM_DISP_AAL>;
1161 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1162 };
1163
1164 gamma@14016000 {
1165 compatible = "mediatek,mt8173-disp-gamma";
1166 reg = <0 0x14016000 0 0x1000>;
1167 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1168 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1169 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1170 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1171 };
1172
1173 merge@14017000 {
1174 compatible = "mediatek,mt8173-disp-merge";
1175 reg = <0 0x14017000 0 0x1000>;
1176 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1177 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1178 };
1179
1180 split0: split@14018000 {
1181 compatible = "mediatek,mt8173-disp-split";
1182 reg = <0 0x14018000 0 0x1000>;
1183 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1184 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1185 };
1186
1187 split1: split@14019000 {
1188 compatible = "mediatek,mt8173-disp-split";
1189 reg = <0 0x14019000 0 0x1000>;
1190 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1191 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1192 };
1193
1194 ufoe@1401a000 {
1195 compatible = "mediatek,mt8173-disp-ufoe";
1196 reg = <0 0x1401a000 0 0x1000>;
1197 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1198 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1199 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1200 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1201 };
1202
1203 dsi0: dsi@1401b000 {
1204 compatible = "mediatek,mt8173-dsi";
1205 reg = <0 0x1401b000 0 0x1000>;
1206 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1207 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1208 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1209 <&mmsys CLK_MM_DSI0_DIGITAL>,
1210 <&mipi_tx0>;
1211 clock-names = "engine", "digital", "hs";
1212 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1213 phys = <&mipi_tx0>;
1214 phy-names = "dphy";
1215 status = "disabled";
1216 };
1217
1218 dsi1: dsi@1401c000 {
1219 compatible = "mediatek,mt8173-dsi";
1220 reg = <0 0x1401c000 0 0x1000>;
1221 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1222 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1223 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1224 <&mmsys CLK_MM_DSI1_DIGITAL>,
1225 <&mipi_tx1>;
1226 clock-names = "engine", "digital", "hs";
1227 phys = <&mipi_tx1>;
1228 phy-names = "dphy";
1229 status = "disabled";
1230 };
1231
1232 dpi0: dpi@1401d000 {
1233 compatible = "mediatek,mt8173-dpi";
1234 reg = <0 0x1401d000 0 0x1000>;
1235 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1236 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1237 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1238 <&mmsys CLK_MM_DPI_ENGINE>,
1239 <&apmixedsys CLK_APMIXED_TVDPLL>;
1240 clock-names = "pixel", "engine", "pll";
1241 status = "disabled";
1242
1243 port {
1244 dpi0_out: endpoint {
1245 remote-endpoint = <&hdmi0_in>;
1246 };
1247 };
1248 };
1249
1250 pwm0: pwm@1401e000 {
1251 compatible = "mediatek,mt8173-disp-pwm",
1252 "mediatek,mt6595-disp-pwm";
1253 reg = <0 0x1401e000 0 0x1000>;
1254 #pwm-cells = <2>;
1255 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1256 <&mmsys CLK_MM_DISP_PWM0MM>;
1257 clock-names = "main", "mm";
1258 status = "disabled";
1259 };
1260
1261 pwm1: pwm@1401f000 {
1262 compatible = "mediatek,mt8173-disp-pwm",
1263 "mediatek,mt6595-disp-pwm";
1264 reg = <0 0x1401f000 0 0x1000>;
1265 #pwm-cells = <2>;
1266 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1267 <&mmsys CLK_MM_DISP_PWM1MM>;
1268 clock-names = "main", "mm";
1269 status = "disabled";
1270 };
1271
1272 mutex: mutex@14020000 {
1273 compatible = "mediatek,mt8173-disp-mutex";
1274 reg = <0 0x14020000 0 0x1000>;
1275 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1276 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1277 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1278 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1279 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1280 <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
1281 };
1282
1283 larb0: larb@14021000 {
1284 compatible = "mediatek,mt8173-smi-larb";
1285 reg = <0 0x14021000 0 0x1000>;
1286 mediatek,smi = <&smi_common>;
1287 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1288 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1289 <&mmsys CLK_MM_SMI_LARB0>;
1290 clock-names = "apb", "smi";
1291 };
1292
1293 smi_common: smi@14022000 {
1294 compatible = "mediatek,mt8173-smi-common";
1295 reg = <0 0x14022000 0 0x1000>;
1296 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1297 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1298 <&mmsys CLK_MM_SMI_COMMON>;
1299 clock-names = "apb", "smi";
1300 };
1301
1302 od@14023000 {
1303 compatible = "mediatek,mt8173-disp-od";
1304 reg = <0 0x14023000 0 0x1000>;
1305 clocks = <&mmsys CLK_MM_DISP_OD>;
1306 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1307 };
1308
1309 hdmi0: hdmi@14025000 {
1310 compatible = "mediatek,mt8173-hdmi";
1311 reg = <0 0x14025000 0 0x400>;
1312 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1313 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1314 <&mmsys CLK_MM_HDMI_PLLCK>,
1315 <&mmsys CLK_MM_HDMI_AUDIO>,
1316 <&mmsys CLK_MM_HDMI_SPDIF>;
1317 clock-names = "pixel", "pll", "bclk", "spdif";
1318 pinctrl-names = "default";
1319 pinctrl-0 = <&hdmi_pin>;
1320 phys = <&hdmi_phy>;
1321 phy-names = "hdmi";
1322 mediatek,syscon-hdmi = <&mmsys 0x900>;
1323 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1324 assigned-clock-parents = <&hdmi_phy>;
1325 status = "disabled";
1326
1327 ports {
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330
1331 port@0 {
1332 reg = <0>;
1333
1334 hdmi0_in: endpoint {
1335 remote-endpoint = <&dpi0_out>;
1336 };
1337 };
1338 };
1339 };
1340
1341 larb4: larb@14027000 {
1342 compatible = "mediatek,mt8173-smi-larb";
1343 reg = <0 0x14027000 0 0x1000>;
1344 mediatek,smi = <&smi_common>;
1345 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1346 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1347 <&mmsys CLK_MM_SMI_LARB4>;
1348 clock-names = "apb", "smi";
1349 };
1350
1351 imgsys: clock-controller@15000000 {
1352 compatible = "mediatek,mt8173-imgsys", "syscon";
1353 reg = <0 0x15000000 0 0x1000>;
1354 #clock-cells = <1>;
1355 };
1356
1357 larb2: larb@15001000 {
1358 compatible = "mediatek,mt8173-smi-larb";
1359 reg = <0 0x15001000 0 0x1000>;
1360 mediatek,smi = <&smi_common>;
1361 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1362 clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1363 <&imgsys CLK_IMG_LARB2_SMI>;
1364 clock-names = "apb", "smi";
1365 };
1366
1367 vdecsys: clock-controller@16000000 {
1368 compatible = "mediatek,mt8173-vdecsys", "syscon";
1369 reg = <0 0x16000000 0 0x1000>;
1370 #clock-cells = <1>;
1371 };
1372
1373 vcodec_dec: vcodec@16000000 {
1374 compatible = "mediatek,mt8173-vcodec-dec";
1375 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1376 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1377 <0 0x16021000 0 0x800>, /* VDEC_LD */
1378 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1379 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1380 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1381 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1382 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1383 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1384 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1385 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1386 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1387 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1388 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1389 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1390 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1391 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1392 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1393 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1394 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1395 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1396 mediatek,vpu = <&vpu>;
1397 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1398 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1399 <&topckgen CLK_TOP_UNIVPLL_D2>,
1400 <&topckgen CLK_TOP_CCI400_SEL>,
1401 <&topckgen CLK_TOP_VDEC_SEL>,
1402 <&topckgen CLK_TOP_VCODECPLL>,
1403 <&apmixedsys CLK_APMIXED_VENCPLL>,
1404 <&topckgen CLK_TOP_VENC_LT_SEL>,
1405 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1406 clock-names = "vcodecpll",
1407 "univpll_d2",
1408 "clk_cci400_sel",
1409 "vdec_sel",
1410 "vdecpll",
1411 "vencpll",
1412 "venc_lt_sel",
1413 "vdec_bus_clk_src";
1414 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1415 <&topckgen CLK_TOP_CCI400_SEL>,
1416 <&topckgen CLK_TOP_VDEC_SEL>,
1417 <&apmixedsys CLK_APMIXED_VCODECPLL>,
1418 <&apmixedsys CLK_APMIXED_VENCPLL>;
1419 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1420 <&topckgen CLK_TOP_UNIVPLL_D2>,
1421 <&topckgen CLK_TOP_VCODECPLL>;
1422 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1423 };
1424
1425 larb1: larb@16010000 {
1426 compatible = "mediatek,mt8173-smi-larb";
1427 reg = <0 0x16010000 0 0x1000>;
1428 mediatek,smi = <&smi_common>;
1429 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1430 clocks = <&vdecsys CLK_VDEC_CKEN>,
1431 <&vdecsys CLK_VDEC_LARB_CKEN>;
1432 clock-names = "apb", "smi";
1433 };
1434
1435 vencsys: clock-controller@18000000 {
1436 compatible = "mediatek,mt8173-vencsys", "syscon";
1437 reg = <0 0x18000000 0 0x1000>;
1438 #clock-cells = <1>;
1439 };
1440
1441 larb3: larb@18001000 {
1442 compatible = "mediatek,mt8173-smi-larb";
1443 reg = <0 0x18001000 0 0x1000>;
1444 mediatek,smi = <&smi_common>;
1445 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1446 clocks = <&vencsys CLK_VENC_CKE1>,
1447 <&vencsys CLK_VENC_CKE0>;
1448 clock-names = "apb", "smi";
1449 };
1450
1451 vcodec_enc_avc: vcodec@18002000 {
1452 compatible = "mediatek,mt8173-vcodec-enc";
1453 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1454 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1455 iommus = <&iommu M4U_PORT_VENC_RCPU>,
1456 <&iommu M4U_PORT_VENC_REC>,
1457 <&iommu M4U_PORT_VENC_BSDMA>,
1458 <&iommu M4U_PORT_VENC_SV_COMV>,
1459 <&iommu M4U_PORT_VENC_RD_COMV>,
1460 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1461 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1462 <&iommu M4U_PORT_VENC_REF_LUMA>,
1463 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1464 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1465 <&iommu M4U_PORT_VENC_NBM_WDMA>;
1466 mediatek,vpu = <&vpu>;
1467 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1468 clock-names = "venc_sel";
1469 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1470 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1471 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1472 };
1473
1474 jpegdec: jpegdec@18004000 {
1475 compatible = "mediatek,mt8173-jpgdec";
1476 reg = <0 0x18004000 0 0x1000>;
1477 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1478 clocks = <&vencsys CLK_VENC_CKE0>,
1479 <&vencsys CLK_VENC_CKE3>;
1480 clock-names = "jpgdec-smi",
1481 "jpgdec";
1482 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1483 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1484 <&iommu M4U_PORT_JPGDEC_BSDMA>;
1485 };
1486
1487 vencltsys: clock-controller@19000000 {
1488 compatible = "mediatek,mt8173-vencltsys", "syscon";
1489 reg = <0 0x19000000 0 0x1000>;
1490 #clock-cells = <1>;
1491 };
1492
1493 larb5: larb@19001000 {
1494 compatible = "mediatek,mt8173-smi-larb";
1495 reg = <0 0x19001000 0 0x1000>;
1496 mediatek,smi = <&smi_common>;
1497 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1498 clocks = <&vencltsys CLK_VENCLT_CKE1>,
1499 <&vencltsys CLK_VENCLT_CKE0>;
1500 clock-names = "apb", "smi";
1501 };
1502
1503 vcodec_enc_vp8: vcodec@19002000 {
1504 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1505 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1506 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1507 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
1508 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1509 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1510 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1511 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1512 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1513 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1514 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1515 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1516 mediatek,vpu = <&vpu>;
1517 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1518 clock-names = "venc_lt_sel";
1519 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1520 assigned-clock-parents =
1521 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1522 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1523 };
1524 };
1525 };
