0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2020 MediaTek Inc.
0004 * Copyright (c) 2020 BayLibre, SAS.
0005 * Author: Fabien Parent <fparent@baylibre.com>
0006 */
0007
0008 #include <dt-bindings/clock/mt8167-clk.h>
0009 #include <dt-bindings/memory/mt8167-larb-port.h>
0010 #include <dt-bindings/power/mt8167-power.h>
0011
0012 #include "mt8167-pinfunc.h"
0013
0014 #include "mt8516.dtsi"
0015
0016 / {
0017 compatible = "mediatek,mt8167";
0018
0019 soc {
0020 topckgen: topckgen@10000000 {
0021 compatible = "mediatek,mt8167-topckgen", "syscon";
0022 reg = <0 0x10000000 0 0x1000>;
0023 #clock-cells = <1>;
0024 };
0025
0026 infracfg: infracfg@10001000 {
0027 compatible = "mediatek,mt8167-infracfg", "syscon";
0028 reg = <0 0x10001000 0 0x1000>;
0029 #clock-cells = <1>;
0030 };
0031
0032 apmixedsys: apmixedsys@10018000 {
0033 compatible = "mediatek,mt8167-apmixedsys", "syscon";
0034 reg = <0 0x10018000 0 0x710>;
0035 #clock-cells = <1>;
0036 };
0037
0038 scpsys: syscon@10006000 {
0039 compatible = "syscon", "simple-mfd";
0040 reg = <0 0x10006000 0 0x1000>;
0041 #power-domain-cells = <1>;
0042
0043 spm: power-controller {
0044 compatible = "mediatek,mt8167-power-controller";
0045 #address-cells = <1>;
0046 #size-cells = <0>;
0047 #power-domain-cells = <1>;
0048
0049 /* power domains of the SoC */
0050 power-domain@MT8167_POWER_DOMAIN_MM {
0051 reg = <MT8167_POWER_DOMAIN_MM>;
0052 clocks = <&topckgen CLK_TOP_SMI_MM>;
0053 clock-names = "mm";
0054 #power-domain-cells = <0>;
0055 mediatek,infracfg = <&infracfg>;
0056 };
0057
0058 power-domain@MT8167_POWER_DOMAIN_VDEC {
0059 reg = <MT8167_POWER_DOMAIN_VDEC>;
0060 clocks = <&topckgen CLK_TOP_SMI_MM>,
0061 <&topckgen CLK_TOP_RG_VDEC>;
0062 clock-names = "mm", "vdec";
0063 #power-domain-cells = <0>;
0064 };
0065
0066 power-domain@MT8167_POWER_DOMAIN_ISP {
0067 reg = <MT8167_POWER_DOMAIN_ISP>;
0068 clocks = <&topckgen CLK_TOP_SMI_MM>;
0069 clock-names = "mm";
0070 #power-domain-cells = <0>;
0071 };
0072
0073 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
0074 reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
0075 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
0076 <&topckgen CLK_TOP_RG_SLOW_MFG>;
0077 clock-names = "axi_mfg", "mfg";
0078 #address-cells = <1>;
0079 #size-cells = <0>;
0080 #power-domain-cells = <1>;
0081 mediatek,infracfg = <&infracfg>;
0082
0083 power-domain@MT8167_POWER_DOMAIN_MFG_2D {
0084 reg = <MT8167_POWER_DOMAIN_MFG_2D>;
0085 #address-cells = <1>;
0086 #size-cells = <0>;
0087 #power-domain-cells = <1>;
0088
0089 power-domain@MT8167_POWER_DOMAIN_MFG {
0090 reg = <MT8167_POWER_DOMAIN_MFG>;
0091 #power-domain-cells = <0>;
0092 mediatek,infracfg = <&infracfg>;
0093 };
0094 };
0095 };
0096
0097 power-domain@MT8167_POWER_DOMAIN_CONN {
0098 reg = <MT8167_POWER_DOMAIN_CONN>;
0099 #power-domain-cells = <0>;
0100 mediatek,infracfg = <&infracfg>;
0101 };
0102 };
0103 };
0104
0105 imgsys: syscon@15000000 {
0106 compatible = "mediatek,mt8167-imgsys", "syscon";
0107 reg = <0 0x15000000 0 0x1000>;
0108 #clock-cells = <1>;
0109 };
0110
0111 vdecsys: syscon@16000000 {
0112 compatible = "mediatek,mt8167-vdecsys", "syscon";
0113 reg = <0 0x16000000 0 0x1000>;
0114 #clock-cells = <1>;
0115 };
0116
0117 pio: pinctrl@1000b000 {
0118 compatible = "mediatek,mt8167-pinctrl";
0119 reg = <0 0x1000b000 0 0x1000>;
0120 mediatek,pctl-regmap = <&syscfg_pctl>;
0121 pins-are-numbered;
0122 gpio-controller;
0123 #gpio-cells = <2>;
0124 interrupt-controller;
0125 #interrupt-cells = <2>;
0126 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0127 };
0128
0129 mmsys: mmsys@14000000 {
0130 compatible = "mediatek,mt8167-mmsys", "syscon";
0131 reg = <0 0x14000000 0 0x1000>;
0132 #clock-cells = <1>;
0133 };
0134
0135 smi_common: smi@14017000 {
0136 compatible = "mediatek,mt8167-smi-common";
0137 reg = <0 0x14017000 0 0x1000>;
0138 clocks = <&mmsys CLK_MM_SMI_COMMON>,
0139 <&mmsys CLK_MM_SMI_COMMON>;
0140 clock-names = "apb", "smi";
0141 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
0142 };
0143
0144 larb0: larb@14016000 {
0145 compatible = "mediatek,mt8167-smi-larb";
0146 reg = <0 0x14016000 0 0x1000>;
0147 mediatek,smi = <&smi_common>;
0148 clocks = <&mmsys CLK_MM_SMI_LARB0>,
0149 <&mmsys CLK_MM_SMI_LARB0>;
0150 clock-names = "apb", "smi";
0151 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
0152 };
0153
0154 larb1: larb@15001000 {
0155 compatible = "mediatek,mt8167-smi-larb";
0156 reg = <0 0x15001000 0 0x1000>;
0157 mediatek,smi = <&smi_common>;
0158 clocks = <&imgsys CLK_IMG_LARB1_SMI>,
0159 <&imgsys CLK_IMG_LARB1_SMI>;
0160 clock-names = "apb", "smi";
0161 power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
0162 };
0163
0164 larb2: larb@16010000 {
0165 compatible = "mediatek,mt8167-smi-larb";
0166 reg = <0 0x16010000 0 0x1000>;
0167 mediatek,smi = <&smi_common>;
0168 clocks = <&vdecsys CLK_VDEC_CKEN>,
0169 <&vdecsys CLK_VDEC_LARB1_CKEN>;
0170 clock-names = "apb", "smi";
0171 power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
0172 };
0173
0174 iommu: m4u@10203000 {
0175 compatible = "mediatek,mt8167-m4u";
0176 reg = <0 0x10203000 0 0x1000>;
0177 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
0178 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
0179 #iommu-cells = <1>;
0180 };
0181 };
0182 };
