0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2021 MediaTek Inc.
0004 * Author: Sam.Shih <sam.shih@mediatek.com>
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/mt7986-clk.h>
0010
0011 / {
0012 interrupt-parent = <&gic>;
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 clk40m: oscillator@0 {
0017 compatible = "fixed-clock";
0018 clock-frequency = <40000000>;
0019 #clock-cells = <0>;
0020 clock-output-names = "clkxtal";
0021 };
0022
0023 cpus {
0024 #address-cells = <1>;
0025 #size-cells = <0>;
0026 cpu0: cpu@0 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a53";
0029 enable-method = "psci";
0030 reg = <0x0>;
0031 #cooling-cells = <2>;
0032 };
0033
0034 cpu1: cpu@1 {
0035 device_type = "cpu";
0036 compatible = "arm,cortex-a53";
0037 enable-method = "psci";
0038 reg = <0x1>;
0039 #cooling-cells = <2>;
0040 };
0041
0042 cpu2: cpu@2 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a53";
0045 enable-method = "psci";
0046 reg = <0x2>;
0047 #cooling-cells = <2>;
0048 };
0049
0050 cpu3: cpu@3 {
0051 device_type = "cpu";
0052 enable-method = "psci";
0053 compatible = "arm,cortex-a53";
0054 reg = <0x3>;
0055 #cooling-cells = <2>;
0056 };
0057 };
0058
0059 psci {
0060 compatible = "arm,psci-0.2";
0061 method = "smc";
0062 };
0063
0064 reserved-memory {
0065 #address-cells = <2>;
0066 #size-cells = <2>;
0067 ranges;
0068 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
0069 secmon_reserved: secmon@43000000 {
0070 reg = <0 0x43000000 0 0x30000>;
0071 no-map;
0072 };
0073 };
0074
0075 timer {
0076 compatible = "arm,armv8-timer";
0077 interrupt-parent = <&gic>;
0078 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0079 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0080 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0081 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0082 };
0083
0084 soc {
0085 #address-cells = <2>;
0086 #size-cells = <2>;
0087 compatible = "simple-bus";
0088 ranges;
0089
0090 gic: interrupt-controller@c000000 {
0091 compatible = "arm,gic-v3";
0092 #interrupt-cells = <3>;
0093 interrupt-parent = <&gic>;
0094 interrupt-controller;
0095 reg = <0 0x0c000000 0 0x10000>, /* GICD */
0096 <0 0x0c080000 0 0x80000>, /* GICR */
0097 <0 0x0c400000 0 0x2000>, /* GICC */
0098 <0 0x0c410000 0 0x1000>, /* GICH */
0099 <0 0x0c420000 0 0x2000>; /* GICV */
0100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0101 };
0102
0103 infracfg: infracfg@10001000 {
0104 compatible = "mediatek,mt7986-infracfg", "syscon";
0105 reg = <0 0x10001000 0 0x1000>;
0106 #clock-cells = <1>;
0107 };
0108
0109 topckgen: topckgen@1001b000 {
0110 compatible = "mediatek,mt7986-topckgen", "syscon";
0111 reg = <0 0x1001B000 0 0x1000>;
0112 #clock-cells = <1>;
0113 };
0114
0115 watchdog: watchdog@1001c000 {
0116 compatible = "mediatek,mt7986-wdt",
0117 "mediatek,mt6589-wdt";
0118 reg = <0 0x1001c000 0 0x1000>;
0119 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0120 #reset-cells = <1>;
0121 status = "disabled";
0122 };
0123
0124 apmixedsys: apmixedsys@1001e000 {
0125 compatible = "mediatek,mt7986-apmixedsys";
0126 reg = <0 0x1001E000 0 0x1000>;
0127 #clock-cells = <1>;
0128 };
0129
0130 pio: pinctrl@1001f000 {
0131 compatible = "mediatek,mt7986a-pinctrl";
0132 reg = <0 0x1001f000 0 0x1000>,
0133 <0 0x11c30000 0 0x1000>,
0134 <0 0x11c40000 0 0x1000>,
0135 <0 0x11e20000 0 0x1000>,
0136 <0 0x11e30000 0 0x1000>,
0137 <0 0x11f00000 0 0x1000>,
0138 <0 0x11f10000 0 0x1000>,
0139 <0 0x1000b000 0 0x1000>;
0140 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
0141 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
0142 gpio-controller;
0143 #gpio-cells = <2>;
0144 gpio-ranges = <&pio 0 0 100>;
0145 interrupt-controller;
0146 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
0147 interrupt-parent = <&gic>;
0148 #interrupt-cells = <2>;
0149 };
0150
0151 sgmiisys0: syscon@10060000 {
0152 compatible = "mediatek,mt7986-sgmiisys_0",
0153 "syscon";
0154 reg = <0 0x10060000 0 0x1000>;
0155 #clock-cells = <1>;
0156 };
0157
0158 sgmiisys1: syscon@10070000 {
0159 compatible = "mediatek,mt7986-sgmiisys_1",
0160 "syscon";
0161 reg = <0 0x10070000 0 0x1000>;
0162 #clock-cells = <1>;
0163 };
0164
0165 trng: trng@1020f000 {
0166 compatible = "mediatek,mt7986-rng",
0167 "mediatek,mt7623-rng";
0168 reg = <0 0x1020f000 0 0x100>;
0169 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
0170 clock-names = "rng";
0171 status = "disabled";
0172 };
0173
0174 uart0: serial@11002000 {
0175 compatible = "mediatek,mt7986-uart",
0176 "mediatek,mt6577-uart";
0177 reg = <0 0x11002000 0 0x400>;
0178 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0179 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
0180 <&infracfg CLK_INFRA_UART0_CK>;
0181 clock-names = "baud", "bus";
0182 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
0183 <&infracfg CLK_INFRA_UART0_SEL>;
0184 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
0185 <&topckgen CLK_TOP_UART_SEL>;
0186 status = "disabled";
0187 };
0188
0189 uart1: serial@11003000 {
0190 compatible = "mediatek,mt7986-uart",
0191 "mediatek,mt6577-uart";
0192 reg = <0 0x11003000 0 0x400>;
0193 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0194 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
0195 <&infracfg CLK_INFRA_UART1_CK>;
0196 clock-names = "baud", "bus";
0197 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
0198 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
0199 status = "disabled";
0200 };
0201
0202 uart2: serial@11004000 {
0203 compatible = "mediatek,mt7986-uart",
0204 "mediatek,mt6577-uart";
0205 reg = <0 0x11004000 0 0x400>;
0206 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0207 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
0208 <&infracfg CLK_INFRA_UART2_CK>;
0209 clock-names = "baud", "bus";
0210 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
0211 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
0212 status = "disabled";
0213 };
0214
0215 ethsys: syscon@15000000 {
0216 #address-cells = <1>;
0217 #size-cells = <1>;
0218 compatible = "mediatek,mt7986-ethsys",
0219 "syscon";
0220 reg = <0 0x15000000 0 0x1000>;
0221 #clock-cells = <1>;
0222 #reset-cells = <1>;
0223 };
0224
0225 eth: ethernet@15100000 {
0226 compatible = "mediatek,mt7986-eth";
0227 reg = <0 0x15100000 0 0x80000>;
0228 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
0229 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
0230 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
0231 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
0232 clocks = <ðsys CLK_ETH_FE_EN>,
0233 <ðsys CLK_ETH_GP2_EN>,
0234 <ðsys CLK_ETH_GP1_EN>,
0235 <ðsys CLK_ETH_WOCPU1_EN>,
0236 <ðsys CLK_ETH_WOCPU0_EN>,
0237 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
0238 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
0239 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
0240 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
0241 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
0242 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
0243 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
0244 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
0245 <&topckgen CLK_TOP_NETSYS_SEL>,
0246 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
0247 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
0248 "sgmii_tx250m", "sgmii_rx250m",
0249 "sgmii_cdr_ref", "sgmii_cdr_fb",
0250 "sgmii2_tx250m", "sgmii2_rx250m",
0251 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
0252 "netsys0", "netsys1";
0253 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
0254 <&topckgen CLK_TOP_SGM_325M_SEL>;
0255 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
0256 <&apmixedsys CLK_APMIXED_SGMPLL>;
0257 mediatek,ethsys = <ðsys>;
0258 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
0259 #reset-cells = <1>;
0260 #address-cells = <1>;
0261 #size-cells = <0>;
0262 status = "disabled";
0263 };
0264 };
0265
0266 };
