0001 /*
0002 * Copyright (c) 2017 MediaTek Inc.
0003 * Author: Ming Huang <ming.huang@mediatek.com>
0004 * Sean Wang <sean.wang@mediatek.com>
0005 *
0006 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
0007 */
0008
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/clock/mt7622-clk.h>
0012 #include <dt-bindings/phy/phy.h>
0013 #include <dt-bindings/power/mt7622-power.h>
0014 #include <dt-bindings/reset/mt7622-reset.h>
0015 #include <dt-bindings/thermal/thermal.h>
0016
0017 / {
0018 compatible = "mediatek,mt7622";
0019 interrupt-parent = <&sysirq>;
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 cpu_opp_table: opp-table {
0024 compatible = "operating-points-v2";
0025 opp-shared;
0026 opp-300000000 {
0027 opp-hz = /bits/ 64 <30000000>;
0028 opp-microvolt = <950000>;
0029 };
0030
0031 opp-437500000 {
0032 opp-hz = /bits/ 64 <437500000>;
0033 opp-microvolt = <1000000>;
0034 };
0035
0036 opp-600000000 {
0037 opp-hz = /bits/ 64 <600000000>;
0038 opp-microvolt = <1050000>;
0039 };
0040
0041 opp-812500000 {
0042 opp-hz = /bits/ 64 <812500000>;
0043 opp-microvolt = <1100000>;
0044 };
0045
0046 opp-1025000000 {
0047 opp-hz = /bits/ 64 <1025000000>;
0048 opp-microvolt = <1150000>;
0049 };
0050
0051 opp-1137500000 {
0052 opp-hz = /bits/ 64 <1137500000>;
0053 opp-microvolt = <1200000>;
0054 };
0055
0056 opp-1262500000 {
0057 opp-hz = /bits/ 64 <1262500000>;
0058 opp-microvolt = <1250000>;
0059 };
0060
0061 opp-1350000000 {
0062 opp-hz = /bits/ 64 <1350000000>;
0063 opp-microvolt = <1310000>;
0064 };
0065 };
0066
0067 cpus {
0068 #address-cells = <2>;
0069 #size-cells = <0>;
0070
0071 cpu0: cpu@0 {
0072 device_type = "cpu";
0073 compatible = "arm,cortex-a53";
0074 reg = <0x0 0x0>;
0075 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
0076 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
0077 clock-names = "cpu", "intermediate";
0078 operating-points-v2 = <&cpu_opp_table>;
0079 #cooling-cells = <2>;
0080 enable-method = "psci";
0081 clock-frequency = <1300000000>;
0082 cci-control-port = <&cci_control2>;
0083 next-level-cache = <&L2>;
0084 };
0085
0086 cpu1: cpu@1 {
0087 device_type = "cpu";
0088 compatible = "arm,cortex-a53";
0089 reg = <0x0 0x1>;
0090 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
0091 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
0092 clock-names = "cpu", "intermediate";
0093 operating-points-v2 = <&cpu_opp_table>;
0094 #cooling-cells = <2>;
0095 enable-method = "psci";
0096 clock-frequency = <1300000000>;
0097 cci-control-port = <&cci_control2>;
0098 next-level-cache = <&L2>;
0099 };
0100
0101 L2: l2-cache {
0102 compatible = "cache";
0103 cache-level = <2>;
0104 };
0105 };
0106
0107 pwrap_clk: dummy40m {
0108 compatible = "fixed-clock";
0109 clock-frequency = <40000000>;
0110 #clock-cells = <0>;
0111 };
0112
0113 clk25m: oscillator {
0114 compatible = "fixed-clock";
0115 #clock-cells = <0>;
0116 clock-frequency = <25000000>;
0117 clock-output-names = "clkxtal";
0118 };
0119
0120 psci {
0121 compatible = "arm,psci-0.2";
0122 method = "smc";
0123 };
0124
0125 pmu {
0126 compatible = "arm,cortex-a53-pmu";
0127 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
0128 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
0129 interrupt-affinity = <&cpu0>, <&cpu1>;
0130 };
0131
0132 reserved-memory {
0133 #address-cells = <2>;
0134 #size-cells = <2>;
0135 ranges;
0136
0137 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
0138 secmon_reserved: secmon@43000000 {
0139 reg = <0 0x43000000 0 0x30000>;
0140 no-map;
0141 };
0142 };
0143
0144 thermal-zones {
0145 cpu_thermal: cpu-thermal {
0146 polling-delay-passive = <1000>;
0147 polling-delay = <1000>;
0148
0149 thermal-sensors = <&thermal 0>;
0150
0151 trips {
0152 cpu_passive: cpu-passive {
0153 temperature = <47000>;
0154 hysteresis = <2000>;
0155 type = "passive";
0156 };
0157
0158 cpu_active: cpu-active {
0159 temperature = <67000>;
0160 hysteresis = <2000>;
0161 type = "active";
0162 };
0163
0164 cpu_hot: cpu-hot {
0165 temperature = <87000>;
0166 hysteresis = <2000>;
0167 type = "hot";
0168 };
0169
0170 cpu-crit {
0171 temperature = <107000>;
0172 hysteresis = <2000>;
0173 type = "critical";
0174 };
0175 };
0176
0177 cooling-maps {
0178 map0 {
0179 trip = <&cpu_passive>;
0180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0181 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0182 };
0183
0184 map1 {
0185 trip = <&cpu_active>;
0186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0187 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0188 };
0189
0190 map2 {
0191 trip = <&cpu_hot>;
0192 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0193 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0194 };
0195 };
0196 };
0197 };
0198
0199 timer {
0200 compatible = "arm,armv8-timer";
0201 interrupt-parent = <&gic>;
0202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
0203 IRQ_TYPE_LEVEL_HIGH)>,
0204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
0205 IRQ_TYPE_LEVEL_HIGH)>,
0206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
0207 IRQ_TYPE_LEVEL_HIGH)>,
0208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
0209 IRQ_TYPE_LEVEL_HIGH)>;
0210 };
0211
0212 infracfg: infracfg@10000000 {
0213 compatible = "mediatek,mt7622-infracfg",
0214 "syscon";
0215 reg = <0 0x10000000 0 0x1000>;
0216 #clock-cells = <1>;
0217 #reset-cells = <1>;
0218 };
0219
0220 pwrap: pwrap@10001000 {
0221 compatible = "mediatek,mt7622-pwrap";
0222 reg = <0 0x10001000 0 0x250>;
0223 reg-names = "pwrap";
0224 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
0225 clock-names = "spi", "wrap";
0226 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
0227 reset-names = "pwrap";
0228 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
0229 status = "disabled";
0230 };
0231
0232 pericfg: pericfg@10002000 {
0233 compatible = "mediatek,mt7622-pericfg",
0234 "syscon";
0235 reg = <0 0x10002000 0 0x1000>;
0236 #clock-cells = <1>;
0237 #reset-cells = <1>;
0238 };
0239
0240 scpsys: power-controller@10006000 {
0241 compatible = "mediatek,mt7622-scpsys",
0242 "syscon";
0243 #power-domain-cells = <1>;
0244 reg = <0 0x10006000 0 0x1000>;
0245 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
0246 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
0247 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
0248 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
0249 infracfg = <&infracfg>;
0250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
0251 clock-names = "hif_sel";
0252 };
0253
0254 cir: cir@10009000 {
0255 compatible = "mediatek,mt7622-cir";
0256 reg = <0 0x10009000 0 0x1000>;
0257 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
0258 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
0259 <&topckgen CLK_TOP_AXI_SEL>;
0260 clock-names = "clk", "bus";
0261 status = "disabled";
0262 };
0263
0264 sysirq: interrupt-controller@10200620 {
0265 compatible = "mediatek,mt7622-sysirq",
0266 "mediatek,mt6577-sysirq";
0267 interrupt-controller;
0268 #interrupt-cells = <3>;
0269 interrupt-parent = <&gic>;
0270 reg = <0 0x10200620 0 0x20>;
0271 };
0272
0273 efuse: efuse@10206000 {
0274 compatible = "mediatek,mt7622-efuse",
0275 "mediatek,efuse";
0276 reg = <0 0x10206000 0 0x1000>;
0277 #address-cells = <1>;
0278 #size-cells = <1>;
0279
0280 thermal_calibration: calib@198 {
0281 reg = <0x198 0xc>;
0282 };
0283 };
0284
0285 apmixedsys: apmixedsys@10209000 {
0286 compatible = "mediatek,mt7622-apmixedsys",
0287 "syscon";
0288 reg = <0 0x10209000 0 0x1000>;
0289 #clock-cells = <1>;
0290 };
0291
0292 topckgen: topckgen@10210000 {
0293 compatible = "mediatek,mt7622-topckgen",
0294 "syscon";
0295 reg = <0 0x10210000 0 0x1000>;
0296 #clock-cells = <1>;
0297 };
0298
0299 rng: rng@1020f000 {
0300 compatible = "mediatek,mt7622-rng",
0301 "mediatek,mt7623-rng";
0302 reg = <0 0x1020f000 0 0x1000>;
0303 clocks = <&infracfg CLK_INFRA_TRNG>;
0304 clock-names = "rng";
0305 };
0306
0307 pio: pinctrl@10211000 {
0308 compatible = "mediatek,mt7622-pinctrl";
0309 reg = <0 0x10211000 0 0x1000>,
0310 <0 0x10005000 0 0x1000>;
0311 reg-names = "base", "eint";
0312 gpio-controller;
0313 #gpio-cells = <2>;
0314 gpio-ranges = <&pio 0 0 103>;
0315 interrupt-controller;
0316 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0317 interrupt-parent = <&gic>;
0318 #interrupt-cells = <2>;
0319 };
0320
0321 watchdog: watchdog@10212000 {
0322 compatible = "mediatek,mt7622-wdt",
0323 "mediatek,mt6589-wdt";
0324 reg = <0 0x10212000 0 0x800>;
0325 };
0326
0327 rtc: rtc@10212800 {
0328 compatible = "mediatek,mt7622-rtc",
0329 "mediatek,soc-rtc";
0330 reg = <0 0x10212800 0 0x200>;
0331 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
0332 clocks = <&topckgen CLK_TOP_RTC>;
0333 clock-names = "rtc";
0334 };
0335
0336 gic: interrupt-controller@10300000 {
0337 compatible = "arm,gic-400";
0338 interrupt-controller;
0339 #interrupt-cells = <3>;
0340 interrupt-parent = <&gic>;
0341 reg = <0 0x10310000 0 0x1000>,
0342 <0 0x10320000 0 0x1000>,
0343 <0 0x10340000 0 0x2000>,
0344 <0 0x10360000 0 0x2000>;
0345 };
0346
0347 cci: cci@10390000 {
0348 compatible = "arm,cci-400";
0349 #address-cells = <1>;
0350 #size-cells = <1>;
0351 reg = <0 0x10390000 0 0x1000>;
0352 ranges = <0 0 0x10390000 0x10000>;
0353
0354 cci_control0: slave-if@1000 {
0355 compatible = "arm,cci-400-ctrl-if";
0356 interface-type = "ace-lite";
0357 reg = <0x1000 0x1000>;
0358 };
0359
0360 cci_control1: slave-if@4000 {
0361 compatible = "arm,cci-400-ctrl-if";
0362 interface-type = "ace";
0363 reg = <0x4000 0x1000>;
0364 };
0365
0366 cci_control2: slave-if@5000 {
0367 compatible = "arm,cci-400-ctrl-if", "syscon";
0368 interface-type = "ace";
0369 reg = <0x5000 0x1000>;
0370 };
0371
0372 pmu@9000 {
0373 compatible = "arm,cci-400-pmu,r1";
0374 reg = <0x9000 0x5000>;
0375 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0376 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0377 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0378 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
0379 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0380 };
0381 };
0382
0383 auxadc: adc@11001000 {
0384 compatible = "mediatek,mt7622-auxadc";
0385 reg = <0 0x11001000 0 0x1000>;
0386 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
0387 clock-names = "main";
0388 #io-channel-cells = <1>;
0389 };
0390
0391 uart0: serial@11002000 {
0392 compatible = "mediatek,mt7622-uart",
0393 "mediatek,mt6577-uart";
0394 reg = <0 0x11002000 0 0x400>;
0395 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
0396 clocks = <&topckgen CLK_TOP_UART_SEL>,
0397 <&pericfg CLK_PERI_UART0_PD>;
0398 clock-names = "baud", "bus";
0399 status = "disabled";
0400 };
0401
0402 uart1: serial@11003000 {
0403 compatible = "mediatek,mt7622-uart",
0404 "mediatek,mt6577-uart";
0405 reg = <0 0x11003000 0 0x400>;
0406 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0407 clocks = <&topckgen CLK_TOP_UART_SEL>,
0408 <&pericfg CLK_PERI_UART1_PD>;
0409 clock-names = "baud", "bus";
0410 status = "disabled";
0411 };
0412
0413 uart2: serial@11004000 {
0414 compatible = "mediatek,mt7622-uart",
0415 "mediatek,mt6577-uart";
0416 reg = <0 0x11004000 0 0x400>;
0417 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
0418 clocks = <&topckgen CLK_TOP_UART_SEL>,
0419 <&pericfg CLK_PERI_UART2_PD>;
0420 clock-names = "baud", "bus";
0421 status = "disabled";
0422 };
0423
0424 uart3: serial@11005000 {
0425 compatible = "mediatek,mt7622-uart",
0426 "mediatek,mt6577-uart";
0427 reg = <0 0x11005000 0 0x400>;
0428 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
0429 clocks = <&topckgen CLK_TOP_UART_SEL>,
0430 <&pericfg CLK_PERI_UART3_PD>;
0431 clock-names = "baud", "bus";
0432 status = "disabled";
0433 };
0434
0435 pwm: pwm@11006000 {
0436 compatible = "mediatek,mt7622-pwm";
0437 reg = <0 0x11006000 0 0x1000>;
0438 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
0439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
0440 <&pericfg CLK_PERI_PWM_PD>,
0441 <&pericfg CLK_PERI_PWM1_PD>,
0442 <&pericfg CLK_PERI_PWM2_PD>,
0443 <&pericfg CLK_PERI_PWM3_PD>,
0444 <&pericfg CLK_PERI_PWM4_PD>,
0445 <&pericfg CLK_PERI_PWM5_PD>,
0446 <&pericfg CLK_PERI_PWM6_PD>;
0447 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
0448 "pwm5", "pwm6";
0449 status = "disabled";
0450 };
0451
0452 i2c0: i2c@11007000 {
0453 compatible = "mediatek,mt7622-i2c";
0454 reg = <0 0x11007000 0 0x90>,
0455 <0 0x11000100 0 0x80>;
0456 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
0457 clock-div = <16>;
0458 clocks = <&pericfg CLK_PERI_I2C0_PD>,
0459 <&pericfg CLK_PERI_AP_DMA_PD>;
0460 clock-names = "main", "dma";
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463 status = "disabled";
0464 };
0465
0466 i2c1: i2c@11008000 {
0467 compatible = "mediatek,mt7622-i2c";
0468 reg = <0 0x11008000 0 0x90>,
0469 <0 0x11000180 0 0x80>;
0470 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
0471 clock-div = <16>;
0472 clocks = <&pericfg CLK_PERI_I2C1_PD>,
0473 <&pericfg CLK_PERI_AP_DMA_PD>;
0474 clock-names = "main", "dma";
0475 #address-cells = <1>;
0476 #size-cells = <0>;
0477 status = "disabled";
0478 };
0479
0480 i2c2: i2c@11009000 {
0481 compatible = "mediatek,mt7622-i2c";
0482 reg = <0 0x11009000 0 0x90>,
0483 <0 0x11000200 0 0x80>;
0484 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
0485 clock-div = <16>;
0486 clocks = <&pericfg CLK_PERI_I2C2_PD>,
0487 <&pericfg CLK_PERI_AP_DMA_PD>;
0488 clock-names = "main", "dma";
0489 #address-cells = <1>;
0490 #size-cells = <0>;
0491 status = "disabled";
0492 };
0493
0494 spi0: spi@1100a000 {
0495 compatible = "mediatek,mt7622-spi";
0496 reg = <0 0x1100a000 0 0x100>;
0497 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
0498 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0499 <&topckgen CLK_TOP_SPI0_SEL>,
0500 <&pericfg CLK_PERI_SPI0_PD>;
0501 clock-names = "parent-clk", "sel-clk", "spi-clk";
0502 #address-cells = <1>;
0503 #size-cells = <0>;
0504 status = "disabled";
0505 };
0506
0507 thermal: thermal@1100b000 {
0508 #thermal-sensor-cells = <1>;
0509 compatible = "mediatek,mt7622-thermal";
0510 reg = <0 0x1100b000 0 0x1000>;
0511 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
0512 clocks = <&pericfg CLK_PERI_THERM_PD>,
0513 <&pericfg CLK_PERI_AUXADC_PD>;
0514 clock-names = "therm", "auxadc";
0515 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
0516 reset-names = "therm";
0517 mediatek,auxadc = <&auxadc>;
0518 mediatek,apmixedsys = <&apmixedsys>;
0519 nvmem-cells = <&thermal_calibration>;
0520 nvmem-cell-names = "calibration-data";
0521 };
0522
0523 btif: serial@1100c000 {
0524 compatible = "mediatek,mt7622-btif",
0525 "mediatek,mtk-btif";
0526 reg = <0 0x1100c000 0 0x1000>;
0527 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
0528 clocks = <&pericfg CLK_PERI_BTIF_PD>;
0529 clock-names = "main";
0530 reg-shift = <2>;
0531 reg-io-width = <4>;
0532 status = "disabled";
0533
0534 bluetooth {
0535 compatible = "mediatek,mt7622-bluetooth";
0536 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
0537 clocks = <&clk25m>;
0538 clock-names = "ref";
0539 };
0540 };
0541
0542 nandc: nfi@1100d000 {
0543 compatible = "mediatek,mt7622-nfc";
0544 reg = <0 0x1100D000 0 0x1000>;
0545 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
0546 clocks = <&pericfg CLK_PERI_NFI_PD>,
0547 <&pericfg CLK_PERI_SNFI_PD>;
0548 clock-names = "nfi_clk", "pad_clk";
0549 ecc-engine = <&bch>;
0550 #address-cells = <1>;
0551 #size-cells = <0>;
0552 status = "disabled";
0553 };
0554
0555 snfi: spi@1100d000 {
0556 compatible = "mediatek,mt7622-snand";
0557 reg = <0 0x1100d000 0 0x1000>;
0558 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
0559 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
0560 clock-names = "nfi_clk", "pad_clk";
0561 nand-ecc-engine = <&bch>;
0562 #address-cells = <1>;
0563 #size-cells = <0>;
0564 status = "disabled";
0565 };
0566
0567 bch: ecc@1100e000 {
0568 compatible = "mediatek,mt7622-ecc";
0569 reg = <0 0x1100e000 0 0x1000>;
0570 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
0571 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
0572 clock-names = "nfiecc_clk";
0573 status = "disabled";
0574 };
0575
0576 nor_flash: spi@11014000 {
0577 compatible = "mediatek,mt7622-nor",
0578 "mediatek,mt8173-nor";
0579 reg = <0 0x11014000 0 0xe0>;
0580 clocks = <&pericfg CLK_PERI_FLASH_PD>,
0581 <&topckgen CLK_TOP_FLASH_SEL>;
0582 clock-names = "spi", "sf";
0583 #address-cells = <1>;
0584 #size-cells = <0>;
0585 status = "disabled";
0586 };
0587
0588 spi1: spi@11016000 {
0589 compatible = "mediatek,mt7622-spi";
0590 reg = <0 0x11016000 0 0x100>;
0591 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
0592 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
0593 <&topckgen CLK_TOP_SPI1_SEL>,
0594 <&pericfg CLK_PERI_SPI1_PD>;
0595 clock-names = "parent-clk", "sel-clk", "spi-clk";
0596 #address-cells = <1>;
0597 #size-cells = <0>;
0598 status = "disabled";
0599 };
0600
0601 uart4: serial@11019000 {
0602 compatible = "mediatek,mt7622-uart",
0603 "mediatek,mt6577-uart";
0604 reg = <0 0x11019000 0 0x400>;
0605 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
0606 clocks = <&topckgen CLK_TOP_UART_SEL>,
0607 <&pericfg CLK_PERI_UART4_PD>;
0608 clock-names = "baud", "bus";
0609 status = "disabled";
0610 };
0611
0612 audsys: clock-controller@11220000 {
0613 compatible = "mediatek,mt7622-audsys", "syscon";
0614 reg = <0 0x11220000 0 0x2000>;
0615 #clock-cells = <1>;
0616
0617 afe: audio-controller {
0618 compatible = "mediatek,mt7622-audio";
0619 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
0620 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
0621 interrupt-names = "afe", "asys";
0622
0623 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
0624 <&topckgen CLK_TOP_AUD1_SEL>,
0625 <&topckgen CLK_TOP_AUD2_SEL>,
0626 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
0627 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
0628 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
0629 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
0630 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
0631 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
0632 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
0633 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
0634 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
0635 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
0636 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
0637 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
0638 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
0639 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
0640 <&audsys CLK_AUDIO_I2SO1>,
0641 <&audsys CLK_AUDIO_I2SO2>,
0642 <&audsys CLK_AUDIO_I2SO3>,
0643 <&audsys CLK_AUDIO_I2SO4>,
0644 <&audsys CLK_AUDIO_I2SIN1>,
0645 <&audsys CLK_AUDIO_I2SIN2>,
0646 <&audsys CLK_AUDIO_I2SIN3>,
0647 <&audsys CLK_AUDIO_I2SIN4>,
0648 <&audsys CLK_AUDIO_ASRCO1>,
0649 <&audsys CLK_AUDIO_ASRCO2>,
0650 <&audsys CLK_AUDIO_ASRCO3>,
0651 <&audsys CLK_AUDIO_ASRCO4>,
0652 <&audsys CLK_AUDIO_AFE>,
0653 <&audsys CLK_AUDIO_AFE_CONN>,
0654 <&audsys CLK_AUDIO_A1SYS>,
0655 <&audsys CLK_AUDIO_A2SYS>;
0656
0657 clock-names = "infra_sys_audio_clk",
0658 "top_audio_mux1_sel",
0659 "top_audio_mux2_sel",
0660 "top_audio_a1sys_hp",
0661 "top_audio_a2sys_hp",
0662 "i2s0_src_sel",
0663 "i2s1_src_sel",
0664 "i2s2_src_sel",
0665 "i2s3_src_sel",
0666 "i2s0_src_div",
0667 "i2s1_src_div",
0668 "i2s2_src_div",
0669 "i2s3_src_div",
0670 "i2s0_mclk_en",
0671 "i2s1_mclk_en",
0672 "i2s2_mclk_en",
0673 "i2s3_mclk_en",
0674 "i2so0_hop_ck",
0675 "i2so1_hop_ck",
0676 "i2so2_hop_ck",
0677 "i2so3_hop_ck",
0678 "i2si0_hop_ck",
0679 "i2si1_hop_ck",
0680 "i2si2_hop_ck",
0681 "i2si3_hop_ck",
0682 "asrc0_out_ck",
0683 "asrc1_out_ck",
0684 "asrc2_out_ck",
0685 "asrc3_out_ck",
0686 "audio_afe_pd",
0687 "audio_afe_conn_pd",
0688 "audio_a1sys_pd",
0689 "audio_a2sys_pd";
0690
0691 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
0692 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
0693 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
0694 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
0695 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
0696 <&topckgen CLK_TOP_AUD2PLL>;
0697 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
0698 };
0699 };
0700
0701 mmc0: mmc@11230000 {
0702 compatible = "mediatek,mt7622-mmc";
0703 reg = <0 0x11230000 0 0x1000>;
0704 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
0705 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
0706 <&topckgen CLK_TOP_MSDC50_0_SEL>;
0707 clock-names = "source", "hclk";
0708 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
0709 reset-names = "hrst";
0710 status = "disabled";
0711 };
0712
0713 mmc1: mmc@11240000 {
0714 compatible = "mediatek,mt7622-mmc";
0715 reg = <0 0x11240000 0 0x1000>;
0716 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
0717 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
0718 <&topckgen CLK_TOP_AXI_SEL>;
0719 clock-names = "source", "hclk";
0720 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
0721 reset-names = "hrst";
0722 status = "disabled";
0723 };
0724
0725 wmac: wmac@18000000 {
0726 compatible = "mediatek,mt7622-wmac";
0727 reg = <0 0x18000000 0 0x100000>;
0728 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
0729
0730 mediatek,infracfg = <&infracfg>;
0731 status = "disabled";
0732
0733 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
0734 };
0735
0736 ssusbsys: ssusbsys@1a000000 {
0737 compatible = "mediatek,mt7622-ssusbsys",
0738 "syscon";
0739 reg = <0 0x1a000000 0 0x1000>;
0740 #clock-cells = <1>;
0741 #reset-cells = <1>;
0742 };
0743
0744 ssusb: usb@1a0c0000 {
0745 compatible = "mediatek,mt7622-xhci",
0746 "mediatek,mtk-xhci";
0747 reg = <0 0x1a0c0000 0 0x01000>,
0748 <0 0x1a0c4700 0 0x0100>;
0749 reg-names = "mac", "ippc";
0750 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
0751 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
0752 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
0753 <&ssusbsys CLK_SSUSB_REF_EN>,
0754 <&ssusbsys CLK_SSUSB_MCU_EN>,
0755 <&ssusbsys CLK_SSUSB_DMA_EN>;
0756 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
0757 phys = <&u2port0 PHY_TYPE_USB2>,
0758 <&u3port0 PHY_TYPE_USB3>,
0759 <&u2port1 PHY_TYPE_USB2>;
0760
0761 status = "disabled";
0762 };
0763
0764 u3phy: t-phy@1a0c4000 {
0765 compatible = "mediatek,mt7622-tphy",
0766 "mediatek,generic-tphy-v1";
0767 reg = <0 0x1a0c4000 0 0x700>;
0768 #address-cells = <2>;
0769 #size-cells = <2>;
0770 ranges;
0771 status = "disabled";
0772
0773 u2port0: usb-phy@1a0c4800 {
0774 reg = <0 0x1a0c4800 0 0x0100>;
0775 #phy-cells = <1>;
0776 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
0777 clock-names = "ref";
0778 };
0779
0780 u3port0: usb-phy@1a0c4900 {
0781 reg = <0 0x1a0c4900 0 0x0700>;
0782 #phy-cells = <1>;
0783 clocks = <&clk25m>;
0784 clock-names = "ref";
0785 };
0786
0787 u2port1: usb-phy@1a0c5000 {
0788 reg = <0 0x1a0c5000 0 0x0100>;
0789 #phy-cells = <1>;
0790 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
0791 clock-names = "ref";
0792 };
0793 };
0794
0795 pciesys: pciesys@1a100800 {
0796 compatible = "mediatek,mt7622-pciesys",
0797 "syscon";
0798 reg = <0 0x1a100800 0 0x1000>;
0799 #clock-cells = <1>;
0800 #reset-cells = <1>;
0801 };
0802
0803 pciecfg: pciecfg@1a140000 {
0804 compatible = "mediatek,generic-pciecfg", "syscon";
0805 reg = <0 0x1a140000 0 0x1000>;
0806 };
0807
0808 pcie0: pcie@1a143000 {
0809 compatible = "mediatek,mt7622-pcie";
0810 device_type = "pci";
0811 reg = <0 0x1a143000 0 0x1000>;
0812 reg-names = "port0";
0813 linux,pci-domain = <0>;
0814 #address-cells = <3>;
0815 #size-cells = <2>;
0816 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
0817 interrupt-names = "pcie_irq";
0818 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
0819 <&pciesys CLK_PCIE_P0_AHB_EN>,
0820 <&pciesys CLK_PCIE_P0_AUX_EN>,
0821 <&pciesys CLK_PCIE_P0_AXI_EN>,
0822 <&pciesys CLK_PCIE_P0_OBFF_EN>,
0823 <&pciesys CLK_PCIE_P0_PIPE_EN>;
0824 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
0825 "axi_ck0", "obff_ck0", "pipe_ck0";
0826
0827 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
0828 bus-range = <0x00 0xff>;
0829 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
0830 status = "disabled";
0831
0832 #interrupt-cells = <1>;
0833 interrupt-map-mask = <0 0 0 7>;
0834 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0835 <0 0 0 2 &pcie_intc0 1>,
0836 <0 0 0 3 &pcie_intc0 2>,
0837 <0 0 0 4 &pcie_intc0 3>;
0838 pcie_intc0: interrupt-controller {
0839 interrupt-controller;
0840 #address-cells = <0>;
0841 #interrupt-cells = <1>;
0842 };
0843 };
0844
0845 pcie1: pcie@1a145000 {
0846 compatible = "mediatek,mt7622-pcie";
0847 device_type = "pci";
0848 reg = <0 0x1a145000 0 0x1000>;
0849 reg-names = "port1";
0850 linux,pci-domain = <1>;
0851 #address-cells = <3>;
0852 #size-cells = <2>;
0853 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
0854 interrupt-names = "pcie_irq";
0855 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
0856 /* designer has connect RC1 with p0_ahb clock */
0857 <&pciesys CLK_PCIE_P0_AHB_EN>,
0858 <&pciesys CLK_PCIE_P1_AUX_EN>,
0859 <&pciesys CLK_PCIE_P1_AXI_EN>,
0860 <&pciesys CLK_PCIE_P1_OBFF_EN>,
0861 <&pciesys CLK_PCIE_P1_PIPE_EN>;
0862 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
0863 "axi_ck1", "obff_ck1", "pipe_ck1";
0864
0865 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
0866 bus-range = <0x00 0xff>;
0867 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
0868 status = "disabled";
0869
0870 #interrupt-cells = <1>;
0871 interrupt-map-mask = <0 0 0 7>;
0872 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
0873 <0 0 0 2 &pcie_intc1 1>,
0874 <0 0 0 3 &pcie_intc1 2>,
0875 <0 0 0 4 &pcie_intc1 3>;
0876 pcie_intc1: interrupt-controller {
0877 interrupt-controller;
0878 #address-cells = <0>;
0879 #interrupt-cells = <1>;
0880 };
0881 };
0882
0883 sata: sata@1a200000 {
0884 compatible = "mediatek,mt7622-ahci",
0885 "mediatek,mtk-ahci";
0886 reg = <0 0x1a200000 0 0x1100>;
0887 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
0888 interrupt-names = "hostc";
0889 clocks = <&pciesys CLK_SATA_AHB_EN>,
0890 <&pciesys CLK_SATA_AXI_EN>,
0891 <&pciesys CLK_SATA_ASIC_EN>,
0892 <&pciesys CLK_SATA_RBC_EN>,
0893 <&pciesys CLK_SATA_PM_EN>;
0894 clock-names = "ahb", "axi", "asic", "rbc", "pm";
0895 phys = <&sata_port PHY_TYPE_SATA>;
0896 phy-names = "sata-phy";
0897 ports-implemented = <0x1>;
0898 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
0899 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
0900 <&pciesys MT7622_SATA_PHY_SW_RST>,
0901 <&pciesys MT7622_SATA_PHY_REG_RST>;
0902 reset-names = "axi", "sw", "reg";
0903 mediatek,phy-mode = <&pciesys>;
0904 status = "disabled";
0905 };
0906
0907 sata_phy: t-phy@1a243000 {
0908 compatible = "mediatek,mt7622-tphy",
0909 "mediatek,generic-tphy-v1";
0910 #address-cells = <2>;
0911 #size-cells = <2>;
0912 ranges;
0913 status = "disabled";
0914
0915 sata_port: sata-phy@1a243000 {
0916 reg = <0 0x1a243000 0 0x0100>;
0917 clocks = <&topckgen CLK_TOP_ETH_500M>;
0918 clock-names = "ref";
0919 #phy-cells = <1>;
0920 };
0921 };
0922
0923 hifsys: syscon@1af00000 {
0924 compatible = "mediatek,mt7622-hifsys", "syscon";
0925 reg = <0 0x1af00000 0 0x70>;
0926 };
0927
0928 ethsys: syscon@1b000000 {
0929 compatible = "mediatek,mt7622-ethsys",
0930 "syscon";
0931 reg = <0 0x1b000000 0 0x1000>;
0932 #clock-cells = <1>;
0933 #reset-cells = <1>;
0934 };
0935
0936 hsdma: dma-controller@1b007000 {
0937 compatible = "mediatek,mt7622-hsdma";
0938 reg = <0 0x1b007000 0 0x1000>;
0939 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
0940 clocks = <ðsys CLK_ETH_HSDMA_EN>;
0941 clock-names = "hsdma";
0942 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
0943 #dma-cells = <1>;
0944 dma-requests = <3>;
0945 };
0946
0947 pcie_mirror: pcie-mirror@10000400 {
0948 compatible = "mediatek,mt7622-pcie-mirror",
0949 "syscon";
0950 reg = <0 0x10000400 0 0x10>;
0951 };
0952
0953 wed0: wed@1020a000 {
0954 compatible = "mediatek,mt7622-wed",
0955 "syscon";
0956 reg = <0 0x1020a000 0 0x1000>;
0957 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
0958 };
0959
0960 wed1: wed@1020b000 {
0961 compatible = "mediatek,mt7622-wed",
0962 "syscon";
0963 reg = <0 0x1020b000 0 0x1000>;
0964 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
0965 };
0966
0967 eth: ethernet@1b100000 {
0968 compatible = "mediatek,mt7622-eth",
0969 "mediatek,mt2701-eth",
0970 "syscon";
0971 reg = <0 0x1b100000 0 0x20000>;
0972 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
0973 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
0974 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
0975 clocks = <&topckgen CLK_TOP_ETH_SEL>,
0976 <ðsys CLK_ETH_ESW_EN>,
0977 <ðsys CLK_ETH_GP0_EN>,
0978 <ðsys CLK_ETH_GP1_EN>,
0979 <ðsys CLK_ETH_GP2_EN>,
0980 <&sgmiisys CLK_SGMII_TX250M_EN>,
0981 <&sgmiisys CLK_SGMII_RX250M_EN>,
0982 <&sgmiisys CLK_SGMII_CDR_REF>,
0983 <&sgmiisys CLK_SGMII_CDR_FB>,
0984 <&topckgen CLK_TOP_SGMIIPLL>,
0985 <&apmixedsys CLK_APMIXED_ETH2PLL>;
0986 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
0987 "sgmii_tx250m", "sgmii_rx250m",
0988 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
0989 "eth2pll";
0990 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
0991 mediatek,ethsys = <ðsys>;
0992 mediatek,sgmiisys = <&sgmiisys>;
0993 cci-control-port = <&cci_control2>;
0994 mediatek,wed = <&wed0>, <&wed1>;
0995 mediatek,pcie-mirror = <&pcie_mirror>;
0996 mediatek,hifsys = <&hifsys>;
0997 dma-coherent;
0998 #address-cells = <1>;
0999 #size-cells = <0>;
1000 status = "disabled";
1001 };
1002
1003 sgmiisys: sgmiisys@1b128000 {
1004 compatible = "mediatek,mt7622-sgmiisys",
1005 "syscon";
1006 reg = <0 0x1b128000 0 0x3000>;
1007 #clock-cells = <1>;
1008 };
1009 };
