0001 /*
0002 * Copyright (c) 2017 MediaTek Inc.
0003 * Author: Ming Huang <ming.huang@mediatek.com>
0004 * Sean Wang <sean.wang@mediatek.com>
0005 *
0006 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
0007 */
0008
0009 /dts-v1/;
0010 #include <dt-bindings/input/input.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012
0013 #include "mt7622.dtsi"
0014 #include "mt6380.dtsi"
0015
0016 / {
0017 model = "MediaTek MT7622 RFB1 board";
0018 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
0019
0020 aliases {
0021 serial0 = &uart0;
0022 };
0023
0024 chosen {
0025 stdout-path = "serial0:115200n8";
0026 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
0027 };
0028
0029 cpus {
0030 cpu@0 {
0031 proc-supply = <&mt6380_vcpu_reg>;
0032 sram-supply = <&mt6380_vm_reg>;
0033 };
0034
0035 cpu@1 {
0036 proc-supply = <&mt6380_vcpu_reg>;
0037 sram-supply = <&mt6380_vm_reg>;
0038 };
0039 };
0040
0041 gpio-keys {
0042 compatible = "gpio-keys";
0043
0044 key-factory {
0045 label = "factory";
0046 linux,code = <BTN_0>;
0047 gpios = <&pio 0 0>;
0048 };
0049
0050 key-wps {
0051 label = "wps";
0052 linux,code = <KEY_WPS_BUTTON>;
0053 gpios = <&pio 102 0>;
0054 };
0055 };
0056
0057 memory {
0058 reg = <0 0x40000000 0 0x20000000>;
0059 };
0060
0061 reg_1p8v: regulator-1p8v {
0062 compatible = "regulator-fixed";
0063 regulator-name = "fixed-1.8V";
0064 regulator-min-microvolt = <1800000>;
0065 regulator-max-microvolt = <1800000>;
0066 regulator-always-on;
0067 };
0068
0069 reg_3p3v: regulator-3p3v {
0070 compatible = "regulator-fixed";
0071 regulator-name = "fixed-3.3V";
0072 regulator-min-microvolt = <3300000>;
0073 regulator-max-microvolt = <3300000>;
0074 regulator-boot-on;
0075 regulator-always-on;
0076 };
0077
0078 reg_5v: regulator-5v {
0079 compatible = "regulator-fixed";
0080 regulator-name = "fixed-5V";
0081 regulator-min-microvolt = <5000000>;
0082 regulator-max-microvolt = <5000000>;
0083 regulator-boot-on;
0084 regulator-always-on;
0085 };
0086 };
0087
0088 &bch {
0089 status = "disabled";
0090 };
0091
0092 &btif {
0093 status = "okay";
0094 };
0095
0096 &cir {
0097 pinctrl-names = "default";
0098 pinctrl-0 = <&irrx_pins>;
0099 status = "okay";
0100 };
0101
0102 ð {
0103 pinctrl-names = "default";
0104 pinctrl-0 = <ð_pins>;
0105 status = "okay";
0106
0107 gmac0: mac@0 {
0108 compatible = "mediatek,eth-mac";
0109 reg = <0>;
0110 phy-mode = "2500base-x";
0111
0112 fixed-link {
0113 speed = <2500>;
0114 full-duplex;
0115 pause;
0116 };
0117 };
0118
0119 mdio-bus {
0120 #address-cells = <1>;
0121 #size-cells = <0>;
0122
0123 switch@0 {
0124 compatible = "mediatek,mt7531";
0125 reg = <0>;
0126 reset-gpios = <&pio 54 0>;
0127
0128 ports {
0129 #address-cells = <1>;
0130 #size-cells = <0>;
0131
0132 port@0 {
0133 reg = <0>;
0134 label = "lan0";
0135 };
0136
0137 port@1 {
0138 reg = <1>;
0139 label = "lan1";
0140 };
0141
0142 port@2 {
0143 reg = <2>;
0144 label = "lan2";
0145 };
0146
0147 port@3 {
0148 reg = <3>;
0149 label = "lan3";
0150 };
0151
0152 port@4 {
0153 reg = <4>;
0154 label = "wan";
0155 };
0156
0157 port@6 {
0158 reg = <6>;
0159 label = "cpu";
0160 ethernet = <&gmac0>;
0161 phy-mode = "2500base-x";
0162
0163 fixed-link {
0164 speed = <2500>;
0165 full-duplex;
0166 pause;
0167 };
0168 };
0169 };
0170 };
0171
0172 };
0173 };
0174
0175 &i2c1 {
0176 pinctrl-names = "default";
0177 pinctrl-0 = <&i2c1_pins>;
0178 status = "okay";
0179 };
0180
0181 &i2c2 {
0182 pinctrl-names = "default";
0183 pinctrl-0 = <&i2c2_pins>;
0184 status = "okay";
0185 };
0186
0187 &mmc0 {
0188 pinctrl-names = "default", "state_uhs";
0189 pinctrl-0 = <&emmc_pins_default>;
0190 pinctrl-1 = <&emmc_pins_uhs>;
0191 status = "okay";
0192 bus-width = <8>;
0193 max-frequency = <50000000>;
0194 cap-mmc-highspeed;
0195 mmc-hs200-1_8v;
0196 vmmc-supply = <®_3p3v>;
0197 vqmmc-supply = <®_1p8v>;
0198 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
0199 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
0200 non-removable;
0201 };
0202
0203 &mmc1 {
0204 pinctrl-names = "default", "state_uhs";
0205 pinctrl-0 = <&sd0_pins_default>;
0206 pinctrl-1 = <&sd0_pins_uhs>;
0207 status = "okay";
0208 bus-width = <4>;
0209 max-frequency = <50000000>;
0210 cap-sd-highspeed;
0211 r_smpl = <1>;
0212 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
0213 vmmc-supply = <®_3p3v>;
0214 vqmmc-supply = <®_3p3v>;
0215 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
0216 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
0217 };
0218
0219 &nandc {
0220 pinctrl-names = "default";
0221 pinctrl-0 = <¶llel_nand_pins>;
0222 status = "disabled";
0223 };
0224
0225 &nor_flash {
0226 pinctrl-names = "default";
0227 pinctrl-0 = <&spi_nor_pins>;
0228 status = "disabled";
0229
0230 flash@0 {
0231 compatible = "jedec,spi-nor";
0232 reg = <0>;
0233 };
0234 };
0235
0236 &pcie0 {
0237 pinctrl-names = "default";
0238 pinctrl-0 = <&pcie0_pins>;
0239 status = "okay";
0240 };
0241
0242 &pio {
0243 /* eMMC is shared pin with parallel NAND */
0244 emmc_pins_default: emmc-pins-default {
0245 mux {
0246 function = "emmc", "emmc_rst";
0247 groups = "emmc";
0248 };
0249
0250 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
0251 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
0252 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
0253 */
0254 conf-cmd-dat {
0255 pins = "NDL0", "NDL1", "NDL2",
0256 "NDL3", "NDL4", "NDL5",
0257 "NDL6", "NDL7", "NRB";
0258 input-enable;
0259 bias-pull-up;
0260 };
0261
0262 conf-clk {
0263 pins = "NCLE";
0264 bias-pull-down;
0265 };
0266 };
0267
0268 emmc_pins_uhs: emmc-pins-uhs {
0269 mux {
0270 function = "emmc";
0271 groups = "emmc";
0272 };
0273
0274 conf-cmd-dat {
0275 pins = "NDL0", "NDL1", "NDL2",
0276 "NDL3", "NDL4", "NDL5",
0277 "NDL6", "NDL7", "NRB";
0278 input-enable;
0279 drive-strength = <4>;
0280 bias-pull-up;
0281 };
0282
0283 conf-clk {
0284 pins = "NCLE";
0285 drive-strength = <4>;
0286 bias-pull-down;
0287 };
0288 };
0289
0290 eth_pins: eth-pins {
0291 mux {
0292 function = "eth";
0293 groups = "mdc_mdio", "rgmii_via_gmac2";
0294 };
0295 };
0296
0297 i2c1_pins: i2c1-pins {
0298 mux {
0299 function = "i2c";
0300 groups = "i2c1_0";
0301 };
0302 };
0303
0304 i2c2_pins: i2c2-pins {
0305 mux {
0306 function = "i2c";
0307 groups = "i2c2_0";
0308 };
0309 };
0310
0311 i2s1_pins: i2s1-pins {
0312 mux {
0313 function = "i2s";
0314 groups = "i2s_out_mclk_bclk_ws",
0315 "i2s1_in_data",
0316 "i2s1_out_data";
0317 };
0318
0319 conf {
0320 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
0321 "I2S_WS", "I2S_MCLK";
0322 drive-strength = <12>;
0323 bias-pull-down;
0324 };
0325 };
0326
0327 irrx_pins: irrx-pins {
0328 mux {
0329 function = "ir";
0330 groups = "ir_1_rx";
0331 };
0332 };
0333
0334 irtx_pins: irtx-pins {
0335 mux {
0336 function = "ir";
0337 groups = "ir_1_tx";
0338 };
0339 };
0340
0341 /* Parallel nand is shared pin with eMMC */
0342 parallel_nand_pins: parallel-nand-pins {
0343 mux {
0344 function = "flash";
0345 groups = "par_nand";
0346 };
0347 };
0348
0349 pcie0_pins: pcie0-pins {
0350 mux {
0351 function = "pcie";
0352 groups = "pcie0_pad_perst",
0353 "pcie0_1_waken",
0354 "pcie0_1_clkreq";
0355 };
0356 };
0357
0358 pcie1_pins: pcie1-pins {
0359 mux {
0360 function = "pcie";
0361 groups = "pcie1_pad_perst",
0362 "pcie1_0_waken",
0363 "pcie1_0_clkreq";
0364 };
0365 };
0366
0367 pmic_bus_pins: pmic-bus-pins {
0368 mux {
0369 function = "pmic";
0370 groups = "pmic_bus";
0371 };
0372 };
0373
0374 pwm7_pins: pwm1-2-pins {
0375 mux {
0376 function = "pwm";
0377 groups = "pwm_ch7_2";
0378 };
0379 };
0380
0381 wled_pins: wled-pins {
0382 mux {
0383 function = "led";
0384 groups = "wled";
0385 };
0386 };
0387
0388 sd0_pins_default: sd0-pins-default {
0389 mux {
0390 function = "sd";
0391 groups = "sd_0";
0392 };
0393
0394 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
0395 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
0396 * DAT2, DAT3, CMD, CLK for SD respectively.
0397 */
0398 conf-cmd-data {
0399 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
0400 "I2S2_IN","I2S4_OUT";
0401 input-enable;
0402 drive-strength = <8>;
0403 bias-pull-up;
0404 };
0405 conf-clk {
0406 pins = "I2S3_OUT";
0407 drive-strength = <12>;
0408 bias-pull-down;
0409 };
0410 conf-cd {
0411 pins = "TXD3";
0412 bias-pull-up;
0413 };
0414 };
0415
0416 sd0_pins_uhs: sd0-pins-uhs {
0417 mux {
0418 function = "sd";
0419 groups = "sd_0";
0420 };
0421
0422 conf-cmd-data {
0423 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
0424 "I2S2_IN","I2S4_OUT";
0425 input-enable;
0426 bias-pull-up;
0427 };
0428
0429 conf-clk {
0430 pins = "I2S3_OUT";
0431 bias-pull-down;
0432 };
0433 };
0434
0435 /* Serial NAND is shared pin with SPI-NOR */
0436 serial_nand_pins: serial-nand-pins {
0437 mux {
0438 function = "flash";
0439 groups = "snfi";
0440 };
0441 };
0442
0443 spic0_pins: spic0-pins {
0444 mux {
0445 function = "spi";
0446 groups = "spic0_0";
0447 };
0448 };
0449
0450 spic1_pins: spic1-pins {
0451 mux {
0452 function = "spi";
0453 groups = "spic1_0";
0454 };
0455 };
0456
0457 /* SPI-NOR is shared pin with serial NAND */
0458 spi_nor_pins: spi-nor-pins {
0459 mux {
0460 function = "flash";
0461 groups = "spi_nor";
0462 };
0463 };
0464
0465 /* serial NAND is shared pin with SPI-NOR */
0466 serial_nand_pins: serial-nand-pins {
0467 mux {
0468 function = "flash";
0469 groups = "snfi";
0470 };
0471 };
0472
0473 uart0_pins: uart0-pins {
0474 mux {
0475 function = "uart";
0476 groups = "uart0_0_tx_rx" ;
0477 };
0478 };
0479
0480 uart2_pins: uart2-pins {
0481 mux {
0482 function = "uart";
0483 groups = "uart2_1_tx_rx" ;
0484 };
0485 };
0486
0487 watchdog_pins: watchdog-pins {
0488 mux {
0489 function = "watchdog";
0490 groups = "watchdog";
0491 };
0492 };
0493
0494 wmac_pins: wmac-pins {
0495 mux {
0496 function = "antsel";
0497 groups = "antsel0", "antsel1", "antsel2", "antsel3",
0498 "antsel4", "antsel5", "antsel6", "antsel7",
0499 "antsel8", "antsel9", "antsel12", "antsel13",
0500 "antsel14", "antsel15", "antsel16", "antsel17";
0501 };
0502 };
0503 };
0504
0505 &pwm {
0506 pinctrl-names = "default";
0507 pinctrl-0 = <&pwm7_pins>;
0508 status = "okay";
0509 };
0510
0511 &pwrap {
0512 pinctrl-names = "default";
0513 pinctrl-0 = <&pmic_bus_pins>;
0514
0515 status = "okay";
0516 };
0517
0518 &sata {
0519 status = "okay";
0520 };
0521
0522 &sata_phy {
0523 status = "okay";
0524 };
0525
0526 &spi0 {
0527 pinctrl-names = "default";
0528 pinctrl-0 = <&spic0_pins>;
0529 status = "okay";
0530 };
0531
0532 &spi1 {
0533 pinctrl-names = "default";
0534 pinctrl-0 = <&spic1_pins>;
0535 status = "okay";
0536 };
0537
0538 &ssusb {
0539 vusb33-supply = <®_3p3v>;
0540 vbus-supply = <®_5v>;
0541 status = "okay";
0542 };
0543
0544 &u3phy {
0545 status = "okay";
0546 };
0547
0548 &uart0 {
0549 pinctrl-names = "default";
0550 pinctrl-0 = <&uart0_pins>;
0551 status = "okay";
0552 };
0553
0554 &uart2 {
0555 pinctrl-names = "default";
0556 pinctrl-0 = <&uart2_pins>;
0557 status = "okay";
0558 };
0559
0560 &watchdog {
0561 pinctrl-names = "default";
0562 pinctrl-0 = <&watchdog_pins>;
0563 status = "okay";
0564 };
0565
0566 &wmac {
0567 pinctrl-names = "default";
0568 pinctrl-0 = <&wmac_pins>;
0569 status = "okay";
0570 };
