0001 /*
0002 * Copyright (c) 2018 MediaTek Inc.
0003 * Author: Ryder Lee <ryder.lee@mediatek.com>
0004 *
0005 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
0006 */
0007
0008 /dts-v1/;
0009 #include <dt-bindings/input/input.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/leds/common.h>
0012
0013 #include "mt7622.dtsi"
0014 #include "mt6380.dtsi"
0015
0016 / {
0017 model = "Bananapi BPI-R64";
0018 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
0019
0020 aliases {
0021 serial0 = &uart0;
0022 };
0023
0024 chosen {
0025 stdout-path = "serial0:115200n8";
0026 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
0027 };
0028
0029 cpus {
0030 cpu@0 {
0031 proc-supply = <&mt6380_vcpu_reg>;
0032 sram-supply = <&mt6380_vm_reg>;
0033 };
0034
0035 cpu@1 {
0036 proc-supply = <&mt6380_vcpu_reg>;
0037 sram-supply = <&mt6380_vm_reg>;
0038 };
0039 };
0040
0041 gpio-keys {
0042 compatible = "gpio-keys";
0043
0044 factory-key {
0045 label = "factory";
0046 linux,code = <BTN_0>;
0047 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
0048 };
0049
0050 wps-key {
0051 label = "wps";
0052 linux,code = <KEY_WPS_BUTTON>;
0053 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
0054 };
0055 };
0056
0057 leds {
0058 compatible = "gpio-leds";
0059
0060 led-0 {
0061 label = "bpi-r64:pio:green";
0062 color = <LED_COLOR_ID_GREEN>;
0063 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
0064 default-state = "off";
0065 };
0066
0067 led-1 {
0068 label = "bpi-r64:pio:red";
0069 color = <LED_COLOR_ID_RED>;
0070 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
0071 default-state = "off";
0072 };
0073 };
0074
0075 memory {
0076 reg = <0 0x40000000 0 0x40000000>;
0077 };
0078
0079 reg_1p8v: regulator-1p8v {
0080 compatible = "regulator-fixed";
0081 regulator-name = "fixed-1.8V";
0082 regulator-min-microvolt = <1800000>;
0083 regulator-max-microvolt = <1800000>;
0084 regulator-always-on;
0085 };
0086
0087 reg_3p3v: regulator-3p3v {
0088 compatible = "regulator-fixed";
0089 regulator-name = "fixed-3.3V";
0090 regulator-min-microvolt = <3300000>;
0091 regulator-max-microvolt = <3300000>;
0092 regulator-boot-on;
0093 regulator-always-on;
0094 };
0095
0096 reg_5v: regulator-5v {
0097 compatible = "regulator-fixed";
0098 regulator-name = "fixed-5V";
0099 regulator-min-microvolt = <5000000>;
0100 regulator-max-microvolt = <5000000>;
0101 regulator-boot-on;
0102 regulator-always-on;
0103 };
0104 };
0105
0106 &bch {
0107 status = "disabled";
0108 };
0109
0110 &btif {
0111 status = "okay";
0112 };
0113
0114 &cir {
0115 pinctrl-names = "default";
0116 pinctrl-0 = <&irrx_pins>;
0117 status = "okay";
0118 };
0119
0120 ð {
0121 status = "okay";
0122 gmac0: mac@0 {
0123 compatible = "mediatek,eth-mac";
0124 reg = <0>;
0125 phy-mode = "2500base-x";
0126
0127 fixed-link {
0128 speed = <2500>;
0129 full-duplex;
0130 pause;
0131 };
0132 };
0133
0134 gmac1: mac@1 {
0135 compatible = "mediatek,eth-mac";
0136 reg = <1>;
0137 phy-mode = "rgmii";
0138
0139 fixed-link {
0140 speed = <1000>;
0141 full-duplex;
0142 pause;
0143 };
0144 };
0145
0146 mdio: mdio-bus {
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149
0150 switch@0 {
0151 compatible = "mediatek,mt7531";
0152 reg = <0>;
0153 reset-gpios = <&pio 54 0>;
0154
0155 ports {
0156 #address-cells = <1>;
0157 #size-cells = <0>;
0158
0159 port@0 {
0160 reg = <0>;
0161 label = "wan";
0162 };
0163
0164 port@1 {
0165 reg = <1>;
0166 label = "lan0";
0167 };
0168
0169 port@2 {
0170 reg = <2>;
0171 label = "lan1";
0172 };
0173
0174 port@3 {
0175 reg = <3>;
0176 label = "lan2";
0177 };
0178
0179 port@4 {
0180 reg = <4>;
0181 label = "lan3";
0182 };
0183
0184 port@6 {
0185 reg = <6>;
0186 label = "cpu";
0187 ethernet = <&gmac0>;
0188 phy-mode = "2500base-x";
0189
0190 fixed-link {
0191 speed = <2500>;
0192 full-duplex;
0193 pause;
0194 };
0195 };
0196 };
0197 };
0198
0199 };
0200 };
0201
0202 &i2c1 {
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&i2c1_pins>;
0205 status = "okay";
0206 };
0207
0208 &i2c2 {
0209 pinctrl-names = "default";
0210 pinctrl-0 = <&i2c2_pins>;
0211 status = "okay";
0212 };
0213
0214 &mmc0 {
0215 pinctrl-names = "default", "state_uhs";
0216 pinctrl-0 = <&emmc_pins_default>;
0217 pinctrl-1 = <&emmc_pins_uhs>;
0218 status = "okay";
0219 bus-width = <8>;
0220 max-frequency = <50000000>;
0221 cap-mmc-highspeed;
0222 mmc-hs200-1_8v;
0223 vmmc-supply = <®_3p3v>;
0224 vqmmc-supply = <®_1p8v>;
0225 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
0226 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
0227 non-removable;
0228 };
0229
0230 &mmc1 {
0231 pinctrl-names = "default", "state_uhs";
0232 pinctrl-0 = <&sd0_pins_default>;
0233 pinctrl-1 = <&sd0_pins_uhs>;
0234 status = "okay";
0235 bus-width = <4>;
0236 max-frequency = <50000000>;
0237 cap-sd-highspeed;
0238 r_smpl = <1>;
0239 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
0240 vmmc-supply = <®_3p3v>;
0241 vqmmc-supply = <®_3p3v>;
0242 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
0243 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
0244 };
0245
0246 &nandc {
0247 pinctrl-names = "default";
0248 pinctrl-0 = <¶llel_nand_pins>;
0249 status = "disabled";
0250 };
0251
0252 &nor_flash {
0253 pinctrl-names = "default";
0254 pinctrl-0 = <&spi_nor_pins>;
0255 status = "disabled";
0256
0257 flash@0 {
0258 compatible = "jedec,spi-nor";
0259 reg = <0>;
0260 };
0261 };
0262
0263 &pcie0 {
0264 pinctrl-names = "default";
0265 pinctrl-0 = <&pcie0_pins>;
0266 status = "okay";
0267 };
0268
0269 &pcie1 {
0270 pinctrl-names = "default";
0271 pinctrl-0 = <&pcie1_pins>;
0272 status = "okay";
0273 };
0274
0275 &pio {
0276 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
0277 * SATA functions. i.e. output-high: PCIe, output-low: SATA
0278 */
0279 asm_sel {
0280 gpio-hog;
0281 gpios = <90 GPIO_ACTIVE_HIGH>;
0282 output-high;
0283 };
0284
0285 /* eMMC is shared pin with parallel NAND */
0286 emmc_pins_default: emmc-pins-default {
0287 mux {
0288 function = "emmc", "emmc_rst";
0289 groups = "emmc";
0290 };
0291
0292 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
0293 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
0294 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
0295 */
0296 conf-cmd-dat {
0297 pins = "NDL0", "NDL1", "NDL2",
0298 "NDL3", "NDL4", "NDL5",
0299 "NDL6", "NDL7", "NRB";
0300 input-enable;
0301 bias-pull-up;
0302 };
0303
0304 conf-clk {
0305 pins = "NCLE";
0306 bias-pull-down;
0307 };
0308 };
0309
0310 emmc_pins_uhs: emmc-pins-uhs {
0311 mux {
0312 function = "emmc";
0313 groups = "emmc";
0314 };
0315
0316 conf-cmd-dat {
0317 pins = "NDL0", "NDL1", "NDL2",
0318 "NDL3", "NDL4", "NDL5",
0319 "NDL6", "NDL7", "NRB";
0320 input-enable;
0321 drive-strength = <4>;
0322 bias-pull-up;
0323 };
0324
0325 conf-clk {
0326 pins = "NCLE";
0327 drive-strength = <4>;
0328 bias-pull-down;
0329 };
0330 };
0331
0332 eth_pins: eth-pins {
0333 mux {
0334 function = "eth";
0335 groups = "mdc_mdio", "rgmii_via_gmac2";
0336 };
0337 };
0338
0339 i2c1_pins: i2c1-pins {
0340 mux {
0341 function = "i2c";
0342 groups = "i2c1_0";
0343 };
0344 };
0345
0346 i2c2_pins: i2c2-pins {
0347 mux {
0348 function = "i2c";
0349 groups = "i2c2_0";
0350 };
0351 };
0352
0353 i2s1_pins: i2s1-pins {
0354 mux {
0355 function = "i2s";
0356 groups = "i2s_out_mclk_bclk_ws",
0357 "i2s1_in_data",
0358 "i2s1_out_data";
0359 };
0360
0361 conf {
0362 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
0363 "I2S_WS", "I2S_MCLK";
0364 drive-strength = <12>;
0365 bias-pull-down;
0366 };
0367 };
0368
0369 irrx_pins: irrx-pins {
0370 mux {
0371 function = "ir";
0372 groups = "ir_1_rx";
0373 };
0374 };
0375
0376 irtx_pins: irtx-pins {
0377 mux {
0378 function = "ir";
0379 groups = "ir_1_tx";
0380 };
0381 };
0382
0383 /* Parallel nand is shared pin with eMMC */
0384 parallel_nand_pins: parallel-nand-pins {
0385 mux {
0386 function = "flash";
0387 groups = "par_nand";
0388 };
0389 };
0390
0391 pcie0_pins: pcie0-pins {
0392 mux {
0393 function = "pcie";
0394 groups = "pcie0_pad_perst",
0395 "pcie0_1_waken",
0396 "pcie0_1_clkreq";
0397 };
0398 };
0399
0400 pcie1_pins: pcie1-pins {
0401 mux {
0402 function = "pcie";
0403 groups = "pcie1_pad_perst",
0404 "pcie1_0_waken",
0405 "pcie1_0_clkreq";
0406 };
0407 };
0408
0409 pmic_bus_pins: pmic-bus-pins {
0410 mux {
0411 function = "pmic";
0412 groups = "pmic_bus";
0413 };
0414 };
0415
0416 pwm_pins: pwm-pins {
0417 mux {
0418 function = "pwm";
0419 groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
0420 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
0421 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
0422 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
0423 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
0424 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
0425 };
0426 };
0427
0428 wled_pins: wled-pins {
0429 mux {
0430 function = "led";
0431 groups = "wled";
0432 };
0433 };
0434
0435 sd0_pins_default: sd0-pins-default {
0436 mux {
0437 function = "sd";
0438 groups = "sd_0";
0439 };
0440
0441 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
0442 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
0443 * DAT2, DAT3, CMD, CLK for SD respectively.
0444 */
0445 conf-cmd-data {
0446 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
0447 "I2S2_IN","I2S4_OUT";
0448 input-enable;
0449 drive-strength = <8>;
0450 bias-pull-up;
0451 };
0452 conf-clk {
0453 pins = "I2S3_OUT";
0454 drive-strength = <12>;
0455 bias-pull-down;
0456 };
0457 conf-cd {
0458 pins = "TXD3";
0459 bias-pull-up;
0460 };
0461 };
0462
0463 sd0_pins_uhs: sd0-pins-uhs {
0464 mux {
0465 function = "sd";
0466 groups = "sd_0";
0467 };
0468
0469 conf-cmd-data {
0470 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
0471 "I2S2_IN","I2S4_OUT";
0472 input-enable;
0473 bias-pull-up;
0474 };
0475
0476 conf-clk {
0477 pins = "I2S3_OUT";
0478 bias-pull-down;
0479 };
0480 };
0481
0482 /* Serial NAND is shared pin with SPI-NOR */
0483 serial_nand_pins: serial-nand-pins {
0484 mux {
0485 function = "flash";
0486 groups = "snfi";
0487 };
0488 };
0489
0490 spic0_pins: spic0-pins {
0491 mux {
0492 function = "spi";
0493 groups = "spic0_0";
0494 };
0495 };
0496
0497 spic1_pins: spic1-pins {
0498 mux {
0499 function = "spi";
0500 groups = "spic1_0";
0501 };
0502 };
0503
0504 /* SPI-NOR is shared pin with serial NAND */
0505 spi_nor_pins: spi-nor-pins {
0506 mux {
0507 function = "flash";
0508 groups = "spi_nor";
0509 };
0510 };
0511
0512 /* serial NAND is shared pin with SPI-NOR */
0513 serial_nand_pins: serial-nand-pins {
0514 mux {
0515 function = "flash";
0516 groups = "snfi";
0517 };
0518 };
0519
0520 uart0_pins: uart0-pins {
0521 mux {
0522 function = "uart";
0523 groups = "uart0_0_tx_rx" ;
0524 };
0525 };
0526
0527 uart2_pins: uart2-pins {
0528 mux {
0529 function = "uart";
0530 groups = "uart2_1_tx_rx" ;
0531 };
0532 };
0533
0534 watchdog_pins: watchdog-pins {
0535 mux {
0536 function = "watchdog";
0537 groups = "watchdog";
0538 };
0539 };
0540 };
0541
0542 &pwm {
0543 pinctrl-names = "default";
0544 pinctrl-0 = <&pwm_pins>;
0545 status = "okay";
0546 };
0547
0548 &pwrap {
0549 pinctrl-names = "default";
0550 pinctrl-0 = <&pmic_bus_pins>;
0551
0552 status = "okay";
0553 };
0554
0555 &sata {
0556 status = "disable";
0557 };
0558
0559 &sata_phy {
0560 status = "disable";
0561 };
0562
0563 &spi0 {
0564 pinctrl-names = "default";
0565 pinctrl-0 = <&spic0_pins>;
0566 status = "okay";
0567 };
0568
0569 &spi1 {
0570 pinctrl-names = "default";
0571 pinctrl-0 = <&spic1_pins>;
0572 };
0573
0574 &ssusb {
0575 vusb33-supply = <®_3p3v>;
0576 vbus-supply = <®_5v>;
0577 status = "okay";
0578 };
0579
0580 &u3phy {
0581 status = "okay";
0582 };
0583
0584 &uart0 {
0585 pinctrl-names = "default";
0586 pinctrl-0 = <&uart0_pins>;
0587 status = "okay";
0588 };
0589
0590 &uart2 {
0591 pinctrl-names = "default";
0592 pinctrl-0 = <&uart2_pins>;
0593 };
0594
0595 &watchdog {
0596 pinctrl-names = "default";
0597 pinctrl-0 = <&watchdog_pins>;
0598 status = "okay";
0599 };
0600
0601 &wmac {
0602 status = "okay";
0603 };
