0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2017 MediaTek Inc.
0004 * Author: Mars.C <mars.cheng@mediatek.com>
0005 */
0006
0007 #include <dt-bindings/clock/mt6797-clk.h>
0008 #include <dt-bindings/interrupt-controller/irq.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
0011
0012 / {
0013 compatible = "mediatek,mt6797";
0014 interrupt-parent = <&sysirq>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 psci {
0019 compatible = "arm,psci-0.2";
0020 method = "smc";
0021 };
0022
0023 cpus {
0024 #address-cells = <1>;
0025 #size-cells = <0>;
0026
0027 cpu0: cpu@0 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a53";
0030 enable-method = "psci";
0031 reg = <0x000>;
0032 };
0033
0034 cpu1: cpu@1 {
0035 device_type = "cpu";
0036 compatible = "arm,cortex-a53";
0037 enable-method = "psci";
0038 reg = <0x001>;
0039 };
0040
0041 cpu2: cpu@2 {
0042 device_type = "cpu";
0043 compatible = "arm,cortex-a53";
0044 enable-method = "psci";
0045 reg = <0x002>;
0046 };
0047
0048 cpu3: cpu@3 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a53";
0051 enable-method = "psci";
0052 reg = <0x003>;
0053 };
0054
0055 cpu4: cpu@100 {
0056 device_type = "cpu";
0057 compatible = "arm,cortex-a53";
0058 enable-method = "psci";
0059 reg = <0x100>;
0060 };
0061
0062 cpu5: cpu@101 {
0063 device_type = "cpu";
0064 compatible = "arm,cortex-a53";
0065 enable-method = "psci";
0066 reg = <0x101>;
0067 };
0068
0069 cpu6: cpu@102 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a53";
0072 enable-method = "psci";
0073 reg = <0x102>;
0074 };
0075
0076 cpu7: cpu@103 {
0077 device_type = "cpu";
0078 compatible = "arm,cortex-a53";
0079 enable-method = "psci";
0080 reg = <0x103>;
0081 };
0082
0083 cpu8: cpu@200 {
0084 device_type = "cpu";
0085 compatible = "arm,cortex-a72";
0086 enable-method = "psci";
0087 reg = <0x200>;
0088 };
0089
0090 cpu9: cpu@201 {
0091 device_type = "cpu";
0092 compatible = "arm,cortex-a72";
0093 enable-method = "psci";
0094 reg = <0x201>;
0095 };
0096 };
0097
0098 clk26m: oscillator@0 {
0099 compatible = "fixed-clock";
0100 #clock-cells = <0>;
0101 clock-frequency = <26000000>;
0102 clock-output-names = "clk26m";
0103 };
0104
0105 timer {
0106 compatible = "arm,armv8-timer";
0107 interrupt-parent = <&gic>;
0108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0109 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0110 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0111 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0112 };
0113
0114 topckgen: topckgen@10000000 {
0115 compatible = "mediatek,mt6797-topckgen";
0116 reg = <0 0x10000000 0 0x1000>;
0117 #clock-cells = <1>;
0118 };
0119
0120 infrasys: infracfg_ao@10001000 {
0121 compatible = "mediatek,mt6797-infracfg", "syscon";
0122 reg = <0 0x10001000 0 0x1000>;
0123 #clock-cells = <1>;
0124 };
0125
0126 pio: pinctrl@10005000 {
0127 compatible = "mediatek,mt6797-pinctrl";
0128 reg = <0 0x10005000 0 0x1000>,
0129 <0 0x10002000 0 0x400>,
0130 <0 0x10002400 0 0x400>,
0131 <0 0x10002800 0 0x400>,
0132 <0 0x10002C00 0 0x400>;
0133 reg-names = "gpio", "iocfgl", "iocfgb",
0134 "iocfgr", "iocfgt";
0135 gpio-controller;
0136 #gpio-cells = <2>;
0137
0138 uart0_pins_a: uart0 {
0139 pins0 {
0140 pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
0141 <MT6797_GPIO235__FUNC_URXD0>;
0142 };
0143 };
0144
0145 uart1_pins_a: uart1 {
0146 pins1 {
0147 pinmux = <MT6797_GPIO232__FUNC_URXD1>,
0148 <MT6797_GPIO233__FUNC_UTXD1>;
0149 };
0150 };
0151
0152 i2c0_pins_a: i2c0 {
0153 pins0 {
0154 pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
0155 <MT6797_GPIO38__FUNC_SDA0_0>;
0156 };
0157 };
0158
0159 i2c1_pins_a: i2c1 {
0160 pins1 {
0161 pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
0162 <MT6797_GPIO56__FUNC_SDA1_0>;
0163 };
0164 };
0165
0166 i2c2_pins_a: i2c2 {
0167 pins2 {
0168 pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
0169 <MT6797_GPIO95__FUNC_SDA2_0>;
0170 };
0171 };
0172
0173 i2c3_pins_a: i2c3 {
0174 pins3 {
0175 pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
0176 <MT6797_GPIO74__FUNC_SCL3_0>;
0177 };
0178 };
0179
0180 i2c4_pins_a: i2c4 {
0181 pins4 {
0182 pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
0183 <MT6797_GPIO239__FUNC_SCL4_0>;
0184 };
0185 };
0186
0187 i2c5_pins_a: i2c5 {
0188 pins5 {
0189 pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
0190 <MT6797_GPIO241__FUNC_SCL5_0>;
0191 };
0192 };
0193
0194 i2c6_pins_a: i2c6 {
0195 pins6 {
0196 pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
0197 <MT6797_GPIO151__FUNC_SCL6_0>;
0198 };
0199 };
0200
0201 i2c7_pins_a: i2c7 {
0202 pins7 {
0203 pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
0204 <MT6797_GPIO153__FUNC_SCL7_0>;
0205 };
0206 };
0207 };
0208
0209 scpsys: power-controller@10006000 {
0210 compatible = "mediatek,mt6797-scpsys";
0211 #power-domain-cells = <1>;
0212 reg = <0 0x10006000 0 0x1000>;
0213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
0214 <&topckgen CLK_TOP_MUX_MM>,
0215 <&topckgen CLK_TOP_MUX_VDEC>;
0216 clock-names = "mfg", "mm", "vdec";
0217 infracfg = <&infrasys>;
0218 };
0219
0220 watchdog: watchdog@10007000 {
0221 compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
0222 reg = <0 0x10007000 0 0x100>;
0223 };
0224
0225 apmixedsys: apmixed@1000c000 {
0226 compatible = "mediatek,mt6797-apmixedsys";
0227 reg = <0 0x1000c000 0 0x1000>;
0228 #clock-cells = <1>;
0229 };
0230
0231 sysirq: intpol-controller@10200620 {
0232 compatible = "mediatek,mt6797-sysirq",
0233 "mediatek,mt6577-sysirq";
0234 interrupt-controller;
0235 #interrupt-cells = <3>;
0236 interrupt-parent = <&gic>;
0237 reg = <0 0x10220620 0 0x20>,
0238 <0 0x10220690 0 0x10>;
0239 };
0240
0241 uart0: serial@11002000 {
0242 compatible = "mediatek,mt6797-uart",
0243 "mediatek,mt6577-uart";
0244 reg = <0 0x11002000 0 0x400>;
0245 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
0246 clocks = <&infrasys CLK_INFRA_UART0>,
0247 <&infrasys CLK_INFRA_AP_DMA>;
0248 clock-names = "baud", "bus";
0249 status = "disabled";
0250 };
0251
0252 uart1: serial@11003000 {
0253 compatible = "mediatek,mt6797-uart",
0254 "mediatek,mt6577-uart";
0255 reg = <0 0x11003000 0 0x400>;
0256 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0257 clocks = <&infrasys CLK_INFRA_UART1>,
0258 <&infrasys CLK_INFRA_AP_DMA>;
0259 clock-names = "baud", "bus";
0260 status = "disabled";
0261 };
0262
0263 uart2: serial@11004000 {
0264 compatible = "mediatek,mt6797-uart",
0265 "mediatek,mt6577-uart";
0266 reg = <0 0x11004000 0 0x400>;
0267 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
0268 clocks = <&infrasys CLK_INFRA_UART2>,
0269 <&infrasys CLK_INFRA_AP_DMA>;
0270 clock-names = "baud", "bus";
0271 status = "disabled";
0272 };
0273
0274 uart3: serial@11005000 {
0275 compatible = "mediatek,mt6797-uart",
0276 "mediatek,mt6577-uart";
0277 reg = <0 0x11005000 0 0x400>;
0278 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
0279 clocks = <&infrasys CLK_INFRA_UART3>,
0280 <&infrasys CLK_INFRA_AP_DMA>;
0281 clock-names = "baud", "bus";
0282 status = "disabled";
0283 };
0284
0285 i2c0: i2c@11007000 {
0286 compatible = "mediatek,mt6797-i2c",
0287 "mediatek,mt6577-i2c";
0288 id = <0>;
0289 reg = <0 0x11007000 0 0x1000>,
0290 <0 0x11000100 0 0x80>;
0291 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
0292 clocks = <&infrasys CLK_INFRA_I2C0>,
0293 <&infrasys CLK_INFRA_AP_DMA>;
0294 clock-names = "main", "dma";
0295 clock-div = <10>;
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 status = "disabled";
0299 };
0300
0301 i2c1: i2c@11008000 {
0302 compatible = "mediatek,mt6797-i2c",
0303 "mediatek,mt6577-i2c";
0304 id = <1>;
0305 reg = <0 0x11008000 0 0x1000>,
0306 <0 0x11000180 0 0x80>;
0307 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
0308 clocks = <&infrasys CLK_INFRA_I2C1>,
0309 <&infrasys CLK_INFRA_AP_DMA>;
0310 clock-names = "main", "dma";
0311 clock-div = <10>;
0312 #address-cells = <1>;
0313 #size-cells = <0>;
0314 status = "disabled";
0315 };
0316
0317 i2c8: i2c@11009000 {
0318 compatible = "mediatek,mt6797-i2c",
0319 "mediatek,mt6577-i2c";
0320 id = <8>;
0321 reg = <0 0x11009000 0 0x1000>,
0322 <0 0x11000200 0 0x80>;
0323 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
0324 clocks = <&infrasys CLK_INFRA_I2C2>,
0325 <&infrasys CLK_INFRA_AP_DMA>,
0326 <&infrasys CLK_INFRA_I2C2_ARB>;
0327 clock-names = "main", "dma", "arb";
0328 clock-div = <10>;
0329 #address-cells = <1>;
0330 #size-cells = <0>;
0331 status = "disabled";
0332 };
0333
0334 i2c9: i2c@1100d000 {
0335 compatible = "mediatek,mt6797-i2c",
0336 "mediatek,mt6577-i2c";
0337 id = <9>;
0338 reg = <0 0x1100d000 0 0x1000>,
0339 <0 0x11000280 0 0x80>;
0340 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
0341 clocks = <&infrasys CLK_INFRA_I2C3>,
0342 <&infrasys CLK_INFRA_AP_DMA>,
0343 <&infrasys CLK_INFRA_I2C3_ARB>;
0344 clock-names = "main", "dma", "arb";
0345 clock-div = <10>;
0346 #address-cells = <1>;
0347 #size-cells = <0>;
0348 status = "disabled";
0349 };
0350
0351 i2c6: i2c@1100e000 {
0352 compatible = "mediatek,mt6797-i2c",
0353 "mediatek,mt6577-i2c";
0354 id = <6>;
0355 reg = <0 0x1100e000 0 0x1000>,
0356 <0 0x11000500 0 0x80>;
0357 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
0358 clocks = <&infrasys CLK_INFRA_I2C_APPM>,
0359 <&infrasys CLK_INFRA_AP_DMA>;
0360 clock-names = "main", "dma";
0361 clock-div = <10>;
0362 #address-cells = <1>;
0363 #size-cells = <0>;
0364 status = "disabled";
0365 };
0366
0367 i2c7: i2c@11010000 {
0368 compatible = "mediatek,mt6797-i2c",
0369 "mediatek,mt6577-i2c";
0370 id = <7>;
0371 reg = <0 0x11010000 0 0x1000>,
0372 <0 0x11000580 0 0x80>;
0373 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
0374 clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
0375 <&infrasys CLK_INFRA_AP_DMA>;
0376 clock-names = "main", "dma";
0377 clock-div = <10>;
0378 #address-cells = <1>;
0379 #size-cells = <0>;
0380 status = "disabled";
0381 };
0382
0383 i2c4: i2c@11011000 {
0384 compatible = "mediatek,mt6797-i2c",
0385 "mediatek,mt6577-i2c";
0386 id = <4>;
0387 reg = <0 0x11011000 0 0x1000>,
0388 <0 0x11000300 0 0x80>;
0389 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
0390 clocks = <&infrasys CLK_INFRA_I2C4>,
0391 <&infrasys CLK_INFRA_AP_DMA>;
0392 clock-names = "main", "dma";
0393 clock-div = <10>;
0394 #address-cells = <1>;
0395 #size-cells = <0>;
0396 status = "disabled";
0397 };
0398
0399 i2c2: i2c@11013000 {
0400 compatible = "mediatek,mt6797-i2c",
0401 "mediatek,mt6577-i2c";
0402 id = <2>;
0403 reg = <0 0x11013000 0 0x1000>,
0404 <0 0x11000400 0 0x80>;
0405 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
0406 clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
0407 <&infrasys CLK_INFRA_AP_DMA>,
0408 <&infrasys CLK_INFRA_I2C2_ARB>;
0409 clock-names = "main", "dma", "arb";
0410 clock-div = <10>;
0411 #address-cells = <1>;
0412 #size-cells = <0>;
0413 status = "disabled";
0414 };
0415
0416 i2c3: i2c@11014000 {
0417 compatible = "mediatek,mt6797-i2c",
0418 "mediatek,mt6577-i2c";
0419 id = <3>;
0420 reg = <0 0x11014000 0 0x1000>,
0421 <0 0x11000480 0 0x80>;
0422 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
0423 clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
0424 <&infrasys CLK_INFRA_AP_DMA>,
0425 <&infrasys CLK_INFRA_I2C3_ARB>;
0426 clock-names = "main", "dma", "arb";
0427 clock-div = <10>;
0428 #address-cells = <1>;
0429 #size-cells = <0>;
0430 status = "disabled";
0431 };
0432
0433 i2c5: i2c@1101c000 {
0434 compatible = "mediatek,mt6797-i2c",
0435 "mediatek,mt6577-i2c";
0436 id = <5>;
0437 reg = <0 0x1101c000 0 0x1000>,
0438 <0 0x11000380 0 0x80>;
0439 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
0440 clocks = <&infrasys CLK_INFRA_I2C5>,
0441 <&infrasys CLK_INFRA_AP_DMA>;
0442 clock-names = "main", "dma";
0443 clock-div = <10>;
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 status = "disabled";
0447 };
0448
0449 mmsys: syscon@14000000 {
0450 compatible = "mediatek,mt6797-mmsys", "syscon";
0451 reg = <0 0x14000000 0 0x1000>;
0452 #clock-cells = <1>;
0453 };
0454
0455 imgsys: imgsys_config@15000000 {
0456 compatible = "mediatek,mt6797-imgsys", "syscon";
0457 reg = <0 0x15000000 0 0x1000>;
0458 #clock-cells = <1>;
0459 };
0460
0461 vdecsys: vdec_gcon@16000000 {
0462 compatible = "mediatek,mt6797-vdecsys", "syscon";
0463 reg = <0 0x16000000 0 0x10000>;
0464 #clock-cells = <1>;
0465 };
0466
0467 vencsys: venc_gcon@17000000 {
0468 compatible = "mediatek,mt6797-vencsys", "syscon";
0469 reg = <0 0x17000000 0 0x1000>;
0470 #clock-cells = <1>;
0471 };
0472
0473 gic: interrupt-controller@19000000 {
0474 compatible = "arm,gic-v3";
0475 #interrupt-cells = <3>;
0476 interrupt-parent = <&gic>;
0477 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0478 interrupt-controller;
0479 reg = <0 0x19000000 0 0x10000>, /* GICD */
0480 <0 0x19200000 0 0x200000>, /* GICR */
0481 <0 0x10240000 0 0x2000>; /* GICC */
0482 };
0483 };
