0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2015 MediaTek Inc.
0004 * Author: Mars.C <mars.cheng@mediatek.com>
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
0010
0011 / {
0012 compatible = "mediatek,mt6795";
0013 interrupt-parent = <&sysirq>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 psci {
0018 compatible = "arm,psci-0.2";
0019 method = "smc";
0020 };
0021
0022 cpus {
0023 #address-cells = <1>;
0024 #size-cells = <0>;
0025
0026 cpu0: cpu@0 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a53";
0029 enable-method = "psci";
0030 reg = <0x000>;
0031 cci-control-port = <&cci_control2>;
0032 next-level-cache = <&l2_0>;
0033 };
0034
0035 cpu1: cpu@1 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a53";
0038 enable-method = "psci";
0039 reg = <0x001>;
0040 cci-control-port = <&cci_control2>;
0041 next-level-cache = <&l2_0>;
0042 };
0043
0044 cpu2: cpu@2 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a53";
0047 enable-method = "psci";
0048 reg = <0x002>;
0049 cci-control-port = <&cci_control2>;
0050 next-level-cache = <&l2_0>;
0051 };
0052
0053 cpu3: cpu@3 {
0054 device_type = "cpu";
0055 compatible = "arm,cortex-a53";
0056 enable-method = "psci";
0057 reg = <0x003>;
0058 cci-control-port = <&cci_control2>;
0059 next-level-cache = <&l2_0>;
0060 };
0061
0062 cpu4: cpu@100 {
0063 device_type = "cpu";
0064 compatible = "arm,cortex-a53";
0065 enable-method = "psci";
0066 reg = <0x100>;
0067 cci-control-port = <&cci_control1>;
0068 next-level-cache = <&l2_1>;
0069 };
0070
0071 cpu5: cpu@101 {
0072 device_type = "cpu";
0073 compatible = "arm,cortex-a53";
0074 enable-method = "psci";
0075 reg = <0x101>;
0076 cci-control-port = <&cci_control1>;
0077 next-level-cache = <&l2_1>;
0078 };
0079
0080 cpu6: cpu@102 {
0081 device_type = "cpu";
0082 compatible = "arm,cortex-a53";
0083 enable-method = "psci";
0084 reg = <0x102>;
0085 cci-control-port = <&cci_control1>;
0086 next-level-cache = <&l2_1>;
0087 };
0088
0089 cpu7: cpu@103 {
0090 device_type = "cpu";
0091 compatible = "arm,cortex-a53";
0092 enable-method = "psci";
0093 reg = <0x103>;
0094 cci-control-port = <&cci_control1>;
0095 next-level-cache = <&l2_1>;
0096 };
0097
0098 cpu-map {
0099 cluster0 {
0100 core0 {
0101 cpu = <&cpu0>;
0102 };
0103
0104 core1 {
0105 cpu = <&cpu1>;
0106 };
0107
0108 core2 {
0109 cpu = <&cpu2>;
0110 };
0111
0112 core3 {
0113 cpu = <&cpu3>;
0114 };
0115 };
0116
0117 cluster1 {
0118 core0 {
0119 cpu = <&cpu4>;
0120 };
0121
0122 core1 {
0123 cpu = <&cpu5>;
0124 };
0125
0126 core2 {
0127 cpu = <&cpu6>;
0128 };
0129
0130 core3 {
0131 cpu = <&cpu7>;
0132 };
0133 };
0134 };
0135
0136 l2_0: l2-cache0 {
0137 compatible = "cache";
0138 cache-level = <2>;
0139 };
0140
0141 l2_1: l2-cache1 {
0142 compatible = "cache";
0143 cache-level = <2>;
0144 };
0145 };
0146
0147 clk26m: oscillator-26m {
0148 compatible = "fixed-clock";
0149 #clock-cells = <0>;
0150 clock-frequency = <26000000>;
0151 clock-output-names = "clk26m";
0152 };
0153
0154 clk32k: oscillator-32k {
0155 compatible = "fixed-clock";
0156 #clock-cells = <0>;
0157 clock-frequency = <32000>;
0158 clock-output-names = "clk32k";
0159 };
0160
0161 system_clk: dummy13m {
0162 compatible = "fixed-clock";
0163 clock-frequency = <13000000>;
0164 #clock-cells = <0>;
0165 };
0166
0167 pmu {
0168 compatible = "arm,cortex-a53-pmu";
0169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
0170 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>,
0171 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
0172 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
0173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0174 };
0175
0176 timer {
0177 compatible = "arm,armv8-timer";
0178 interrupt-parent = <&gic>;
0179 interrupts = <GIC_PPI 13
0180 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0181 <GIC_PPI 14
0182 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0183 <GIC_PPI 11
0184 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0185 <GIC_PPI 10
0186 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0187 };
0188
0189 soc {
0190 #address-cells = <2>;
0191 #size-cells = <2>;
0192 compatible = "simple-bus";
0193 ranges;
0194
0195 pio: pinctrl@10005000 {
0196 compatible = "mediatek,mt6795-pinctrl";
0197 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
0198 reg-names = "base", "eint";
0199 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0200 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0201 gpio-controller;
0202 #gpio-cells = <2>;
0203 gpio-ranges = <&pio 0 0 196>;
0204 interrupt-controller;
0205 #interrupt-cells = <2>;
0206 };
0207
0208 watchdog: watchdog@10007000 {
0209 compatible = "mediatek,mt6795-wdt";
0210 reg = <0 0x10007000 0 0x100>;
0211 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
0212 #reset-cells = <1>;
0213 timeout-sec = <20>;
0214 };
0215
0216 timer: timer@10008000 {
0217 compatible = "mediatek,mt6795-timer",
0218 "mediatek,mt6577-timer";
0219 reg = <0 0x10008000 0 0x1000>;
0220 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
0221 clocks = <&system_clk>, <&clk32k>;
0222 };
0223
0224 sysirq: intpol-controller@10200620 {
0225 compatible = "mediatek,mt6795-sysirq",
0226 "mediatek,mt6577-sysirq";
0227 interrupt-controller;
0228 #interrupt-cells = <3>;
0229 interrupt-parent = <&gic>;
0230 reg = <0 0x10200620 0 0x20>;
0231 };
0232
0233 gic: interrupt-controller@10221000 {
0234 compatible = "arm,gic-400";
0235 #interrupt-cells = <3>;
0236 interrupt-parent = <&gic>;
0237 interrupt-controller;
0238 reg = <0 0x10221000 0 0x1000>,
0239 <0 0x10222000 0 0x2000>,
0240 <0 0x10224000 0 0x2000>,
0241 <0 0x10226000 0 0x2000>;
0242 interrupts = <GIC_PPI 9
0243 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0244 };
0245
0246 cci: cci@10390000 {
0247 compatible = "arm,cci-400";
0248 #address-cells = <1>;
0249 #size-cells = <1>;
0250 reg = <0 0x10390000 0 0x1000>;
0251 ranges = <0 0 0x10390000 0x10000>;
0252
0253 cci_control0: slave-if@1000 {
0254 compatible = "arm,cci-400-ctrl-if";
0255 interface-type = "ace-lite";
0256 reg = <0x1000 0x1000>;
0257 };
0258
0259 cci_control1: slave-if@4000 {
0260 compatible = "arm,cci-400-ctrl-if";
0261 interface-type = "ace";
0262 reg = <0x4000 0x1000>;
0263 };
0264
0265 cci_control2: slave-if@5000 {
0266 compatible = "arm,cci-400-ctrl-if";
0267 interface-type = "ace";
0268 reg = <0x5000 0x1000>;
0269 };
0270
0271 pmu@9000 {
0272 compatible = "arm,cci-400-pmu,r1";
0273 reg = <0x9000 0x5000>;
0274 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0275 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0276 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0277 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
0278 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0279 };
0280 };
0281
0282 uart0: serial@11002000 {
0283 compatible = "mediatek,mt6795-uart",
0284 "mediatek,mt6577-uart";
0285 reg = <0 0x11002000 0 0x400>;
0286 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
0287 clocks = <&clk26m>;
0288 status = "disabled";
0289 };
0290
0291 uart1: serial@11003000 {
0292 compatible = "mediatek,mt6795-uart",
0293 "mediatek,mt6577-uart";
0294 reg = <0 0x11003000 0 0x400>;
0295 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0296 clocks = <&clk26m>;
0297 status = "disabled";
0298 };
0299
0300 uart2: serial@11004000 {
0301 compatible = "mediatek,mt6795-uart",
0302 "mediatek,mt6577-uart";
0303 reg = <0 0x11004000 0 0x400>;
0304 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
0305 clocks = <&clk26m>;
0306 status = "disabled";
0307 };
0308
0309 uart3: serial@11005000 {
0310 compatible = "mediatek,mt6795-uart",
0311 "mediatek,mt6577-uart";
0312 reg = <0 0x11005000 0 0x400>;
0313 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
0314 clocks = <&clk26m>;
0315 status = "disabled";
0316 };
0317 };
0318 };
