0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (c) 2019 MediaTek Inc.
0004 * Author: Mars.C <mars.cheng@mediatek.com>
0005 *
0006 */
0007
0008 #include <dt-bindings/clock/mt6779-clk.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
0012
0013 / {
0014 compatible = "mediatek,mt6779";
0015 interrupt-parent = <&sysirq>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 psci {
0020 compatible = "arm,psci-0.2";
0021 method = "smc";
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu0: cpu@0 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a55";
0031 enable-method = "psci";
0032 reg = <0x000>;
0033 };
0034
0035 cpu1: cpu@1 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a55";
0038 enable-method = "psci";
0039 reg = <0x100>;
0040 };
0041
0042 cpu2: cpu@2 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a55";
0045 enable-method = "psci";
0046 reg = <0x200>;
0047 };
0048
0049 cpu3: cpu@3 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a55";
0052 enable-method = "psci";
0053 reg = <0x300>;
0054 };
0055
0056 cpu4: cpu@4 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a55";
0059 enable-method = "psci";
0060 reg = <0x400>;
0061 };
0062
0063 cpu5: cpu@5 {
0064 device_type = "cpu";
0065 compatible = "arm,cortex-a55";
0066 enable-method = "psci";
0067 reg = <0x500>;
0068 };
0069
0070 cpu6: cpu@6 {
0071 device_type = "cpu";
0072 compatible = "arm,cortex-a75";
0073 enable-method = "psci";
0074 reg = <0x600>;
0075 };
0076
0077 cpu7: cpu@7 {
0078 device_type = "cpu";
0079 compatible = "arm,cortex-a75";
0080 enable-method = "psci";
0081 reg = <0x700>;
0082 };
0083 };
0084
0085 pmu {
0086 compatible = "arm,armv8-pmuv3";
0087 interrupt-parent = <&gic>;
0088 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
0089 };
0090
0091 clk26m: oscillator@0 {
0092 compatible = "fixed-clock";
0093 #clock-cells = <0>;
0094 clock-frequency = <26000000>;
0095 clock-output-names = "clk26m";
0096 };
0097
0098 clk32k: oscillator@1 {
0099 compatible = "fixed-clock";
0100 #clock-cells = <0>;
0101 clock-frequency = <32768>;
0102 clock-output-names = "clk32k";
0103 };
0104
0105 timer {
0106 compatible = "arm,armv8-timer";
0107 interrupt-parent = <&gic>;
0108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
0109 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
0110 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
0111 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
0112 };
0113
0114 soc {
0115 #address-cells = <2>;
0116 #size-cells = <2>;
0117 compatible = "simple-bus";
0118 ranges;
0119
0120 gic: interrupt-controller@0c000000 {
0121 compatible = "arm,gic-v3";
0122 #interrupt-cells = <4>;
0123 interrupt-parent = <&gic>;
0124 interrupt-controller;
0125 reg = <0 0x0c000000 0 0x40000>, /* GICD */
0126 <0 0x0c040000 0 0x200000>; /* GICR */
0127 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
0128
0129 ppi-partitions {
0130 ppi_cluster0: interrupt-partition-0 {
0131 affinity = <&cpu0 &cpu1 \
0132 &cpu2 &cpu3 &cpu4 &cpu5>;
0133 };
0134 ppi_cluster1: interrupt-partition-1 {
0135 affinity = <&cpu6 &cpu7>;
0136 };
0137 };
0138
0139 };
0140
0141 sysirq: intpol-controller@0c53a650 {
0142 compatible = "mediatek,mt6779-sysirq",
0143 "mediatek,mt6577-sysirq";
0144 interrupt-controller;
0145 #interrupt-cells = <3>;
0146 interrupt-parent = <&gic>;
0147 reg = <0 0x0c53a650 0 0x50>;
0148 };
0149
0150 topckgen: clock-controller@10000000 {
0151 compatible = "mediatek,mt6779-topckgen", "syscon";
0152 reg = <0 0x10000000 0 0x1000>;
0153 #clock-cells = <1>;
0154 };
0155
0156 infracfg_ao: clock-controller@10001000 {
0157 compatible = "mediatek,mt6779-infracfg_ao", "syscon";
0158 reg = <0 0x10001000 0 0x1000>;
0159 #clock-cells = <1>;
0160 };
0161
0162 pio: pinctrl@10005000 {
0163 compatible = "mediatek,mt6779-pinctrl", "syscon";
0164 reg = <0 0x10005000 0 0x1000>,
0165 <0 0x11c20000 0 0x1000>,
0166 <0 0x11d10000 0 0x1000>,
0167 <0 0x11e20000 0 0x1000>,
0168 <0 0x11e70000 0 0x1000>,
0169 <0 0x11ea0000 0 0x1000>,
0170 <0 0x11f20000 0 0x1000>,
0171 <0 0x11f30000 0 0x1000>,
0172 <0 0x1000b000 0 0x1000>;
0173 reg-names = "gpio", "iocfg_rm",
0174 "iocfg_br", "iocfg_lm",
0175 "iocfg_lb", "iocfg_rt",
0176 "iocfg_lt", "iocfg_tl",
0177 "eint";
0178 gpio-controller;
0179 #gpio-cells = <2>;
0180 gpio-ranges = <&pio 0 0 210>;
0181 interrupt-controller;
0182 #interrupt-cells = <2>;
0183 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
0184 };
0185
0186 apmixed: clock-controller@1000c000 {
0187 compatible = "mediatek,mt6779-apmixed", "syscon";
0188 reg = <0 0x1000c000 0 0xe00>;
0189 #clock-cells = <1>;
0190 };
0191
0192 pwrap: pwrap@1000d000 {
0193 compatible = "mediatek,mt6779-pwrap";
0194 reg = <0 0x1000d000 0 0x1000>;
0195 reg-names = "pwrap";
0196 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
0197 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>;
0198 clock-names = "spi", "wrap";
0199 };
0200
0201 devapc: devapc@10207000 {
0202 compatible = "mediatek,mt6779-devapc";
0203 reg = <0 0x10207000 0 0x1000>;
0204 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
0205 clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
0206 clock-names = "devapc-infra-clock";
0207 };
0208
0209 uart0: serial@11002000 {
0210 compatible = "mediatek,mt6779-uart",
0211 "mediatek,mt6577-uart";
0212 reg = <0 0x11002000 0 0x400>;
0213 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
0214 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
0215 clock-names = "baud", "bus";
0216 status = "disabled";
0217 };
0218
0219 uart1: serial@11003000 {
0220 compatible = "mediatek,mt6779-uart",
0221 "mediatek,mt6577-uart";
0222 reg = <0 0x11003000 0 0x400>;
0223 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
0224 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
0225 clock-names = "baud", "bus";
0226 status = "disabled";
0227 };
0228
0229 uart2: serial@11004000 {
0230 compatible = "mediatek,mt6779-uart",
0231 "mediatek,mt6577-uart";
0232 reg = <0 0x11004000 0 0x400>;
0233 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
0234 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
0235 clock-names = "baud", "bus";
0236 status = "disabled";
0237 };
0238
0239 audio: clock-controller@11210000 {
0240 compatible = "mediatek,mt6779-audio", "syscon";
0241 reg = <0 0x11210000 0 0x1000>;
0242 #clock-cells = <1>;
0243 };
0244
0245 mfgcfg: clock-controller@13fbf000 {
0246 compatible = "mediatek,mt6779-mfgcfg", "syscon";
0247 reg = <0 0x13fbf000 0 0x1000>;
0248 #clock-cells = <1>;
0249 };
0250
0251 mmsys: syscon@14000000 {
0252 compatible = "mediatek,mt6779-mmsys", "syscon";
0253 reg = <0 0x14000000 0 0x1000>;
0254 #clock-cells = <1>;
0255 };
0256
0257 imgsys: clock-controller@15020000 {
0258 compatible = "mediatek,mt6779-imgsys", "syscon";
0259 reg = <0 0x15020000 0 0x1000>;
0260 #clock-cells = <1>;
0261 };
0262
0263 vdecsys: clock-controller@16000000 {
0264 compatible = "mediatek,mt6779-vdecsys", "syscon";
0265 reg = <0 0x16000000 0 0x1000>;
0266 #clock-cells = <1>;
0267 };
0268
0269 vencsys: clock-controller@17000000 {
0270 compatible = "mediatek,mt6779-vencsys", "syscon";
0271 reg = <0 0x17000000 0 0x1000>;
0272 #clock-cells = <1>;
0273 };
0274
0275 camsys: clock-controller@1a000000 {
0276 compatible = "mediatek,mt6779-camsys", "syscon";
0277 reg = <0 0x1a000000 0 0x10000>;
0278 #clock-cells = <1>;
0279 };
0280
0281 ipesys: clock-controller@1b000000 {
0282 compatible = "mediatek,mt6779-ipesys", "syscon";
0283 reg = <0 0x1b000000 0 0x1000>;
0284 #clock-cells = <1>;
0285 };
0286
0287 };
0288 };
